Design of Voltage Mode Electronically Tunable First Order All Pass Filter in ± 0 . 7 V 16 nm CNFET Technology

A novel voltage mode first order active only tuneable all pass filter (AOTAPF) circuit configuration is presented. The AOTAPF has been designed using ±0.7 V, 16 nm carbon nanotube field effect transistor (CNFET) Technology. The circuit uses CNFET based varactor and unity gain inverting amplifier (UGIA). The presented AOTAPF is realized with three N-type CNFETs and without any external passive components. It is to be noted that the realized circuit uses only two CNFETs between its supply-rails and thus, suitable for low-voltage operation. The electronic tunability is achieved by varying the voltage controlled capacitance of the employed CNFET varactor. By altering the varactor tuning voltage, a wide tunable range of pole frequency between 34.2 GHz to 56.9 GHz is achieved. The proposed circuit does not need any matching constraint and is suitable for multi-GHz frequency applications. The presented AOTAPF performance is substantiated with HSPICE simulation program for 16 nm technology-node, using the well-known Stanford CNFET model. AOTAPF simulation results verify the theory for a wide frequency-range.


Introduction
First order active all pass filter (APF) is an important analog signal processing (ASP) module. It is used for design of multiphase oscillators, phase-equalizers and high-quality-factor frequency-selective circuits. Several first order voltage mode (VM) single-ended (SE) APF circuit realizations have been reported in technical literature [1][2][3][4][5][6][7][8]. These APF circuits use a variety of efficient active-building-blocks (ABBs). However, these realized APFs are based on passive elements and large number of transistors count, which result in larger chip-area, lower slew rate, higher power dissipation and limitations to higher frequency operations. Few such APF configurations with low active and passive component counts are also available in the technical literature [9][10][11][12][13][14][15][16][17][18]. Some of these APF circuits also employ one or more ideal DC current-sources for biasing, which further increase the transistor count [15,17,18].
From the integrated circuit point of view, the active only filters (AOFs) provide several attractive advantages like capability of operating at much higher frequencies, lesser chip area, low power dissipations and electronic tunabilty. As a result, few first order AOTAPFs are reported in the technical literature [19][20][21]. These AOTAPFs use the MOSFETs transconductance and intrinsic gate to source parasitic capacitance as filter design components; still, the frequency of operations falls with in MHz range. Moreover, these reported AOTAPF circuits also contain a large number of transistors.

Carbon Nano-Tube Field Effect Transistor
Carbon nanotubes (CNTs) are graphite-cylindrical-sheets (GCSs), which are considered as the most promising material for future nano-electronic devices and applications, due to their exceptional electronic, mechanical, chemical and thermal properties. CNTs are classified as single-wall CNTs and multi-wall CNTs. Single-wall CNT is based on single GCS while multi-wall CNT consists of more than one GCS. The properties of single-wall CNT are dependent on the chirality-vector (C h ) [28,29]. The C h is defined by vector indices n 1 and n 2 , which are positive-integers. The arrangement-angle of carbon atoms along the CNT is determined by C h . The single-wall CNT can be of metallic or semiconducting behavior depending on the vector indices n 1 and n 2 . If | n 1 − n 2 | is an integer-multiple of three or n 1 = n 2 , the single-wall CNT behaves as metallic, otherwise it behaves as semiconductor. The C h , diameter (D T ) and threshold-voltage (V th ) of a CNT are related by the following equations.
C h = a n 2 1 + n 2 2 + n 1 n 2 (1) where, e is the unit-electron-charge and a is the graphene-lattice-constant with a value of 2.49A • . V π is the π to π bond-energy in tight-bonding-model with a value of 3.033 eV [30]. CNFET is one of the most attractive applications of CNT, which is obtained by replacing the MOSFET channel with one or more single-wall semiconducting CNTs as a channel material, as shown in Figure 1. Like conventional-MOSFET, CNFET is also a voltage-controlled-device and the current through the CNT based channel is controlled via gate voltage. CNFET gate is coupled capacitively with the beneath channel that consists of one or more narrow CNT. A single-CNT provides a limited amount of current.
To enhance the channel current significantly, multiple parallel CNTs are incorporated in the channel. As compared to CMOS, where the design is dependent on the aspect ratio of transistors, a CNFET is usually optimized in terms of D T , number of CNTs (N T ) and inter-CNT pitch (S T ). The S T is basically the distance between the centers of two adjacent CNTs under the same gate. The width of the CNFET gate (W g ) is determined by the following equation [35]: where, W min is the minimum gate width. The CNFET gate capacitance (C g ), is one of the key device features and it significantly affects the performance, especially at high-frequencies. The C g is composed of three different capacitive components; coupling capacitance among the gate and adjacent contacts (C gtg−t ), gate outer-fringe capacitance (C f r−t ) and gate to channel capacitance (C gc−t ). The C gc−t is further composed of two capacitances C gc−m and C gc−e , which are capacitances of single-wall CNTs located in the middle and edge of CNFET respectively. The C gc−t components are shown in Figure 2.
The CNFET gate capacitance parameters are: where, W g and L g are the CNFET channel-width and channel-length respectively. L s is the length of doped source-side extension region. C gtg is the gate-coupling capacitance per unit gate-width, C gc is the gate to channel capacitance per unit channel-length and C f r is the gate outer-fringe capacitance per unit CNT length. Comparatively to C gc and C gtg , the C f r capacitance magnitude is quite smaller and thus its effect can be ignored [35]. The C g thus can be approximated as: The drain/source capacitance (C d/s ) can be determined by following relation.
where, C sub is the capacitance between the CNFET channel and substrate, C ox is the capacitance between the CNFET gate and channel and C gd/gs is the capacitance of the CNFET gate to the drain/source contact. The ratio C sub /C ox is only important when CNFET substrate drive (switches) the gate. To assess the potential performance of CNFET, an accurate and efficient device-model is required, which incorporates typical non-idealities of CNFET device. Most available models of CNFETs in recent literature bear the drawback of ideal modeling, resulting in ignoring numerous important effects [36,37]. The Stanford CNFET model overcomes shortcomings of previous models by including several non-idealities like drain to source series resistance, interconnect wiring capacitance, finite scattering mean free path, inter CNT charge-screening-effect, effect of drain-source extension region and many more [38]. The Stanford CNFET model has been experimentally validated and it efficiently predicts the dynamic and transient performance with more than 90% accuracy [34].  Some important Stanford CNFET-model parameters are shown in Table 1.

CNFET Based UGIA
The UGIA is one of the simplest types of ABB, which employs two N-type CNFETs as shown in Figure 3a [16] and its symbol is shown in Figure 3b. Its transfer gain can be expressed as follows.
where, g m1 and g m2 are the transconductance gains of the CNFETs T 1 and T 2 respectively. With symmetrical T 1 and T 2 on the same die, the g m1 = g m2 , the Equation (10) reduces to Thus, the circuit of Figure 3a, realizes an unity gain inverting amplifier (UGIA). The UGIA equivalent parasitic-model is shown in Figure 3c. Its input and output port resistances can be expressed as where, r g represents the gate-resistance of transistor T 2 and r ds1 , r ds2 are the channel-resistances of transistors T 1 and T 2 respectively. The UGIA input port has very high-resistance. The UGIA output port, being the voltage source, exhibits small resistance. The impact of increasing CNTs (N T ) of both the CNFETs of the UGIA on its performance is studied using HSPICE simulation tool. In the simulations, the Stanford CNFET model is used for the CNFETs with transistor parameters of Table 1. Figure 4 demonstrates the impact of N T on r o , C i , C o , power dissipation and −3 dB bandwidth of the UGIA. A single CNT carries approximately a constant current of 20 µA [28]. The increase of N T of transistors increase the overall current drive capability and hence the transconductance [29]. The impact of increasing N T on UGIA r o is shown in Figure 4a. It is seen that by increasing N T , the output resistance r o decreases. Since an increase in N T is equivalent to an increase in channel width of the CNFETs, r o decreases with the increase of N T . The effects of increasing N T on input and output parasitic capacitances C i and C o of the UGIA, are shown in Figure 4b. It is observed that by increasing N T , both the parasitic capacitances C i and C o increase. Figure 4c demonstrates the effect of increasing N T on the UGIA power dissipation. The power dissipation of UGIA increases as N T increases. The current drive capability of employed CNFETs increases with an increase of N T , which leads to an increase in power dissipation. Figure 4d demonstrates the effect of increasing N T , on UGIA −3 dB bandwidth. It is observed that by increasing N T , the −3 dB bandwidth of UGIA increases.  The transient and AC-analysis were performed with CNFET parameters of Table 1, with N T = 2. Figure 5a shows the transient-response of UGIA input and output voltage at 50 GHz. Figure 5b displays the UGIA AC simulation results of voltage-gain (V o /V i ). It is seen that the obtained voltage-gain magnitude is unity over a wide range of frequency. The −3 dB frequency of employed UGIA voltage-gain is 2.1172 THz. This massive value of −3 dB cutoff frequency makes the UGIA a potential candidate for the design of high frequency ASP modules.
The UGIA parasitic capacitance C i and resistance r i are found as 3.54 aF and 1 TΩ respectively. Figure 5c displays the frequency response of UGIA output port resistance (r o ), which is constant at r o = 7.9921 kΩ over wide frequency-range. The −3 dB cutoff frequency of the UGIA output-impedance is obtained as 1.9017 THz. The UGIA output parasitic-capacitance, C o is found as 10.472 aF, which is nearly insignificant for frequency-range up to several GHz. The total-harmonic-distortion (THD) of UGIA is determined by applying a 50 GHz sinusoidal-signal to input with different voltage amplitudes. Simulation results are presented in Figure 6a. It can be seen that THD is less than 1% for sinsoidal signal with amplitude of 200 mV. Monte Carlo simulation results of the UGIA were performed for 30-trials with transient and AC-sweep environment to see the influence of process-variations. Figure 6b

AOTAPF Circuit Description
The basic scheme for first order APF section is given in Figure 7a. Its transfer function can be expressed as follows.
Its equivalent RC circuit along with a unity gain inverting amplifier is shown in Figure 7b, where pole frequency ω o = a = 1/RC. The CNFET version of Figure 7b is given in Figure 7c, where the unity gain inverting amplifier is replaced with UGIA of Figure 3a and the capacitor C is replaced with a CNFET based varactor capacitance C var between input and output. The N-Type CNFET based varactor used in Figure 7c is given in Figure 8a. Its equivalent symbol is shown in Figure 8b From Equation (15), the pole-frequency (ω o = ω z = ω p ) and the phase-angle (φ), can be expressed respectively as: The Proposed AOTAPF pole-frequency incremental sensitivity with respect to the components C var and r o can be expressed as: From Equation (18), it is observed that the incremental sensitivities of the pole-frequency (ω o ) with respect to C var and r o are within unity in magnitude. By considering the UGIA non-ideal voltage-gain (α) and parasitic resistance (r s ) of tuning control voltage (V tune ) into consideration, the VTF of Equation (15) can be expressed as follows.
From Equation (19) it is seen that the AOTAPF gain and pole-frequency (ω p ) is insensitive to α. However, the zero-frequency (ω z ) is affected slightly due to α. Moreover, the impact of source resistance (r s ) on the performance of APF is negligible due to the presence of high valued output resistance (r o ) of the UGIA (r o r s ). Thus, the effect of r s can be ignored. By considering α into account, the non-ideal phase-angle for the realized filter can be expressed as follows.
Thus, it is seen from Equation (20) that the phase-angle is slightly affected by α. To examine the high-frequency performance of the realized AOTAPF, the UGIA parasitic impedances must be evaluated. By considering the α and non-ideal parasitic impedances of UGIA, the ideal VTF of the realized AOTAPF as illustrated by Equation (15) turns out to be From Equation (21), the ω z and ω p can be written as It is evident from Equation (22) that the non-ideal factor α sightly affects the zero-frequency. In addition, it can be noticed from Equation (23) that UGIA parasitic capacitance C o affects the pole-frequency. The influence of the C o on the performance of the AOTAPF can be minimized by making C var C o .

Design and Verification
To verify the proposed AOTAPF circuit, it is designed and simulated using HSPICE simulation tool with the Stanford CNFET model parameters of Table 1. Based on Equation (21), the value of the varactor capacitance (C var ) is to be set sufficiently higher than the parasitic capacitance (C o ), to evade the mismatch between zero and pole frequencies as well as non-unity gain for higher frequencies design. Figure 9 shows the capacitance tuning characteristics (C-V curves) of the realized CNFET varactor of Figure 8a, with different values of N T . It has been observed that by increasing N T , the capacitance spread (C max − C min ), increases, which ultimately determines the frequency tuning range of AOTAPF. The C-V relationship approximated by polynomial curve fitting is given in Appendix A. For instance, with N T = 100 and by setting V tune = −0.32 V for CNFET T 3 , the observed C var is 0.40423 fF. Thus, with r o = 7.9921 kΩ, Equation (16) Figure 10, where a phase shift of 90 • is evident. Figure 11a,b show the ideal and simulated magnitude and phase responses respectively. The proposed AOTAPF power dissipation is found to be 33.76 µW. It is noticed that the realized APF dissipates very small power, even at very high frequency of operation. Figure 12 shows the equivalent input and output noises against the frequency. It is noticed that the equivalent input noise and output noise for the realized AOTAPF at a designed pole-frequency of 49.26 GHz are found as 6.822 nv/Hz and 6.761 nv/Hz respectively, which are satisfactorily low values. Monte Carlo simulation results of AOTAPF were performed for 30-trials with transient and AC-sweep environment to see the influence of process-variations.     Next, to demonstrate the proposed circuit tunabilty feature, different tuning voltages (V tune ) are applied to the varactor. By varying the V tune from −0.5 V to −0.3 V the varactor capacitance (C var ) varies in the range of 0.574 fF to 0.346 fF respectively. Figure 14a,b demonstrate the magnitude and phase responses respectively of the realized AOTAPF, at different values of V tune . It is noticed from Figure 14b that by varying the V tune from −0.5 V to −0.3 V, the pole frequency of the proposed filter varies in the range of 34.2 GHz to 56.9 GHz. This wide range of pole frequency by adjusting V tune makes the proposed circuit as a potential candidate for multi GHz applications. The transient responses of the proposed filter for different tune voltages are shown in Figure 15. A phase shift of 90 • is noticed for each pole frequency. The THD variations are found as 3.81%, 2.6% and 1.72% for V tune equal to −0.30 V, −0.33 V and −0.50 V respectively. Thus, all the simulation results on the proposed AOTAPF support the theory.

Performance Comparison of the Proposed APF
A brief comparison of the proposed AOTAPF with other available VM SE tunable APF circuit configurations is given in the Table 2. For comparison, only APFs realized with not more than 10 transistors are chosen. The APFs of [12][13][14][15][16][17][18] employ one or more external passive components, which result in occupying larger chip area and also suffer from slew rate limitations as well as wide tolerance. However, the proposed AOTAPF is free from any external passive component. The APFs presented in [15,[17][18][19][20][21] utilize one or more DC current sources for tunability of pole frequency via altering biasing current. However, additional transistors need to be employed for realization of these DC current supplies and thus the transistor count will further increase. It is to be noted like previously presented APFs of [14,15], that the proposed AOTAPF is also suitable for low voltage operation as it employs only two active devices between its supply rails. The proposed AOTAPF circuit configuration is based on only three transistors, while the realized AOTAPF circuits of [19][20][21] use several transistors as they utilize ideal current sources. Although, the previously presented APF circuits of [14,18] are also based on three transistors like the proposed AOTAPF, but they use one or more external passive components. In addition, the reported APF of [18] uses an ideal DC current source which will ultimately increase the transistor count. Table 2 shows that the CMOS-based APF circuit configurations are limited to MHz range while the proposed circuit operates in several GHz ranges.

Conclusions
In this paper, a new single ended voltage mode first order all pass filter using CNFET based unity gain inverting amplifier and a varactor is presented. The proposed circuit is constructed with only three N-type CNFETs and thus it consumes very little area on chip. Since there are only two CNFETs stacked between the power-supply rails, it is able to work equally well at low voltages. The realized all pass filter circuit is free from external passive components and thus it is suitable for integrated circuit implementation. The proposed AOTAPF circuit non-ideal performance is also evaluated. The filter circuit is designed and verified with HSPICE, using the well-known Stanford CNFET model.
Initially, the CNFET-based unity gain inverting amplifier is studied for different numbers of CNTs. It was observed that with only two CNTs, the unity gain inverting amplifier yields optimal performance. Afterward, the CNFET-based varactor is simulated for different CNTs and variable DC voltages. This study enables the designer to choose the number of CNTs for the desired frequency range of operation. Then the realized AOTAPF circuit is studied in detail including gain, phase, and transient performance. The Monte Carlo analysis for process variations as well as THD simulation studies were also performed. The simulation results show a very good gain and phase characteristics at high frequencies with tunable pole-frequency range from 34.2 GHz to 56.9 GHz. This makes the proposed topology a potential contestant for high frequency applications. It will be interesting to substantiate the all pass filter simulation results experimentally; however, due to the current non-availability of needed resources, experimental authentication is not performed. Physical realization of the presented AOTAPF may be a vital-direction for future extension of the proposed work.

Conflicts of Interest:
The authors declare no conflict of interest.

Abbreviations
The following abbreviations are used in this manuscript:

Appendix A
The capacitance tuning characteristics (C-V curves) of the realized CNFET varactor of Figure 8a, are obtained by sweeping the V tune from −0.7 V to +0.7 V for different N Ts using HSPICE simualtion tool. The analytical relationship between the capacitance C var and the control voltage V tune can be obtained by polynomial curve fitting for fixed N T . For N T = 100, the C-V relationship is approximated by following 2nd order polynomial expression: