A 2 . 5-GHz 1V High Efficiency CMOS Power Amplifier IC with a Dual-Switching Transistor and Third Harmonic Tuning Technique

This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-μm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.


Introduction
For modern communication systems, such as short-range wireless applications, a high-efficiency power amplifier plays an important role in maintaining the battery life.To increase the efficiency, switching-mode amplifiers, such as class-E and class-F, are widely used [1][2][3][4].By minimizing the overlap between the drain current and voltage waveforms, the dc power dissipation of the amplifiers can be diminished.The output power of switching-mode amplifiers is also comparable to current-mode ones for the same device peak voltage and current [5].
Unfortunately, efficiency and supply voltage represent a trade-off in switching-mode power amplifiers (PAs).Several techniques have been proposed for improving efficiency at low supply voltages [6][7][8][9][10][11].The fully integrated PAs with a power combiner, such as multiple LC baluns [6], a transformer [7], and a distributed active transformer [8,9], were proposed to boost the power added efficiency (PAE) at low supply voltages.PAE is the ratio of the produced signal power (the difference between the output and input power) and the dc power consumption.However, large combiners lead to high insertion losses and enlarge the chip size.Another approach to increase the efficiency of a low supply voltage PA is an injection-locking technique [10,11].Although this technique provides high gain and high efficiency, the circuit is complicated.
The harmonic manipulation techniques, such as class-J [12] and a tuned amplifier [13][14][15], are also attractive to improve efficiency.However, class-J employs only second harmonic tuning at the output port, while the tuned amplifier in [15] utilizes second and third harmonic tuning at the input and output ports.Both of the techniques increase the fundamental output power with high efficiency.The amplifier using a second harmonic short in [16] has a higher output power capability of 6.6% than the conventional class-E amplifier.However, the peak drain voltage increases significantly.
In this work, a high-efficiency CMOS PA IC operating at a low supply voltage is proposed using 0.18-µm CMOS technology.To boost the PAE, a dual-switching transistor (DST) was adopted in combination with a third harmonic tuning technique [17].The class-E PA topology was employed as a basic structure, and 0.5-V positive, back-gate voltage was injected for low-voltage operation.A detailed theoretical and circuit analysis was performed, and the optimum circuit parameters were derived.
This paper is organized as follows.In Section 2, the circuit analysis of the proposed configuration is described, and the optimum circuit parameters are derived.Section 3 shows the simulation results of the proposed PA.Section 4 discusses the measurement results and compares them with recently reported PAs.Our conclusions are presented in Section 5.

Dual-Switching Transistor (DST)
Figure 1a,b show the operation principle and the input/output characteristics of the DST structure, respectively.The structure consists of two switching transistors: (1) the primary switching transistor M 1 biased at class-AB and (2) the secondary switching transistor M 2 biased at class-B, which are connected in parallel.Only single input and output matching circuits were employed, thus providing less complexity for the single chip implementation.To realize the class-AB operation of M 1 , the positive back-gate voltage V bg was injected.Hence, the threshold voltage decreased so that the overdrive voltage of M 1 would be sufficient for the class-AB operation.
Electronics 2019, 8, x FOR PEER REVIEW 2 of 15 The amplifier using a second harmonic short in [16] has a higher output power capability of 6.6% than the conventional class-E amplifier.However, the peak drain voltage increases significantly.
In this work, a high-efficiency CMOS PA IC operating at a low supply voltage is proposed using 0.18-µm CMOS technology.To boost the PAE, a dual-switching transistor (DST) was adopted in combination with a third harmonic tuning technique [17].The class-E PA topology was employed as a basic structure, and 0.5-V positive, back-gate voltage was injected for low-voltage operation.A detailed theoretical and circuit analysis was performed, and the optimum circuit parameters were derived.
This paper is organized as follows.In Section 2, the circuit analysis of the proposed configuration is described, and the optimum circuit parameters are derived.Section 3 shows the simulation results of the proposed PA.Section 4 discusses the measurement results and compares them with recently reported PAs.Our conclusions are presented in Section 5.At small input power (Pin < P1), the total output power is mainly contributed by M1 (Pout = Pout1), because M1 is in active operation.In this condition, the total dissipation power PDC of the amplifier is equal to VddId1.

Circuit Analysis
At large input power (Pin > P1), both of the switching transistors are active.M1 operates near the saturation power level and corresponds to its output power (Pout1 = Psat1), while M2 delivers the output power of Pout2.Therefore, the total output power of the amplifier Pout is the sum of the two transistors (Psat1 + Pout2).To maximize the PAE, the size of M2 is set to be sufficiently smaller than M1, hence the id2 << id1 and PDC is expected to be slightly higher than VddId1.The overlapping between the drain voltage and current waveforms of the DST should be minimized by adjusting the conduction angle of M2.Consequently, the PAE at the saturation power level is approximately represented as follows: At small input power (P in < P 1 ), the total output power is mainly contributed by M 1 (P out = P out1 ), because M 1 is in active operation.In this condition, the total dissipation power P DC of the amplifier is equal to V dd I d1 .
At large input power (P in > P 1 ), both of the switching transistors are active.M 1 operates near the saturation power level and corresponds to its output power (P out1 = P sat1 ), while M 2 delivers the output power of P out2 .Therefore, the total output power of the amplifier P out is the sum of the two transistors (P sat1 + P out2 ).To maximize the PAE, the size of M 2 is set to be sufficiently smaller than M 1 , hence the i d2 << i d1 and P DC is expected to be slightly higher than V dd I d1 .The overlapping between the drain voltage and current waveforms of the DST should be minimized by adjusting the conduction angle of M 2 .Consequently, the PAE at the saturation power level is approximately represented as follows: In addition, the additional gain expansion generated at the saturation power level by the DST (shaded area in Figure 1b) improves the linearity of the amplifier, P b > P a , where P b is the input P1dB of the proposed amplifier and P a is the input P1dB of the conventional class-AB amplifier.

Third Harmonic Tuning Technique
The third harmonic tuning technique shapes the voltage and current waveforms of the switching transistor at the drain node to minimize the dc power dissipation [18].The technique is realized by connecting a series C 3 -L 3 resonated at 3f o to the output node of the conventional class-E amplifier, as shown in Figure 2. Due to the resonator C 3 -L 3 , under specified conditions, the third harmonic component of the drain voltage and current waveforms can be controlled.(1) In addition, the additional gain expansion generated at the saturation power level by the DST (shaded area in Figure 1b) improves the linearity of the amplifier, Pb > Pa, where Pb is the input P1dB of the proposed amplifier and Pa is the input P1dB of the conventional class-AB amplifier.

Third Harmonic Tuning Technique
The third harmonic tuning technique shapes the voltage and current waveforms of the switching transistor at the drain node to minimize the dc power dissipation [18].The technique is realized by connecting a series C3-L3 resonated at 3fo to the output node of the conventional class-E amplifier, as shown in Figure 2. Due to the resonator C3-L3, under specified conditions, the third harmonic component of the drain voltage and current waveforms can be controlled.Based on a zero-voltage switching (ZVS) condition, a series of mathematical analyses was conducted to describe the operation principle of the amplifier with the third harmonic tuning circuit.The following assumptions were considered: (1) the transistor is an ideal switch, and (2) all passive elements are lossless and linear.For the operation, the transistor was driven at frequency fo and at 50% of the duty cycle (on at 0≤ ωt < π and off at π ≤ ωt <2π).
The loaded Q-factor of C1-L1 and C3-L3 were assumed to be infinite.The fundamental output current IRF and the third harmonic current I3 are represented as follows: (3)

On-State Condition, 0≤ ωt < π
When the switch is turned on, the current flowing to the capacitor ic is equal to 0. Therefore, the capacitor voltage vc is equal to 0. At this interval, the current that flows to the switch isw is given by Based on a zero-voltage switching (ZVS) condition, a series of mathematical analyses was conducted to describe the operation principle of the amplifier with the third harmonic tuning circuit.The following assumptions were considered: (1) the transistor is an ideal switch, and (2) all passive elements are lossless and linear.For the operation, the transistor was driven at frequency fo and at 50% of the duty cycle (on at 0≤ ωt < π and off at π ≤ ωt <2π).
The loaded Q-factor of C 1 -L 1 and C 3 -L 3 were assumed to be infinite.The fundamental output current I RF and the third harmonic current I 3 are represented as follows: i RF (ωt) = I RF sin(ωt + θ). (2) Electronics 2019, 8, 69 4 of 15

On-State Condition, 0≤ ωt < π
When the switch is turned on, the current flowing to the capacitor i c is equal to 0. Therefore, the capacitor voltage v c is equal to 0. At this interval, the current that flows to the switch i sw is given by where I L and θ denote the dc current and the initial phase angle, respectively.Due to the characteristics of the shunt capacitor C s , the initial current of i sw during the on/off transition is zero.Hence, the following is true: When the switch is turned off, i sw is equal to 0. Therefore, i c can be defined as follows, generating the voltage across the capacitor v c as, To solve the above equations, it is assumed that the real part of the third harmonic output impedance Z 3 is equal to zero.The Fourier series analyses for v c (ωt) and i o (ωt) are derived to obtain the third harmonic component.Note that i o (ωt) is the sum of i RF (ωt) and i 3 (ωt), i.e., i o (ωt) = I RF sin(ωt + θ) + I 3 sin(3ωt). ( The third harmonic coefficient of v c is given by The third harmonic coefficient of i o is expressed as Substituting Equations ( 7)-( 10), Z 3 can be obtained as Setting the real part of Z 3 to zero and substituting Equation ( 5) for Equation ( 11) yields the following: Electronics 2019, 8, 69 5 of 15 The initial phase angle (θ) can be obtained by deriving the third harmonic coefficient of i sw , as follows: At the initial condition i sw (0) = 0, we have the following: Substituting Equation (12) with Equation ( 14) generates the initial phase angle θ of −35 • .Thus, the ratio I L /I RF of 0.57 and I L /I 3 of 2.34 are obtained.
Considering that 100% efficiency is realized when the total output power is equal to the dc power consumption, the following is true: where V DD can be defined by applying the Fourier series expansion to Equation ( 7), i.e., To realize a good switching condition, the optimum shunt capacitor C s can be determined by substituting Equation ( 16) with Equation (15): In the circuit implementation, C s is set as the total external capacitance and output capacitance of the switching transistor.

Switching Waveforms
The normalized switching waveforms of drain current i sw (ωt) for 0≤ ωt < π and drain voltage v c (ωt) for π ≤ ωt <2π are given by using Equations ( 4), (7), and ( 16) and the ratio of I L /I RF and I L /I 3 as follows: i sw (ωt) Figure 3 illustrates the normalized drain voltage (dotted line) and current waveforms (solid line) during a time period T. Because the transistor is turned on at 0≤ T < T/2, there is no voltage across the switch and the current flowing to the switch consists of dc, fundamental, and the third harmonic components.Because the transistor is turned off at T/2 ≤ T < T, all the currents flow to the shunt capacitor C s .As shown in Figure 3, the third harmonic tuning technique flattens the waveforms and reduces the overlapping.Therefore, it is expected to achieve low dc power dissipation and high PAE.Because the technique only controls a single harmonic component at the output node, it offers a more suitable structure for single chip PA solutions than class F or class F −1 .Compared with the conventional class-E PA [19] and the second harmonic tuning PA [16], the PA with third harmonic tuning technique has a lower peak voltage waveform.The voltage stress of the switching transistor is reduced, and it is expected to get higher output power capability.For the CMOS process, the output power capability Pc calculates the maximum achievable output power for a given voltage stress Vpeak and rms drain current Irms and is expressed as follows: The resonator C3-L3 induces a parasitic capacitance at the fundamental frequency and reduces the impedance at the output port.As a result, the loaded Q-factor of C1-L1, which is resonated at fo, is decreased.The third harmonic resonator is designed by choosing an inductor with a high Q-factor at 3fo as L3.To compromise with the overall chip area and insertion loss, the layout dimension of the inductor is optimized.Then, the series capacitance C3 is defined by the equation C3 = 1/9(πfo) 2 L3.The parasitic capacitance of the resonator should be minimized to maintain the optimum shunt capacitance Cs of the amplifier.Consequently, by selecting the Q-factor of 10, the third harmonic resonator is optimized to L3 = 2.5 nH and C3 =180 fF.

Back-Gate Bias Technique
The back-gate bias technique is a method to modify the threshold voltage level and the onresistance (Ron) of the MOSFET by connecting the body terminal to the positive or negative voltage.In this paper, a positive back-gate voltage was applied at the body of M1 so that the threshold voltage and the Ron decreased.The technique led to the p-well of the body and n+ of the source being connected in a forward bias condition.Therefore, the positive back-gate bias voltage selection is very important to minimize an excessive dc leakage current from the body to the source [20].A solid backgate body potential should have an ideal connection to the ground, hence a large by-pass capacitance is placed between the body and the ground.Figure 4 shows the comparison between the positive back-gate voltage versus the threshold voltage at 0.5-V bias voltage.Compared with the conventional class-E PA [19] and the second harmonic tuning PA [16], the PA with third harmonic tuning technique has a lower peak voltage waveform.The voltage stress of the switching transistor is reduced, and it is expected to get higher output power capability.For the CMOS process, the output power capability P c calculates the maximum achievable output power for a given voltage stress V peak and rms drain current I rms and is expressed as follows: The resonator C 3 -L 3 induces a parasitic capacitance at the fundamental frequency and reduces the impedance at the output port.As a result, the loaded Q-factor of C 1 -L 1 , which is resonated at f o , is decreased.The third harmonic resonator is designed by choosing an inductor with a high Q-factor at 3f o as L 3 .To compromise with the overall chip area and insertion loss, the layout dimension of the inductor is optimized.Then, the series capacitance C 3 is defined by the equation The parasitic capacitance of the resonator should be minimized to maintain the optimum shunt capacitance C s of the amplifier.Consequently, by selecting the Q-factor of 10, the third harmonic resonator is optimized to L 3 = 2.5 nH and C 3 =180 fF.

Back-Gate Bias Technique
The back-gate bias technique is a method to modify the threshold voltage level and the on-resistance (R on ) of the MOSFET by connecting the body terminal to the positive or negative voltage.In this paper, a positive back-gate voltage was applied at the body of M 1 so that the threshold voltage and the R on decreased.The technique led to the p-well of the body and n+ of the source being connected in a forward bias condition.Therefore, the positive back-gate bias voltage selection is very important to minimize an excessive dc leakage current from the body to the source [20].A solid back-gate body potential should have an ideal connection to the ground, hence a large by-pass capacitance is placed between the body and the ground.Figure 4 shows the comparison between the positive back-gate voltage versus the threshold voltage at 0.5-V bias voltage.

Circuit Configuration of the Proposed PA
Figure 5a shows the circuit schematic of the proposed CMOS PA IC.To achieve high PAE at a low supply voltage, a combination of the DST and the third harmonic tuning circuit (C3-L3) is proposed.The supply voltage Vdd of 1 V was applied with the bias voltage Vbias of 0.5 V.In addition, a 0.5-V positive body bias was injected into the body terminal (B) of M1 by the external biasing terminal (Vbg) to decrease the threshold voltage level of 75 mV, which was optimum for the class-AB operation when there was no input power.In addition, the body of M2 was connected to the ground for the class-B operation.The RC feedback network was employed to modify the input and the output resistance for the impedance matching requirement, as well as to increase the stability of the device; hence, the PA was always unconditionally stable. (a)

Circuit Configuration of the Proposed PA
Figure 5a shows the circuit schematic of the proposed CMOS PA IC.To achieve high PAE at a low supply voltage, a combination of the DST and the third harmonic tuning circuit (C 3 -L 3 ) is proposed.The supply voltage V dd of 1 V was applied with the bias voltage V bias of 0.5 V.In addition, a 0.5-V positive body bias was injected into the body terminal (B) of M 1 by the external biasing terminal (V bg ) to decrease the threshold voltage level of 75 mV, which was optimum for the class-AB operation when there was no input power.In addition, the body of M 2 was connected to the ground for the class-B operation.The RC feedback network was employed to modify the input and the output resistance for the impedance matching requirement, as well as to increase the stability of the device; hence, the PA was always unconditionally stable.

Circuit Configuration of the Proposed PA
Figure 5a shows the circuit schematic of the proposed CMOS PA IC.To achieve high PAE at a low supply voltage, a combination of the DST and the third harmonic tuning circuit (C3-L3) is proposed.The supply voltage Vdd of 1 V was applied with the bias voltage Vbias of 0.5 V.In addition, a 0.5-V positive body bias was injected into the body terminal (B) of M1 by the external biasing terminal (Vbg) to decrease the threshold voltage level of 75 mV, which was optimum for the class-AB operation when there was no input power.In addition, the body of M2 was connected to the ground for the class-B operation.The RC feedback network was employed to modify the input and the output resistance for the impedance matching requirement, as well as to increase the stability of the device; hence, the PA was always unconditionally stable.(a) To minimize the drain loss, a large transistor size was selected.The large size, however, decreased the gain and increased the input power.In this work, the optimized total gate width of 464-µm with a gate length of 0.18-µm was utilized to obtain the power gain higher than 10 dB at 2.5-GHz.Because a large transistor size leads to high output capacitance, the shunt capacitor CS was selected by considering the total output capacitance of the DST.Furthermore, the small inductor LO was inserted at the output for impedance matching.
To verify the effectiveness of the proposed configuration, a 2.5-GHz conventional class-E PA was designed as illustrated in Figure 5b.The size of the switching transistor M was set equal to the total size of the switching transistors in the proposed PA.The 0.5-V back-gate voltage Vbg was injected, and the switching transistor was biased at class-AB with 1-V supply voltage

Simulation Results
The prototype of the proposed circuits was designed and fabricated using six metal layer (1P6M) 0.18-µm CMOS technology by TSMC.This CMOS process offered two ultra-thick top metal layers, 4µm or 2-µm thick, for inductor implementation.High-density MIM capacitors of 1fF/µm 2 and 2fF/µm 2 were also provided.For noise isolation from the P-substrate, deep n-wells were available.
The small-signal and large-signal responses of the proposed PA IC were simulated on a wafer using ADS 2011 by Keysight [21] and Virtuoso ADE IC 6.1.5by Cadence [22].Input and output matching circuits were simulated and optimized using Momentum EM simulation in ADS 2011, while layout and verification were performed by Virtuoso ADE IC 6.1.5,respectively.
Figure 6 illustrates the small-signal input-output response of the proposed PA IC.The S11 and the S22 are −13.9dB and −12.5 dB at 2.5 GHz, respectively.The maximum S21 is 11.2 dB with a 3-dB bandwidth from 1.65 GHz to 3.8 GHz.
Because the third harmonic tuning technique was very effective to decrease the dc power consumption, it is expected that the proposed CMOS PA has high efficiency.Figure 7 shows the simulated dc drain current of the proposed PA IC (solid line) and the conventional PA IC (dotted line) versus the input power.The proposed CMOS PA exhibited a lower dc current than the conventional one under small-signal conditions.
Figure 8 shows the simulated input-output response of the proposed and conventional class-E PAs with sweeping the input power.It confirmed that the proposed PA IC achieves better gain linearity with better PAE than the conventional class-E PA IC.At an input power of lower than -10 dBm, M2 was turned off and the input signal was mainly amplified by M1.When the input power increased, the output power of M2 became higher to compensate for the gain compression of M1, To minimize the drain loss, a large transistor size was selected.The large size, however, decreased the gain and increased the input power.In this work, the optimized total gate width of 464-µm with a gate length of 0.18-µm was utilized to obtain the power gain higher than 10 dB at 2.5-GHz.Because a large transistor size leads to high output capacitance, the shunt capacitor C S was selected by considering the total output capacitance of the DST.Furthermore, the small inductor L O was inserted at the output for impedance matching.
To verify the effectiveness of the proposed configuration, a 2.5-GHz conventional class-E PA was designed as illustrated in Figure 5b.The size of the switching transistor M was set equal to the total size of the switching transistors in the proposed PA.The 0.5-V back-gate voltage V bg was injected, and the switching transistor was biased at class-AB with 1-V supply voltage

Simulation Results
The prototype of the proposed circuits was designed and fabricated using six metal layer (1P6M) 0.18-µm CMOS technology by TSMC.This CMOS process offered two ultra-thick top metal layers, 4-µm or 2-µm thick, for inductor implementation.High-density MIM capacitors of 1fF/µm 2 and 2fF/µm 2 were also provided.For noise isolation from the P-substrate, deep n-wells were available.
The small-signal and large-signal responses of the proposed PA IC were simulated on a wafer using ADS 2011 by Keysight [21] and Virtuoso ADE IC 6.1.5by Cadence [22].Input and output matching circuits were simulated and optimized using Momentum EM simulation in ADS 2011, while layout and verification were performed by Virtuoso ADE IC 6.1.5,respectively.
Figure 6 illustrates the small-signal input-output response of the proposed PA IC.The S 11 and the S 22 are −13.9dB and −12.5 dB at 2.5 GHz, respectively.The maximum S 21 is 11.2 dB with a 3-dB bandwidth from 1.65 GHz to 3.8 GHz.
Because the third harmonic tuning technique was very effective to decrease the dc power consumption, it is expected that the proposed CMOS PA has high efficiency.Figure 7 shows the simulated dc drain current of the proposed PA IC (solid line) and the conventional PA IC (dotted line) versus the input power.The proposed CMOS PA exhibited a lower dc current than the conventional one under small-signal conditions.
Figure 8 shows the simulated input-output response of the proposed and conventional class-E PAs with sweeping the input power.It confirmed that the proposed PA IC achieves better gain linearity with better PAE than the conventional class-E PA IC.At an input power of lower than -10 dBm, M 2 was turned off and the input signal was mainly amplified by M 1 .When the input power increased, the output power of M 2 became higher to compensate for the gain compression of M 1 , achieving a higher linear performance.From the simulation, it was shown that the proposed PA had a power gain of 11.5 dB, an output P1dB of 8.1 dBm, and a peak PAE of 38.5%.
Electronics 2019, 8, x FOR PEER REVIEW 9 of 15 achieving a higher linear performance.From the simulation, it was shown that the proposed PA had a power gain of 11.5 dB, an output P1dB of 8.1 dBm, and a peak PAE of 38.5%.Electronics 2019, 8, x FOR PEER REVIEW 9 of 15 achieving a higher linear performance.From the simulation, it was shown that the proposed PA had a power gain of 11.5 dB, an output P1dB of 8.1 dBm, and a peak PAE of 38.5%.Electronics 2019, 8, x FOR PEER REVIEW 9 of 15 achieving a higher linear performance.From the simulation, it was shown that the proposed PA had a power gain of 11.5 dB, an output P1dB of 8.1 dBm, and a peak PAE of 38.5%.

Measurement Results
The chip photograph of the proposed PA IC is depicted in Figure 9.The proposed PA was designed in 0.18-µm CMOS technology and measured on a wafer.The chip size is 0.9-mm by 1.1-mm.Figure 10 shows the measurement setup and probing situation of the proposed CMOS PA IC.The chip was probed using Summit 11201B Cascade Microtech with a single-ended GSG probe at the input and output RF signals.The RF input was generated using an Agilent E8267D vector signal generator, while the dc source was provided by using Yokogawa GS200.
generator, while the dc source was provided by using Yokogawa GS200.
In the measurement process, 5 chips were measured for whole data variations, i.e., dc, smallsignal, and large-signal performances.The average of the standard deviation of the IDS measurement was 0.03 mA, and the averages of the standard deviations of S11, S21, and S22 were 0.05 dB, 0.06 dB, and 0.1 dB, respectively.To demonstrate the uniformity performance of the PA chips, the IDS characteristics of chip 00 and chip 20 over the supply voltage (Vdd), bias voltage (Vbias), and back-gate voltage (Vbg) variations are illustrated in Figure 11.
In order to demonstrate the small-signal performance based on S-parameters, the output RF was measured using the Agilent E8361A vector network analyzer.Figure 12 illustrates the comparison between the measured small-signal S-parameters (solid line) and the simulated small-signal Sparameters (dashed line) of the proposed circuits at 1 V of supply voltage.The quiescent current was 14.31 mA at 0.5 V of gate bias voltage.As expected, the measured S11 and S22 at 2.5 GHz were lower than −10 dB.The maximum small signal gain was 11.0 dB at 2.5 GHz with a 3-dB bandwidth from 1.7 GHz to 4.1 GHz. Figure 12 shows that measurement results agree well with the simulation results.The chip was probed using Summit 11201B Cascade Microtech with a single-ended GSG probe at the input and output RF signals.The RF input was generated using an Agilent E8267D vector signal generator, while the dc source was provided by using Yokogawa GS200.
In the measurement process, 5 chips were measured for whole data variations, i.e., dc, smallsignal, and large-signal performances.The average of the standard deviation of the IDS measurement was 0.03 mA, and the averages of the standard deviations of S11, S21, and S22 were 0.05 dB, 0.06 dB, and 0.1 dB, respectively.To demonstrate the uniformity performance of the PA chips, the IDS characteristics of chip 00 and chip 20 over the supply voltage (Vdd), bias voltage (Vbias), and back-gate voltage (Vbg) variations are illustrated in Figure 11.
In order to demonstrate the small-signal performance based on S-parameters, the output RF was measured using the Agilent E8361A vector network analyzer.Figure 12 illustrates the comparison between the measured small-signal S-parameters (solid line) and the simulated small-signal Sparameters (dashed line) of the proposed circuits at 1 V of supply voltage.The quiescent current was 14.31 mA at 0.5 V of gate bias voltage.As expected, the measured S11 and S22 at 2.5 GHz were lower than −10 dB.The maximum small signal gain was 11.0 dB at 2.5 GHz with a 3-dB bandwidth from 1.7 GHz to 4.1 GHz. Figure 12 shows that measurement results agree well with the simulation results.In the measurement process, 5 chips were measured for whole data variations, i.e., dc, small-signal, and large-signal performances.The average of the standard deviation of the I DS measurement was 0.03 mA, and the averages of the standard deviations of S 11 , S 21 , and S 22 were 0.05 dB, 0.06 dB, and 0.1 dB, respectively.To demonstrate the uniformity performance of the PA chips, the I DS characteristics of chip 00 and chip 20 over the supply voltage (V dd ), bias voltage (V bias ), and back-gate voltage (V bg ) variations are illustrated in Figure 11.The measurement results of the power gain and the output power of the proposed CMOS PA IC are shown in Figure 13.To measure the output power, an Agilent E4448A spectrum analyzer was utilized.At a supply voltage of 1 V, the proposed PA achieved a saturated output power of 10.1 dBm and an output P1dB of 8.0 dBm. Figure 14 illustrates the measurement results of the PAE of the proposed PA (solid line) and the conventional class-E PA (dotted line) at 1 V of supply voltage.The proposed PA achieved a higher PAE than the conventional PA, with a peak PAE of 34.5%.In order to demonstrate the small-signal performance based on S-parameters, the output RF was measured using the Agilent E8361A vector network analyzer.Figure 12 illustrates the comparison between the measured small-signal S-parameters (solid line) and the simulated small-signal S-parameters (dashed line) of the proposed circuits at 1 V of supply voltage.The quiescent current was 14.31 mA at 0.5 V of gate bias voltage.As expected, the measured S 11 and S 22 at 2.5 GHz were lower than −10 dB.The maximum small signal gain was 11.0 dB at 2.5 GHz with a 3-dB bandwidth from 1.7 GHz to 4.1 GHz. Figure 12 shows that measurement results agree well with the simulation results.The measurement results of the power gain and the output power of the proposed CMOS PA IC are shown in Figure 13.To measure the output power, an Agilent E4448A spectrum analyzer was utilized.At a supply voltage of 1 V, the proposed PA achieved a saturated output power of 10.1 dBm and an output P1dB of 8.0 dBm. Figure 14 illustrates the measurement results of the PAE of the proposed PA (solid line) and the conventional class-E PA (dotted line) at 1 V of supply voltage.The proposed PA achieved a higher PAE than the conventional PA, with a peak PAE of 34.5%.The measurement results of the power gain and the output power of the proposed CMOS PA IC are shown in Figure 13.To measure the output power, an Agilent E4448A spectrum analyzer was utilized.At a supply voltage of 1 V, the proposed PA achieved a saturated output power of 10.1 dBm and an output P1dB of 8.0 dBm. Figure 14 illustrates the measurement results of the PAE of the proposed PA (solid line) and the conventional class-E PA (dotted line) at 1 V of supply voltage.The proposed PA achieved a higher PAE than the conventional PA, with a peak PAE of 34.5%.Figure 15 shows the measurement results of the output power and the P1dB of the proposed PA (solid line) and the conventional class-E PA (dotted line) versus the supply voltage variations from 0.5 V to 1.2 V.The proposed PA achieved larger saturated output power and P1dB than did the conventional PA.The dependency of the efficiency performances (drain efficiency (DE) and PAE) on the supply voltage is illustrated in Figure 16.The proposed PA achieved higher efficiency than the conventional PA at low-voltage operation.Because the load line was adjusted to obtain high efficiency at a supply voltage of 1 V, the efficiency at 1.2 V was slightly lower than that at 1 V.   Figure 15 shows the measurement results of the output power and the P1dB of the proposed PA (solid line) and the conventional class-E PA (dotted line) versus the supply voltage variations from 0.5 V to 1.2 V.The proposed PA achieved larger saturated output power and P1dB than did the conventional PA.The dependency of the efficiency performances (drain efficiency (DE) and PAE) on the supply voltage is illustrated in Figure 16.The proposed PA achieved higher efficiency than the conventional PA at low-voltage operation.Because the load line was adjusted to obtain high efficiency at a supply voltage of 1 V, the efficiency at 1.2 V was slightly lower than that at 1 V.    Table 1 shows the performance of the proposed PA IC with several published works of lowvoltage operation PAs.The proposed PA IC has achieved excellent PAE with sufficient output power at low-voltage operation compared with the previously published works.Table 1 shows the performance of the proposed PA IC with several published works of lowvoltage operation PAs.The proposed PA IC has achieved excellent PAE with sufficient output power at low-voltage operation compared with the previously published works.Table 1 shows the performance of the proposed PA IC with several published works of low-voltage operation PAs.The proposed PA IC has achieved excellent PAE with sufficient output power at low-voltage operation compared with the previously published works.

2. 1 .Figure 1 .
Figure 1a,b show the operation principle and the input/output characteristics of the DST structure, respectively.The structure consists of two switching transistors: (1) the primary switching transistor M1 biased at class-AB and (2) the secondary switching transistor M2 biased at class-B, which are connected in parallel.Only single input and output matching circuits were employed, thus providing less complexity for the single chip implementation.To realize the class-AB operation of M1, the positive back-gate voltage Vbg was injected.Hence, the threshold voltage decreased so that the overdrive voltage of M1 would be sufficient for the class-AB operation.

Figure 2 .
Figure 2. Basic configuration of the third harmonic tuning circuit.

Figure 2 .
Figure 2. Basic configuration of the third harmonic tuning circuit.

Figure 4 .
Figure 4. Simulated threshold voltage and transconductance versus back-gate voltage variations of the M1 at 0.5-V bias voltage.

Figure 4 .
Figure 4. Simulated threshold voltage and transconductance versus back-gate voltage variations of the M 1 at 0.5-V bias voltage.

Figure 4 .
Figure 4. Simulated threshold voltage and transconductance versus back-gate voltage variations of the M1 at 0.5-V bias voltage.

Figure 5 .
Figure 5. Circuit schematics of (a) the proposed power amplifier (PA) IC, and (b) the conventional class-E PA IC.

Figure 6 .
Figure 6.Simulation results of S11, S21, and S22 of the proposed PA IC.

Figure 7 .
Figure 7. Simulation results of the drain currents versus the input power of the proposed PA IC (solid line) and the conventional PA IC (dotted line).

Figure 6 .
Figure 6.Simulation results of S 11 , S 21 , and S 22 of the proposed PA IC.

Figure 6 .
Figure 6.Simulation results of S11, S21, and S22 of the proposed PA IC.

Figure 7 .
Figure 7. Simulation results of the drain currents versus the input power of the proposed PA IC (solid line) and the conventional PA IC (dotted line).

Figure 7 .
Figure 7. Simulation results of the drain currents versus the input power of the proposed PA IC (solid line) and the conventional PA IC (dotted line).

Figure 6 .
Figure 6.Simulation results of S11, S21, and S22 of the proposed PA IC.

Figure 7 .
Figure 7. Simulation results of the drain currents versus the input power of the proposed PA IC (solid line) and the conventional PA IC (dotted line).

Figure 8 .
Figure 8. Simulated input-output response of the proposed PA (solid line) and the conventional class-E PA (dotted line) PA.

Figure 9 .
Figure 9. Photograph of the chip of the proposed circuits.Figure 9. Photograph of the chip of the proposed circuits.

Figure 9 .
Figure 9. Photograph of the chip of the proposed circuits.Figure 9. Photograph of the chip of the proposed circuits.

Figure 9 .
Figure 9. Photograph of the chip of the proposed circuits.

Figure 10 .
Figure 10.(a) Measurement setup; and (b) probing situation of the proposed CMOS PA IC.

Figure 10 .
Figure 10.(a) Measurement setup; and (b) probing situation of the proposed CMOS PA IC.

Figure 11 .
Figure 11.The uniformity dc performance measurement results of the proposed CMOS PA IC.

Figure 12 .
Figure 12.The measurement results (solid line) versus the simulation results (dashed line) of S11, S21, and S22 of the proposed PA IC at 1 V of supply voltage.

Figure 11 .
Figure 11.The uniformity dc performance measurement results of the proposed CMOS PA IC.

Figure 10 .
Figure 10.(a) Measurement setup; and (b) probing situation of the proposed CMOS PA IC.

Figure 11 .
Figure 11.The uniformity dc performance measurement results of the proposed CMOS PA IC.

Figure 12 .
Figure 12.The measurement results (solid line) versus the simulation results (dashed line) of S11, S21, and S22 of the proposed PA IC at 1 V of supply voltage.

Figure 12 .
Figure 12.The measurement results (solid line) versus the simulation results (dashed line) of S 11 , S 21 , and S 22 of the proposed PA IC at 1 V of supply voltage.

Electronics 2019, 8 , 15 Figure 13 .
Figure 13.Measurement results of the power gain and pout of the proposed PA IC versus the input power.

Figure 14 .
Figure 14.PAE of the proposed PA (solid line) and the conventional class-E PA (dotted line) versus the input power at a supply voltage of 1 V.

Figure 13 .
Figure 13.Measurement results of the power gain and pout of the proposed PA IC versus the input power.

Electronics 2019, 8 , 15 Figure 13 .
Figure 13.Measurement results of the power gain and pout of the proposed PA IC versus the input power.

Figure 14 .
Figure 14.PAE of the proposed PA (solid line) and the conventional class-E PA (dotted line) versus the input power at a supply voltage of 1 V.

Figure 14 .
Figure 14.PAE of the proposed PA (solid line) and the conventional class-E PA (dotted line) versus the input power at a supply voltage of 1 V.

Figure 15
Figure 15  the measurement results of the output power and the P1dB of the proposed PA (solid line) and the conventional class-E PA (dotted line) versus the supply voltage variations from 0.5 V to 1.2 V.The proposed PA achieved larger saturated output power and P1dB than did the conventional PA.The dependency of the efficiency performances (drain efficiency (DE) and PAE) on the supply voltage is illustrated in Figure16.The proposed PA achieved higher efficiency than the conventional PA at low-voltage operation.Because the load line was adjusted to obtain high efficiency at a supply voltage of 1 V, the efficiency at 1.2 V was slightly lower than that at 1 V.

Figure 15 .
Figure 15.The pout and P1dB of the proposed PA (solid line) and the conventional class-E PA (dotted line) versus supply the voltage variations.

Figure 16 .
Figure 16.The drain efficiency (DE) and PAE of the proposed PA (solid line) and the conventional class-E PA (dotted line) versus the supply voltage.

Figure 15 . 15 Figure 15 .
Figure 15.The pout and P1dB of the proposed PA (solid line) and the conventional class-E PA (dotted line) versus supply the voltage variations.

Figure 16 .
Figure 16.The drain efficiency (DE) and PAE of the proposed PA (solid line) and the conventional class-E PA (dotted line) versus the supply voltage.

Figure 16 .
Figure 16.The drain efficiency (DE) and PAE of the proposed PA (solid line) and the conventional class-E PA (dotted line) versus the supply voltage.

Table 1 .
Summary of the proposed PA IC with several published works.

Table 1 .
Summary of the proposed PA IC with several published works.

Table 1 .
Summary of the proposed PA IC with several published works.