Three Topologies of a Non-Isolated High Gain Switched-Inductor Switched-Capacitor Step-Up Cuk Converter for Renewable Energy Applications

This paper introduces three topologies of a non-isolated high gain step-up Cuk converter based on a switched-inductor (SL) and switched-capacitor (SC) techniques for renewable energy applications, such as photovoltaic and fuel cells. These kinds of Cuk converters provide a negative-to-positive step-up dc–dc voltage conversion. The proposed three topologies SLSC Cuk converters increase the voltage boost ability significantly using the switched-inductor and switched-capacitor techniques compared with the classical Cuk and boost converters. The proposed Cuk converters are derived from the classical Cuk converter by replacing the single inductor at the input and output sides with a SL and the transferring energy capacitor by a SC. The main advantages of the proposed SLSC Cuk converters are achieving a high voltage conversion ratio and reducing the voltage stress across the main switch. Therefore, a switch with low voltage rating and thus, of low RDS−ON can be used, and that leads to a higher efficiency. For example, the third topology have the ability to boost the input voltage up to 13 times when D = 0.75, D is the duty cycle. The voltage gain and the voltage stress across the main switch in the three topologies have been compared with the classical Cuk and boost converter. The proposed three topologies avoid using a transformer, coupled inductors, or extreme duty cycles leading to less volume, loss, and cost. The proposed SLSC Cuk converters are analyzed in continuous conduction mode (CCM), and they have been designed for 12 V input supply voltage, 100 W rated power, 50 kHz switching frequency, and 75% duty cycle. A detailed theoretical analysis of the CCM is represented and all the equations have been derived and matched with the results. The proposed three topologies SLSC Cuk converters have been simulated in MATLAB/SIMULINK and results are discussed.


Introduction
Various dc-dc converter topologies include isolated converters and non-isolated converters have been developed to achieve a high voltage gain without an extremely high duty cycle.Usually, isolated dc-dc converters using transformers are used when a high step-up ratio is required because the voltage gain can be adjusted by increasing the turns ratio of the transformer [1][2][3][4][5][6].However, the isolated converters have some difficulties in achieving a high efficiency due to the power transformer losses and the leakage inductance besides the heavy weight and large volume of the converter.So, the best solution is to use a non-isolated converters with an additional technique associated to achieve a high voltage gain [7][8][9].
A high output voltage classical boost converter requires a MOSFET with high current and voltage ratings.Therefore, this MOSFET has a high on-resistance, which increases cost, size, and conduction loss [10].A number of high step-up topologies have been presented in order to increase the voltage gain and efficiency.In [11], a cascade boost converter is presented.It can supply a load with a high voltage and relatively high efficiency.The major drawbacks of using this topology are higher cost because of using two dc-dc converters and the complexity.
Converters with coupled inductors topology can accomplish high voltage gain [12][13][14][15][16][17].However, using coupled inductors topology will reduce the efficiency due to the losses associated with the leakage inductors.Other drawbacks are requiring high voltage rated switch and suffering from EMI problems [10].
In some special industrial applications such as automobiles, space stations, and manufacturing industries, dc-dc converters that can achieve the negative to positive voltage conversion play an important role [18].In such applications, the negative dc voltage source requires a dc-dc converter that realizes the polarity inversion to provide the positive voltage to the load with respect to the common ground.In designing the dc-dc converter for the negative dc voltage bus, two features should be considered: a negative to positive voltage conversion path and high voltage conversion ratios [19].
The classical Cuk (shown in Figure 1) and buck boost converters are two dc-dc converters that have an output voltage magnitude that is either greater or less than the input voltage with a polarity inversion due to their voltage conversion ratio as described in (1).The value of D which is the duty cycle cannot be too high (more than 0.9) and consequently, their boost voltage abilities have been restricted due to the effect of parasitic components [19].The classical Cuk converter has three modes (buck mode, boost mode, and buck-boost mode) [20].The classical Cuk converter has advantages such as having an energy transfer capacitor, good steady-state performance, continuous input and output current, and low output voltage ripple [20][21][22].Ref. [23][24][25][26] present Cuk converters using different techniques, however, the voltage conversion ratio is low.A number of switched-inductor and switched-capacitor topologies are presented in [27] to achieve high voltage gain.In this paper, the concept of a switched-inductor (SL) and switched-capacitor (SC) techniques have been integrated to the classical Cuk converter, and consequently, new step-up Cuk converters are proposed.From the viewpoint of a circuit topology (combining SL with SC in Cuk converter), the proposed converters are different from any other existing Cuk converter.The main advantages of the proposed converters are summarized as follow.

•
provide a non-isolated negative to positive voltage path with respect to a common ground; • higher voltage conversion ratios than the classical Cuk and boost converter due to the SL and SC techniques; • lower voltage stress across the main switch than the classical Cuk and boost converter, therefore, a switch with low voltage rating and low R DS−ON can be used; • according to the topology, number of diodes, one capacitor, and one or three inductors have been added to the main Cuk converter to perform the SL and SC in order to increase the voltage gain; • use of a single switch; • the main advantage of the classical Cuk converter which is having continuous current in the input and output sides due to the input and output inductors have been kept when designing the proposed topologies.
Topology-I, -II, and -III are described in Sections 2-4.Each topology section contains a power circuit, modes of operation, and a detailed circuit analysis.In Section 5, a comparison analysis is performed between the proposed Cuk topologies, a classical Cuk converter, and classical boost converter in terms of a voltage gain and switch voltage stress.Results are discussed in Section 6.Finally, a brief summary is given in the conclusion in Section 7.

Power Circuit
The SLSC Cuk converter topology-I is obtained from the classical Cuk converter by replacing the input side inductor with a SL and the transferring energy capacitor with a SC. Figure 2 shows the power circuit diagram of the SLSC topology-I.Compared with the Cuk prototype, one inductor, one capacitor, and four diodes are added into the proposed circuit of Figure 2.

Modes of Operation
The proposed three topologies SLSC Cuk converters are analyzed in continuous conduction mode (CCM).In CCM, the operation of the proposed three topologies is divided into two modes.ON-mode when switch S 1 is conducting and OFF-mode when switch S 1 is not conducting.

ON-Mode
When switch S 1 is conducting (turned on), the current direction is shown in Figure 3a.Inductors L 1 and L 2 are charged in parallel by input supply voltage V in through diodes D 1 , D 3 , and switch S 1 .Diodes D 2 , D 4 , and D 5 are reversed-biased.Input supply voltage V in with the discharged energy of capacitors C 1 and C 2 supply the load and charge inductor L 3 through switch S 1 .Equal amount of current flowing through inductors L 1 and L 2 since both inductors are the same.

OFF-Mode
When switch S 1 is not conducting (turned off), the current direction is shown in Figure 3b.Input supply voltage V in with the discharged energy of inductors L 1 and L 2 charge capacitors C 1 and C 2 connected in parallel.Likewise, the discharged energy of inductor L 3 charges capacitors C 1 and C 2 and supply the load.Diodes D 1 and D 3 are reversed-biased.Switching diagrams in CCM of the main steady-state waveforms with enlarged variations for the SLSC topology-I are shown in Figure 4.

Circuit Analysis
It is assumed that all three topologies SLSC Cuk converters are operating in steady-state to simplify the analysis.Also, the following assumptions are made: all components are ideal (100% efficiency), input voltage V in is a pure dc, and all capacitors are sized to have a relatively small voltage ripple at switching frequency f s .
When MOSFET S 1 is conducting, the voltage across inductors L 1 , L 2 , and L 3 are expressed in (2) and ( 3 When MOSFET S 1 is not conducting, the voltage across inductors L 1 , L 2 , and L 3 are expressed in (4) and ( 5).
By applying the volt-second method to the inductors L 1 , L 2 , and L 3 the two expressions in ( 6) and ( 7) can be obtained.
The voltage expression across C 1 and C 2 can be expressed in (8).
The ideal voltage gain in CCM can be expressed in ( 9) From Figure 3a,b, it is possible to find an equation to calculate the current of the two input inductors.Because the two input inductors have the same inductance values, (11) from (10).
Capacitor C O acts as low-pass filter, so (12) is obtained for I L 3 = I L out .
The reverse voltage across D 1 and D 3 applied when they are blocked (OFF-mode) is expressed in (13).
The reverse voltage across D 2 applied when it is blocked (ON-mode) is expressed in (14).
The reverse voltage across D 4 and D 5 of the SC applied when they are blocked (ON-mode) is expressed in (15).
The voltage stress across the power switch S 1 when it is blocked (OFF-mode) is expressed in (16).
The peak-to-peak variation of the inductor's current at the input ( i L 1 = i L 2 = i L in ) and output ( i L 3 = i L out ) sides are expressed in (17) and (18), respectively.
The peak-to-peak variation of the capacitor's voltage 3. Topology-II

Power Circuit
The SLSC Cuk converter topology-II is obtained from the classical Cuk converter by replacing the output side inductor with a SL and the transferring energy capacitor with a SC. Figure 5 shows the power circuit diagram of the SLSC Cuk converter topology-II.Compared with the Cuk prototype, one inductor, one capacitor, and four diodes are added into the proposed circuit of Figure 5.

ON-Mode
When switch S 1 is conducting, the current direction is shown in Figure 6a.Inductor L 1 is charged by input supply voltage V in through switch S 1 .Input supply voltage V in with the discharged energy of capacitors C 1 and C 2 supply the load and charge inductors L 2 and L 3 which is connected in parallel through diodes D 3 , D 5 , and switch S 1 .Diodes D 1 , D 2 , and D 4 are reversed-biased.Equal amount of current flowing through inductors L 2 and L 3 since both inductors are the same.

OFF-Mode
When switch S 1 is not conducting, the current direction is shown in Figure 6b.The input supply voltage V in and the discharged energy of inductor L 1 charge capacitors C 1 and C 2 connected in parallel.Likewise, the discharged energy of inductors L 2 and L 3 charges capacitors C 1 and C 2 and supplies the load.Diodes D 3 and D 5 are reversed-biased.Switching diagrams in CCM of the main steady-state waveforms with enlarged variations for the SLSC topology-II are shown in Figure 7.

Circuit Analysis
When MOSFET S 1 is conducting, the voltage across inductors L 1 , L 2 , and L 3 are expressed in ( 20) and (21) When MOSFET S 1 is not conducting, the voltage across inductors L 1 , L 2 , and L 3 are expressed in (22) and (23).
By applying the volt-second method to the inductors L 1 , L 2 , and L 3 the two expressions in ( 24) and ( 25) can be obtained.
The voltage expression across C 1 and C 2 can be obtained in (26).
The ideal voltage gain in CCM can be expressed in ( 27) The input inductor current (I L 1 = I L in ) is obtained in ( 28) from (27).
From Figure 6, it is possible to find an equation to calculate the current of the two output inductors.Because the two output inductors have the same inductance values, The reverse voltage across D 1 and D 2 of the SC applied when they are blocked (ON-mode) is expressed in (31).
The voltage stress across the power switch S 1 when it is blocked (OFF-mode) is expressed in (32).
The reverse voltage across D 3 and D 5 applied when they are blocked (OFF-mode) is expressed in (33).
The reverse voltage across D 4 applied when it is blocked (ON-mode) is expressed in (34).
The peak-to-peak variation of the inductor's current at the input ( i L 1 = i L in ) and output ( i L 2 = i L 3 = i L out ) sides are expressed in (35) and (36), respectively.
The peak-to-peak variation of the capacitor's voltage ( (37)

Power Circuit
The SLSC Cuk converter topology-III is obtained from the classical Cuk converter by replacing both the input and output side inductors with two SLs and the transferring energy capacitor with a SC. Figure 8 shows the power circuit diagram of the SLSC Cuk converter topology-III.Compared with the Cuk prototype, two inductors, one capacitor, and seven diodes are added into the proposed circuit of Figure 8.
The voltage expression across C 1 and C 2 can be obtained in (44).
The ideal voltage gain in CCM can be expressed in (45).
The reverse voltage across D 1 , D 3 , D 6 , and D 8 applied when they are blocked (OFF-mode) is expressed in (48).
The reverse voltage across D 2 and D 7 applied when they are blocked (ON-mode) is expressed in (49).
The reverse voltage across D 4 and D 5 of the SC applied when they are blocked (ON-mode) is expressed in (50).
The voltage stress across the power switch S 1 when it is blocked (OFF-mode) is expressed in (51).
The peak-to-peak variation of the inductor's current at the input ( i L 1 = i L 2 = i L in ) and output ( i L 3 = i L 4 = i L out ) sides are expressed in (52) and (53), respectively.
The peak-to-peak variation of the capacitor's voltage

Comparison Analysis
A comparison has been made between the proposed three topologies SLSC Cuk converters with the classical Cuk and boost converters as shown in Table 1.The proposed three topologies have a higher voltage gain, and the highest is topology-III as shown graphically in Figure 11a.
The normalized voltage (V s /V in ) on the main switch that describes the voltage stress across semiconductor device MOSFET S 1 of these three topologies are compared with those in the classical Cuk and boost converters and graphically represented in Figure 11b.As can be seen the three topologies have a lower voltage stress, and the lowest is topology-II.Voltage Gain

Results and Discussion
The three proposed topologies are designed for 12 V input voltage, 100 W rated power, 50 kHz switching frequency, and 75% duty cycle.They all have been simulated in MATLAB/SIMULINK.Specifications of the proposed SLSC Cuk converters are shown in Table 2.

Efficiency
An efficiency comparison between the three topologies of the proposed SLSC Cuk converter has been made using the numerical values assumed for parasitic parameters of the semiconductor switches shown in Table 3.The efficiency is graphically represented in Figure 21.Peak efficiencies of 86% for topology-I, 94.33% for topology-II, and 85% for topology-III are achieved when the output power is 120 W and the input voltage is 12 V.As highlighted by [28], The efficiency increases for higher input voltages because the input current decreases, and therefore, the conduction losses of power switches are reduced.

Conclusions
This study has successfully developed three topologies of Cuk converters with high voltage gain and reduced active switch stress.This high voltage gain is accomplished without using a transformer, coupled inductors, or extreme duty cycle.The operation of the proposed converters was analyzed for continuous conduction mode.The proposed converters are regulated by the PWM technique at a constant frequency.Comparisons are made between the proposed converters, the classical Cuk converter, and the classical boost converter.The main advantages of the proposed converters include high voltage gain, low voltage stress which leads to select active switch with low voltage rating and low R DS−ON , continuous input and output current, use of single switch, high efficiency, and simplicity of the design.The steady-state analysis of the voltage gain is discussed in detail.The simulation results agree with the operating modes and the equations derived.The three converters are simulated using MATLAB/SIMULINK.

Table 1 .
Comparison between boost converter, Cuk converter, and three proposed converters.

Figure 11 .
Figure 11.Voltage gain and voltage stress comparison.(a) Voltage gain comparison.(b) Voltage stress on the active switch.

6 . 1 .
Topology-I The SLSC Cuk converter topology-I is designed for −137 output voltage.The voltage stress and current stress on MOSFET S 1 are shown in Figure 12a.The voltage stress and current stress are approximately 78 V and 10 A, respectively.The voltage stress on the two diodes D 4 and D 5 of the SC is shown in Figure 12b.The voltage stress across the two diodes of the SC is −78 V. Diodes D 4 and D 5 are conducting during the off time period of MOSFET S 1 , and they are not conducting during the on time period of MOSFET S 1 as shown in Figure 12b.The voltage waveforms of capacitors C 1 and C 2 are shown in Figure 13a.From the figure, the two capacitors get charged when MOSFET S 1 is off, and they get discharged when MOSFET S 1 is on.The current waveforms of inductors L 1 , L 2 , and L 3 are shown in Figure 13b.The three inductors get charged when MOSFET S 1 is on, and they get discharged when MOSFET S 1 is off.The input voltage, output voltage, and output power waveforms are shown in Figure 14.

Figure 12 .Figure 13 .
Figure 12.Semiconductor devices' stresses of topology-I (a) Voltage and current stresses on S 1 .(b) Voltage stresses on D 4 and D 5 .

Figure 14 .
Figure 14.V in , V out , and P out waveforms of topology-I.

6. 2 .
Topology-II The SLSC Cuk converter topology-II is designed for −87 output voltage.The voltage stress and current stress on MOSFET S 1 are shown in Figure 15a.The voltage stress and current stress are approximately 48 V and 10 A, respectively.The voltage stress on the two diodes D 1 and D 2 of the SC is shown in Figure 15b.The voltage stress across the two diodes of the SC is −48V.Diodes D 1 and D 2 are conducting during the off time period of MOSFET S 1 , and they are not conducting during the on time period of MOSFET S 1 as shown in Figure 15b.The voltage waveforms of capacitors C 1 and C 2 are shown in Figure 16a.From the figure, the two capacitors get charged when MOSFET S 1 is off, and they get discharged when MOSFET S 1 is on.The current waveforms of inductors L 1 , L 2 , and L 3 are shown in Figure 16b.The three inductors get charged when MOSFET S 1 is on, and they get discharged when MOSFET S 1 is off.The input voltage, output voltage, and output power waveforms are shown in Figure 17.

Figure 15 .Figure 16 .
Figure 15.Semiconductor devices' stresses of topology-II (a) Voltage and current stresses on S 1 .(b) Voltage stresses on D 1 and D 2 .

Figure 17 .
Figure 17.V in , V out , and P out waveforms of topology-II.

Figure 18 .Figure 19 .
Figure 18.Semiconductor devices' stresses of topology-III (a) Voltage and current stresses on S 1 .(b) Voltage stresses on D 4 and D 5 .

Figure 20 .
Figure 20.V in , V out , and P out waveforms of topology-III.

Figure 21 .
Figure 21.Efficiency curves as function of the output power.

Table 3 .
Parasitic parameters of the semiconductor switches.