Soft Switching DC Converter for Medium Voltage Applications

Abstract: A dc-dc converter with asymmetric pulse-width modulation is presented for medium voltage applications, such as three-phase ac-dc converters, dc microgrid systems, or dc traction systems. To overcome high voltage stress on primary side and high current rating on secondary side, three dc-dc circuits with primary-series secondary-parallel structure are employed in the proposed converter. Current doubler rectifiers are used on the secondary side to achieve low ripple current on output side. Asymmetric pulse-width modulation is adopted to realize soft switching operation for power switches for wide load current operation and achieve high circuit efficiency. Current balancing cells with magnetic component are used on the primary side to achieve current balance in each circuit cell. The voltage balance capacitors are also adopted on primary side to realize voltage balance of input split capacitors. Finally, the circuit performance is confirmed and verified from the experiments with a 1.44 kW prototype.


Introduction
Medium voltage dc-dc converters have been proposed and implemented to achieve high power density and high efficiency advantages for dc light rail transportation systems [1,2], dc microgrid systems [3,4], or industry power converters [5,6].In those applications, the high side dc bus voltage is normally at 750 V.The 1200 V SiC or Insulated Gate Bipolar Transistor (IGBT) power switches can be used to convert 750 V dc bus voltage to low voltage output through high-frequency link dc-dc converters.However, SiC devices are expensive, and the switching frequency of IGBT devices is less than 60kHz.The series-connected switches [7,8] and series-connected dc-dc converters [9,10] can be used for medium voltage converters with 600V Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) power devices.These two approaches can reduce the voltage stress on power devices.However, the voltage stresses on each power switch are difficult and unbalanced.Therefore, power devices still have an unbalanced voltage stress problem.Three-level pulse-width modulation converters or resonant converters have been presented in [11][12][13][14] to lessen the voltage rating and switching loss on power devices.Modular converters with series or parallel connection have been developed in [15][16][17] for high voltage or current applications.However, the current balance in each circuit modular should be controlled well in order to distribute equal power in each modular.To solve the current balance issue in each circuit modular, the current balance control approaches have been discussed in [18,19] by using the passive magnetic component.
This paper presents a high voltage dc-dc converter with three cascade half-bridge circuits on primary side to reduce the voltage and current ratings of power devices for high voltage and medium power applications, such as dc light trail transportation systems and three-phase ac-dc power converters.Voltage balance capacitors are also employed on the primary side in order to balance input split voltages.To prevent current imbalance on each half bridge circuit, the magnetic coupling (MC) current balance components are employed between each half bridge circuit.If the primary-side currents are unbalanced, then the primary-side and secondary-side voltages of MC component will decreased, or increased, in order to compensate the imbalance in primary-side currents.Asymmetric pulse-width modulation approach is adopted to realize the soft switching turn-on characteristic for power switches.Therefore, the switching losses of power devices at high frequency operation can be reduced.Current doubler rectifiers are used on low voltage side in order to reduce the output ripple current.The paper is organized as follows.The circuit diagram and operating principle are presented in Section 2. The circuit characteristics of the proposed converter are discussed in Section 3. In Section 4, experiments are provided to demonstrate the effectiveness of the developed circuit.Then, the conclusion of the presented circuit is discussed in Section 5.

Circuit Diagram and Principles of Operation
The developed high-frequency link dc-dc converter is illustrated in Figure 1 to realize the main benefits of soft switching operation, low switching loss, low output ripple current and the balance primary-side and secondary-side currents.Three half-bridge circuits with primary-series secondary-parallel configuration are used in the proposed converter to realize low voltage stress V in /3 on power switches S 1 ~S6 , and low current stress I o /6 on power diodes D 1 ~D6 .Therefore, 600 V power MOSFETs are used on the primary side to achieve high frequency operation and low conduction loss.Voltage balance capacitors C f1 and C f2 are employed on the primary side to achieve a split voltages balance at V in /3.Half-bridge circuits are operated under asymmetric pulse-width modulation.Therefore, the soft switching turn-on of power switches can be achieved, and the circuit efficiency is improved.The magnetic coupling current balance [19] cells, MC 1 and MC 2 , are used on the primary side to achieve current balance for each half-bridge circuit.Therefore, the current unbalance issue of modular converters is overcome.The current doubler rectifiers are used on the secondary side to accomplish low ripple current on load side.
Electronics 2018, x, x FOR PEER REVIEW 2 of 14 converters.Voltage balance capacitors are also employed on the primary side in order to balance input split voltages.To prevent current imbalance on each half bridge circuit, the magnetic coupling (MC) current balance components are employed between each half bridge circuit.If the primary-side currents are unbalanced, then the primary-side and secondary-side voltages of MC component will decreased, or increased, in order to compensate the imbalance in primary-side currents.Asymmetric pulse-width modulation approach is adopted to realize the soft switching turn-on characteristic for power switches.Therefore, the switching losses of power devices at high frequency operation can be reduced.Current doubler rectifiers are used on low voltage side in order to reduce the output ripple current.The paper is organized as follows.The circuit diagram and operating principle are presented in Section 2. The circuit characteristics of the proposed converter are discussed in Section 3. In section 4, experiments are provided to demonstrate the effectiveness of the developed circuit.Then, the conclusion of the presented circuit is discussed in Section 5.

Circuit Diagram and Principles of Operation
The developed high-frequency link dc-dc converter is illustrated in Figure 1 to realize the main benefits of soft switching operation, low switching loss, low output ripple current and the balance primary-side and secondary-side currents.Three half-bridge circuits with primary-series secondaryparallel configuration are used in the proposed converter to realize low voltage stress Vin/3 on power switches S1~S6, and low current stress Io/6 on power diodes D1~D6.Therefore, 600 V power MOSFETs are used on the primary side to achieve high frequency operation and low conduction loss.Voltage balance capacitors Cf1 and Cf2 are employed on the primary side to achieve a split voltages balance at Vin/3.Half-bridge circuits are operated under asymmetric pulse-width modulation.Therefore, the soft switching turn-on of power switches can be achieved, and the circuit efficiency is improved.The magnetic coupling current balance [19] cells, MC1 and MC2, are used on the primary side to achieve current balance for each half-bridge circuit.Therefore, the current unbalance issue of modular converters is overcome.The current doubler rectifiers are used on the secondary side to accomplish low ripple current on load side.Step 1 [t0~t1]: Before time t0, all the secondary-side diodes are in the commutated interval, and the primary-side currents ip1~ip3 increase.After time t0, the secondary-side diodes, D1, D3, and D5, are off.In step 1, the primary-side capacitor voltage vCf1 equals vCin1, and vCf2 equals vCin2.The ac-side input voltages of three half bridge circuits vab, vcd, and vef are clamped at vCin1, vCin2, and vCin3, respectively.The magnetizing inductor voltages vLm1, vLm2, and vLm3 are equal to Vin/3 − vC1, Vin/3 − vC2, and Vin/3 − vC3, respectively.The secondary-side inductor voltages vL1, vL3, and vL5 are equal to (Vin/3 − vC1)/n − Vo, (Vin/3 − vC2)/n − Vo and (Vin/3 − vC3)/n − Vo, respectively, and vL2 = vL4 = vL6 = −Vo.Therefore, the primaryside currents ip1 ~ ip3 and the secondary-side currents iL1, iL3, and iL5 increase, and the output inductor currents iL2, iL4, and iL6 decrease, in step 1.
Step 2 [t1~t2]: Switches S1, S3, and S5 are turned off at time t1.Due to the positive value of ip1~ip3, vCS1, vCS3, and vCS5 are increased and vCS2, vCS4, and vCS6 are decreased.The charged and discharged times of CS1~CS6 are very fast so that the primary-side and secondary-side currents are constant in step 2.
Step 3 [t2~t3]: When vCS2 = vC1, vCS4 = vC2 and vCS6 = vC3 at time t2.The primary-side and secondaryside winding voltages of T1~T3 are zero voltage.Thus, the secondary-side diodes D1~D6 are forward biased to commutate the load current such that iL1~iL6 decrease, iD1, iD3, and iD5 increase, and iD2, iD4, and iD6 decrease in step 3. CS2, CS4, and CS6 can be discharged to zero voltage if the energy on the leakage inductors Llk1~Llk3 is large enough, and the dead time td between the upper and lower switches on each half bridge leg is larger than the time interval in steps 2 and 3.
Step 4 [t3~t4]: The capacitor voltages vCS2 = vCS4 = vCS6 = 0 at time t3.Due to ip1(t3)~ip3(t3) being positive, the body diodes of S2, S4, and S6 are conducting so that S2, S4, and S6 are turned on at zero voltage switching.The secondary-side diodes, D1~D6, are at the commutated interval, and the primary-side leakage inductor voltages are vlk1 = −vC1, vlk2 = −vC2, and vlk3 = −vC3.Thus, the primary-side currents ip1~ip3 and the secondary-side inductor currents iL1~iL6 all decrease in step 4. In step 4, the current variations on ip1~ip3 approximate Io/(3n) in order to accomplish the commutation interval through diodes D1~D6.Step 1 [t 0 ~t1 ]: Before time t 0 , all the secondary-side diodes are in the commutated interval, and the primary-side currents i p1 ~ip3 increase.After time t 0 , the secondary-side diodes, D 1 , D 3 , and D 5 , are off.In step 1, the primary-side capacitor voltage v Cf1 equals v Cin1 , and v Cf2 equals v Cin2 .The ac-side input voltages of three half bridge circuits v ab , v cd , and v ef are clamped at v Cin1 , v Cin2 , and v Cin3 , respectively.The magnetizing inductor voltages v Lm1 , v Lm2 , and v Lm3 are equal to Therefore, the primary-side currents i p1 ~ip3 and the secondary-side currents i L1 , i L3 , and i L5 increase, and the output inductor currents i L2 , i L4 , and i L6 decrease, in step 1.
Step 2 [t 1 ~t2 ]: Switches S 1 , S 3 , and S 5 are turned off at time t 1 .Due to the positive value of i p1 ~ip3 , v CS1 , v CS3 , and v CS5 are increased and v CS2 , v CS4 , and v CS6 are decreased.The charged and discharged times of C S1 ~CS6 are very fast so that the primary-side and secondary-side currents are constant in step 2.
Step 3 [t 2 ~t3 ]: The primary-side and secondary-side winding voltages of T 1 ~T3 are zero voltage.Thus, the secondary-side diodes D 1 ~D6 are forward biased to commutate the load current such that i L1 ~iL6 decrease, i D1 , i D3 , and i D5 increase, and i D2 , i D4 , and i D6 decrease in step 3. C S2 , C S4 , and C S6 can be discharged to zero voltage if the energy on the leakage inductors L lk1 ~Llk3 is large enough, and the dead time t d between the upper and lower switches on each half bridge leg is larger than the time interval in steps 2 and 3.
Step 4 [t 3 ~t4 ]: The capacitor voltages v CS2 = v CS4 = v CS6 = 0 at time t 3 .Due to i p1 (t 3 )~i p3 (t 3 ) being positive, the body diodes of S 2 , S 4 , and S 6 are conducting so that S 2 , S 4 , and S 6 are turned on at zero voltage switching.The secondary-side diodes, D 1 ~D6 , are at the commutated interval, and the primary-side leakage inductor voltages are v lk1 = −v C1 , v lk2 = −v C2 , and v lk3 = −v C3 .Thus, the primary-side currents i p1 ~ip3 and the secondary-side inductor currents i L1 ~iL6 all decrease in step 4.
In step 4, the current variations on i p1 ~ip3 approximate I o /(3n) in order to accomplish the commutation interval through diodes D 1 ~D6 .
Therefore, the duty loss in step 4 is calculated as Step 5 [t 4 ~t5 ]: The secondary-side diode currents i D2 , i D4 , and i D6 are zero, and become reverse biased.In step 5, the capacitor voltages v Cf1 = v Cin2 and v Cf2 = v Cin3 , and the ac side voltages v ab = v cd = v ef = 0. Therefore, the magnetizing inductor voltages , and i L5 decrease, and i L2 , i L4 , and i L6 increase, in step 5.

Circuit Characteristics
Three half bridge circuits are used in the proposed converter with primary-series and secondaryparallel connection to distribute load power through three circuits.Therefore, the power rating of each half bridge circuit is one-third of load power, Po/3.In order to balance the modular currents, the magnetic coupling (MC) current balance cells are presented and discussed in [19].Therefore, the magnetic coupling current balance components MC1 and MC2 are used in the proposed converter to achieve current balance issue between three half bridge circuits.If the primary-side currents are unbalanced, such as |ip2| > |ip3|, then the induced voltage vMC2,p is lessened to decrease current ip2 and the secondary-side induced voltage vMC2,s is increased to rise current ip3.If the primary currents are balanced (|ip1| = |ip2| = |ip3|), then the induced primary-side and secondary-side voltages of MC1 and MC2 cells are zero voltage, vMC1,p = vMC1,s = vMC2,p = vMC2,s = 0. Current doubler rectifiers are adopted on the secondary side to lessen the output ripple current.The average dc blocking voltages VC1~VC3 are related to the input voltage and duty cycle of S1, S3, and S5.These three voltages can be calculated from the flux balance on the primary-side inductors.
The output voltage is related to input voltage, duty cycle, and turns ratio, according to the flux balance on the output inductors.Step 6 [t 5 ~t6 ]: Power switches S 2 , S 4 , and S 6 are turned off at time t 5 .Due to i p1 (t 5 ) < 0, i p2 (t 5 ) < 0 and i p3 (t 5 ) < 0, then C S1 , C S3 , and C S5 will be discharged in step 6.Since the charged and discharged times of C S1 ~CS6 are very fast, the primary-side and secondary-side inductor currents are approximately constant in step 6.
Step 7 [t 6 ~t7 ]: The output capacitor voltages v CS1 , v CS3 , and v CS5 are discharged to v C1 , v C2 , and v C3 , respectively, at time t 6 .Then, the primary-side and secondary-side winding voltages of T 1 ~T3 are all zero voltage.In step 7, the secondary-side diodes D 1 ~D6 are all conducting to commutate the inductor currents i L1 ~iL6 .At time t 7 , C S1 , C S3 , and C S5 are discharged to zero voltage.
Step 8 [t 7 ~t0 +T sw ]: The capacitor voltages C S1 , C S3 , and C S5 are discharged to zero voltage at time t 7 .Due to i p1 (t 7 )~i p3 (t 7 ) being all negative, the body diodes of S 1 , S 3 , and S 5 conduct.Therefore, S 1 , S 3 , and S 5 can be turned on under zero voltage after time t 7 .Since D 1 ~D6 are still conducting, the primary-side currents increase.The diodes currents i D1 , i D3 , and i D5 decrease to zero at time t 0 + T sw .The duty loss in this step 8 is calculated as:

Circuit Characteristics
Three half bridge circuits are used in the proposed converter with primary-series and secondary-parallel connection to distribute load power through three circuits.Therefore, the power rating of each half bridge circuit is one-third of load power, P o /3.In order to balance the modular currents, the magnetic coupling (MC) current balance cells are presented and discussed in [19].Therefore, the magnetic coupling current balance components MC 1 and MC 2 are used in the proposed converter to achieve current balance issue between three half bridge circuits.If the primary-side currents are unbalanced, such as |i p2 | > |i p3 |, then the induced voltage v MC2,p is lessened to decrease current i p2 and the secondary-side induced voltage v MC2,s is increased to rise current i p3 .If the primary currents are balanced (|i p1 | = |i p2 | = |i p3 |), then the induced primary-side and secondary-side voltages of MC 1 and MC 2 cells are zero voltage, v MC1,p = v MC1,s = v MC2,p = v MC2,s = 0. Current doubler rectifiers are adopted on the secondary side to lessen the output ripple current.The average dc blocking voltages V C1 ~VC3 are related to the input voltage and duty cycle of S 1 , S 3 , and S 5 .These three voltages can be calculated from the flux balance on the primary-side inductors.
The output voltage is related to input voltage, duty cycle, and turns ratio, according to the flux balance on the output inductors.
where V f is the voltage drop on D 1 ~D6 .Due to the MC, current balance components are used on the primary side of the proposed converter, and the output currents of three half bridge circuits are balanced in steady state.The average secondary-side winding currents of T 1 ~T3 are zero.Therefore, the average output inductor currents are calculated as If the duty cycle d < 0.5, then the average inductor currents I L1 , I L3 , and I L5 are greater than I L2 , I L4 , and I L6 .The ripple currents on L 1 ~L6 are calculated as From ( 5)~( 7), the maximum and minimum output inductor currents are derived as If the magnetizing inductances of T 1 ~T3 are given, the ripple currents on L m1 ~Lm3 are calculated as Due to the conducting time on D 1 ~D6 being related to the duty cycle d, the secondary-side diode average currents and voltage ratings are calculated as V D1,stress = V D3,stress = V D5,stress = (1 − d)V in /(3n), V D2,stress = V D4,stress = V D6,stress = dV in /(3n).( 14) Since the balance capacitors C f1 and C f2 are used on the primary side of three half bridge circuits, the input split voltages V Cin1 , V Cin2 , and V Cin3 are balanced at V in /3.Based on the half bridge circuit topology, the voltage rating of power switches S 1 ~S6 is clamped at V in /3.If the ripple currents on the output inductors and the magnetizing inductors are much less than the average output inductor currents at full load, then the root mean square (rms) currents of power devices are expressed in ( 15) and ( 16).
The zero voltage conditions of power switches S 1 , S 3 , and S 5 are related to the primary-side currents i p1 (t 5 ), i p2 (t 5 ), and i p3 (t 5 ), respectively, and the input voltage.Similar, the zero voltage conditions of power switches S 2 , S 4 , and S 6 are related to the primary-side currents i p1 (t 1 ), i p2 (t 1 ), and i p3 (t 1 ), respectively, and the input voltage.The primary-side currents i p1 ~ip3 at time t 1 and t 5 are related to the load current and the ripple currents on the magnetizing inductors L m1 ~Lm3 , and output inductors L 1 ~L6 .
Similar, the necessary leakage inductance to achieve ZVS condition of S 2 , S 4 , and S 6 is expressed in (20).
Based on the zero-voltage condition in (19) and (20), the necessary leakage inductance can be calculated in (21).
If the ripple voltage on dc blocking capacitors C 1 ~C3 is less than 20% of the average voltage value, then the dc blocking capacitances C 1 ~C3 are calculated as

Experimental Results
Experiments based on a laboratory prototype are provided to verify the effectiveness of the developed circuit.The input dc voltage V in,min = 750 V and V in,max = 800 V, the output voltage V o = 24 V and the maximum load current I o = 60 A. The switching frequency f sw = 100 kHz.The circuit components of the laboratory prototype are summary in Table 1. Figure 4 illustrates the picture of the laboratory prototype circuit.Figure 5 presents the test results of the gating signals of S 1 , S 2 , S 3 , and S 5 under the rated power.The switches S 1 and S 2 have complementary gating signals, and S 1 , S 3 , and S 5 have identical pulse-width modulation signals.Figure 6 illustrates the test waveforms of the primary-side voltage v ab and currents i p1 ~ip3 at the rated power.It is clear that the three primary-side currents i p1 ~ip3 are well balanced.The input split voltages and balance capacitor voltage at the rated power are measured and presented in Figure 7.The measured voltages are V Cin1 = 251 V, V Cin2 = 249.3V, V Cin3 = 249.7 V, V Cf1 = 251 V, and V Cf2 = 249 V under V in = 750 V input.It is clear that the input split voltages and balance capacitor voltages are well balanced.Figure 8 presents the test results of the gating voltage and drain current of power switch S 1 under 20% output load, and the rated output load for both 750 V and 800 V input cases.Before the power switch S 1 is turned on, the drain current is a negative value, to discharge the drain voltage.Therefore, the soft switching characteristic of S 1 can be realized from 20% output load to the rated output load, based on the test results in Figure 8.Similarly, the measured waveforms of S 2 are presented in Figure 9.It can be observed that the zero-voltage switching characteristic of S 2 is also achieved from 20% output load.Since power devices S 3 and S 5 are operated in the same circuit manner as power device S 1 , and S 4 and S 6 are controlled in the same circuit manner as S 2 , it can be expected that the zero-voltage switching of power switches S 3 ~S6 are all achieved from 20% output load.The secondary-side inductor currents and diode currents of first half bridge circuit are measured and presented in Figure 10a under the rated power.The output currents of three half bridge circuits under the full output power are illustrated in Figure 10b.The test results show the three output currents are well balanced.Figure 11 illustrates the measured efficiencies of the proposed circuit under different load conditions and input voltages.The measured circuit efficiencies of the developed converter are 91.5% at 20% rated power, 93.2% at 50% rated power, and 92.7% at the rated power under 750 V input.At 750 V input and the rated power, the duty ratio is close to 0.5, and the current rating on power devices and inductors are almost balanced.Therefore, the power losses are nearly distributed into each power devices and the circuit efficiency is improved, compared to the low load condition and higher voltage input.8 presents the test results of the gating voltage and drain current of power switch S1 under 20% output load, and the rated output load for both 750 V and 800 V input cases.Before the power switch S1 is turned on, the drain current is a negative value, to discharge the drain voltage.Therefore, the soft switching characteristic of S1 can be realized from 20% output load to the rated output load, based on the test results in Figure 8.
Similarly, the measured waveforms of S2 are presented in Figure 9.It can be observed that the zerovoltage switching characteristic of S2 is also achieved from 20% output load.Since power devices S3 and S5 are operated in the same circuit manner as power device S1, and S4 and S6 are controlled in the same circuit manner as S2, it can be expected that the zero-voltage switching of power switches S3~S6 are all achieved from 20% output load.The secondary-side inductor currents and diode currents of first half bridge circuit are measured and presented in Figure 10a under the rated power.The output currents of three half bridge circuits under the full output power are illustrated in Figure 10b.The test results show the three output currents are well balanced.Figure 11 illustrates the measured efficiencies of the proposed circuit under different load conditions and input voltages.The measured circuit efficiencies of the developed converter are 91.5% at 20% rated power, 93.2% at 50% rated power, and 92.7% at the rated power under 750 V input.At 750 V input and the rated power, the duty ratio is close to 0.5, and the current rating on power devices and inductors are almost balanced.Therefore, the power losses are nearly distributed into each power devices and the circuit efficiency is improved, compared to the low load condition and higher voltage input.

Conclusion
A modular dc-dc converter with magnetic coupling current balance is presented for high power industry power units, dc light rail transportation, or dc microgrid system applications.Three half bridge circuits are employed in the proposed converter with primary-series secondary-parallel connection to lessen the voltage stress of power devices on high voltage side and current stress of passive components on low voltage side.Balance capacitors are used on high voltage side to achieve voltage balance on input split capacitors.In order to achieve current balance of three half bridge circuits, magnetic coupling current balance components are employed on the primary-side.The

Conclusions
A modular dc-dc converter with magnetic coupling current balance is presented for high power industry power units, dc light rail transportation, or dc microgrid system applications.Three half bridge circuits are employed in the proposed converter with primary-series secondary-parallel connection to lessen the voltage stress of power devices on high voltage side and current stress of passive components on low voltage side.Balance capacitors are used on high voltage side to achieve voltage balance on input split capacitors.In order to achieve current balance of three half bridge circuits, magnetic coupling current balance components are employed on the primary-side.The current doubler rectifiers are used on low voltage side to achieve partial ripple current reduction.Asymmetric pulse-width modulation approach is used to control power switches and regulate load voltage.From the experimental results, all power switches can be turned on at zero voltage from 20% output power.The other dc-dc converter topologies, such as full-bridge converter with phase-shift pulse-width modulation and resonant converter with frequency control, can also be applied in the proposed modular dc-dc converter with series-parallel connection with currents sharing and split voltages balance.Full-bridge circuit has two times of switch counts compared to the half-bridge circuits in the proposed converter.That will increase the cost and converter size.The resonant converter with frequency modulation cannot be designed at the optimal condition due to the switching frequency being related to the load condition and input voltage.Based on the analysis of circuit characteristics in Section 3 and the test results, it can be observed that the main drawbacks of the proposed converter, with asymmetric pulse-width modulation scheme, are unbalanced current rating on power devices S 1 ~S6 and D 1 ~D6 , and inductors L 1 ~L6 , due to the duty cycle being related to the load current and input voltage.Similar, the average voltages on dc blocking capacitors C 1 ~C3 are also related to duty cycle.If the proposed converter is operated under duty cycle equals 0.5, then the current rating of all power devices and inductors are balanced.

1 .
Figure 1. Circuit configuration of the developed modular converter for medium voltage applications.

Figure 2
Figure 2 provides the voltage and current waveforms of the studied converter in a switching cycle.Based on the pulse-width modulation waveforms shown in Figure 2, eight operating steps can be observed in each switching cycle under steady state.Power switches S1, S3, and S5 have the same gating signals, and S2, S4, and S6 have the same gating signals.The duty cycle of S1, S3, and S5 denotes d and the duty cycle of S2, S4, and S6 is 1 − d.When S1, S3, and S5 are active, then S2, S4, and S6 are inactive.We can obtain that vCf1 = vCin1 and vCf2 = vCin2.If S1, S3, and S5 are inactive, and S2, S4, and S6 are active, then vCf1 = vCin2 and vCf2 = vCin3.For steady state operation, the capacitor voltages vCin1 = vCin2 =

Figure 1 .
Figure 1. Circuit configuration of the developed modular converter for medium voltage applications.

Figure 2
Figure 2 provides the voltage and current waveforms of the studied converter in a switching cycle.Based on the pulse-width modulation waveforms shown in Figure 2, eight operating steps can be observed in each switching cycle under steady state.Power switches S 1 , S 3 , and S 5 have the same gating signals, and S 2 , S 4 , and S 6 have the same gating signals.The duty cycle of S 1 , S 3 , and S 5 denotes d and the duty cycle of S 2 , S 4 , and S 6 is 1 − d.When S 1 , S 3 , and S 5 are active, then S 2 , S 4 , and S 6 are inactive.We can obtain that v Cf1 = v Cin1 and v Cf2 = v Cin2 .If S 1 , S 3 , and S 5 are inactive, and S 2 , S 4 , and S 6 are active, then v Cf1 = v Cin2 and v Cf2 = v Cin3 .For steady state operation, the capacitor voltages v Cin1 = v Cin2 = v Cin3 = v Cf1 = v Cf2 = V in /3.Before the system analysis, the circuit parameters on

Figure 2 .
Figure 2. Pulse-width modulation waveforms of the proposed converter.

Figure 2 .
Figure 2. Pulse-width modulation waveforms of the proposed converter.
primary-side voltage vab and currents ip1~ip3 at the rated power.It is clear that the three primary-side currents ip1~ip3 are well balanced.The input split voltages and balance capacitor voltage at the rated power are measured and presented in Figure 7.The measured voltages are VCin1 = 251 V, VCin2 = 249.3V, VCin3 = 249.7 V, VCf1 = 251 V, and VCf2 = 249 V under Vin = 750 V input.It is clear that the input split voltages and balance capacitor voltages are well balanced. Figure

Figure 5 .Figure 5 .
Figure 5. Measured waveforms of the gating voltages of S 1 , S 2 , S 3 , and S 5 at the rated power (a) with V in = 750 V and (b) with V in = 800 V.

Figure 9 .
Figure 9. Measured results of the gating voltage and current of S2 under (a) Vin = 750 V and 20% output load, (b) Vin = 750 V and the rated output load, (c) Vin = 800 V and 20% output load, and (d) Vin = 800 V and the rated output load.

Figure 9 .Figure 10 .Figure 10 .
Figure 9. Measured results of the gating voltage and current of S 2 under (a) V in = 750 V and 20% output load, (b) V in = 750 V and the rated output load, (c) V in = 800 V and 20% output load, and (d) V in = 800 V and the rated output load.Electronics 2018, x, x FOR PEER REVIEW 12 of 14

Figure 10 .Figure 11 .
Figure 10.Measured waveforms of the secondary-side currents at the rated output power (a) iL1, iL2, iD1, and iD2 in first half bridge circuit and (b) output currents of three half bridge circuits.

Figure 11 .
Figure 11.Measured efficiencies of the proposed converter.