High-Linearity Self-Biased CMOS Current Buffer

: A highly linear fully self-biased class AB current buffer designed in a standard 0.18 µ m CMOS process with 1.8 V power supply is presented in this paper. It is a simple structure that, with a static power consumption of 48 µ W, features an input resistance as low as 89 Ω , high accuracy in the input–output current ratio and total harmonic distortion (THD) ﬁgures lower than − 60 dB at 30 µ A amplitude signal and 1 kHz frequency. Robustness was proved through Monte Carlo and corner simulations, and ﬁnally validated through experimental measurements, showing that the proposed conﬁguration is a suitable choice for high performance low voltage low power applications.


Introduction
Current mirrors are required not only to generate and replicate bias currents, but also as core cells in many analog and mixed signal applications: current conveyors, current feedback operational amplifiers or current-mode filters, among others, are based on this basic current processing block [1][2][3][4][5][6][7][8][9]. Unfortunately, the power consumption of current-mode circuits proportionally increases as the number of active branches where the current is replicated increases. This limitation, critical for the current low-voltage low-power IC design scenario set by the driving portable market, can be circumvented through class AB operation, which makes it possible to dynamically handle current levels higher than the quiescent bias current [10][11][12][13][14]. Furthermore, self-biasing may be used to establish the DC current in the circuit without any additional bias circuitry in order to optimize the power consumption [15].
The goal of this work is to accomplish a reliable fully self-biased class AB current buffer design. It relies on an active input to attain very low input impedance and high linearity, which is further increased by the coupling of the input and output branches through a single transistor. Preliminary results from a not fully self-biased implementation, i.e., requiring extra bias generation for the cascode transistors and the input amplifier, are presented in [16]. This paper presents the complete fully self-biased design, providing more insight into the operation principle and the actual implementation of the required amplifier and the corresponding compensation network, considering both a single-stage and a two-stage differential amplifier. Simulations including process variations and mismatch effects, as well as experimental results, validate the reliability of the proposed approach.
The circuit was characterized and compared with two other widely used class AB buffers designed with the same technology, same power supply and for the same input current range. The first is a quasi-floating gate current buffer (QFG-CB) and the second is a current-conveyor based current buffer (CC-CB). These topologies were chosen for their class AB operation as well as for their ability to keep the input node at a constant DC input voltage V dc (virtual ground), as the proposed circuit does. This is a desirable characteristic in many cases, and becomes essential in some particular configurations based on MOS current dividers [17][18][19]. A particular case where this feature is exploited is the sign circuit required within the neuron of an analog neural system used to calibrate sensors [20,21] (see Figure 1). This sign circuit is required to determine the direction of the current flowing through a multiplier, thus allowing both positive and negative synaptic weights [22]. This particular application motivated the design of the proposed self-biased buffer configuration, with the key requirements of providing the highest possible accuracy and linearity response with a reduced power consumption and a compact size.  The paper is organized as follows: Section 2 presents the operation principle of the proposed buffer. The differential amplifiers and the compensation techniques used to ensure the buffer stability are also presented in this section. In Section 3, the current buffer is thoroughly characterized for both a single-stage and a two-stage amplifier as active input components to show the corresponding trade-offs. A comparison with two other widely used class AB current buffers with a well defined input voltage is also made. Measurement results of the integrated current buffer prototype and a comparison with other integrated circuits are presented in Section 4 and, finally, conclusions are drawn in Section 5.

Proposed Self-Biased Current-Buffer
The proposed self-biased current buffer (SB-CB) is shown in Figure 2. A Differential Amplifier (DA) sets the input voltage at V dc and establishes a virtual ground at this node. The quasi-floating gate (QFG) approach is used to achieve class AB operation [23][24][25][26][27][28][29][30], since this technique requires no additional current and adds minimum hardware penalty, leading to a power efficient and compact solution. In static conditions, the bias current I Bias is determined by the dimensions of the PMOS (P-type metal-oxide-semiconductor) transistors M p1 and M p2 , which are diode-connected and equally sized. Therefore, the same current flows through each NMOS (N-type metal-oxide-semiconductor) transistor M n1 and M n2 , whereas M 1 sinks twice the bias current.
Under dynamic conditions, the PMOS transistors act as dynamic current sources. If the input current flows out of the buffer, the current flowing through M n1 and M n2 decreases and so does the tail current in transistor M 1 . Due to the RC coupling formed by capacitance C and resistances R large , the gate voltage of M p1 and M p2 drops and their current driving capability increases. Hence, the bias current of the buffer is lower than the input current that can be handled. Neglecting channel-length modulation, the current transfer function is given by: where A d is the gain of the differential amplifier and g m i is the transconductance of transistor M i . If a unity current gain, i.e., a current buffer, is required, the transconductance ratios g m p2 /g m p1 and g m n2 /g m n1 must both be equal to 1. The input resistance R in is the parallel of the equivalent resistance R inP seen from the input to V DD , and the equivalent R inN seen from the input to ground: As expected, R in can be reduced by increasing the differential amplifier gain A d . The output resistance R out is given by: R out is dominated by the equivalent resistance of the diode connection of transistor M p1 , so it may be lower than in other current buffer implementations. However, as shown below, a 2.4 MΩ output resistance was achieved in our design, which is still suitable for many applications.
The proposed SB-CB was designed in a standard 0.18 µm CMOS process with 1.8 V supply voltage. The transistor sizes are shown in Table 1. The channel length is L ≥ 1 µm in all cases in order to reduce mismatch effects. The sizes were chosen so the buffer would be able to handle input currents up to 15 µA amplitude with a nominal bias current I Bias = 8 µA. The coupling Metal-Insulator-Metal (MIM) capacitor has a value C = 1 pF. The resistances R large were implemented with minimum-size diode-connected MOS transistors in the cutoff region [31], as they do not need to have a precise value as long as the cutoff frequency f c = 1/[2πR large C] is lower than the signal frequency. Cascode transistors improve the accuracy in the current copy, and the self-bias scheme shown in Figure 2 was used to establish the required BiasP and BiasN voltages [32]. Finally, an NMOS transistor not shown in the figure was connected to the input node as start-up circuit. Table 1. Transistors aspect ratios for the proposed buffer.
To analyze the stability of the SB-CB, it must be noted that the open-loop gain is given by: where A d is the gain of the differential amplifier DA and A cs is the gain of the common-source stage, i.e., transistor M 1 : First, a current buffer SB-CB1 where the DA is a single-stage PMOS differential pair with active load will be considered. When opening the feedback loop, a two-stage configuration results, as shown in Figure 3. To ensure stability, Miller compensation is applied. The bias current is set to 500 nA and derived from the current buffer itself. The amplifier shows 40 dB gain and the buffer is compensated with a Miller capacitance C comp = 300 fF, attaining 82 • phase margin for BW = 4.1 MHz.  As shown in Equation (4), a higher gain differential amplifier will decrease the input impedance. Furthermore, the linearity is expected to increase by the virtual ground set at the input node. Therefore, a two-stage amplifier was also designed to explore the impact of the amplifier on the overall performance of the buffer. If the DA is a two-stage amplifier, the open-loop configuration turns into a three-stage amplifier, as shown in Figure 4. To achieve stability, nested-Miller compensation can be applied. This technique requires the second stage in the differential amplifier not to invert the signal, so the amplifier has to be accordingly designed [33][34][35].  As shown in Figure 4, the two-stage DA was implemented with two cascaded PMOS differential pairs. An additional differential pair, not shown in the figure, was used to set the required bias voltage V bias at the negative input of the second stage so the current distribution through its branches is symmetrical. Again, the bias currents were derived from the current buffer itself. Each differential pair is biased with 500 nA and the two-stage DA gain is 78 dB. The compensation capacitors values are C C1 = 400 fF and C C2 = 100 fF. The phase margin with the nested-Miller compensation is PM = 62 • for a bandwidth (BW) of 3 MHz.

Performance Characterization
For the sake of comparison, simulations were carried out for the self-biased buffer both with a single-stage amplifier (SB-CB1) and a two-stage amplifier (SB-CB2) as DA. Figure 5 shows the output current and the relative error in the copy of current as a function of the input current. The SB-CB2 shows lower relative error in the transfer current. Considering a minimum input current I in = 100 nA, the maximum relative error is 0.09% for the SB-CB2 and 0.24% for the SB-CB1. If the minimum input current is reduced to I in = 10 nA, the maximum relative error increases to 0.75% for the SB-CB2 and 2.08% for the SB-CB1.
As for linearity, both current buffers show very low harmonic distortion. The THD for a 15 µA amplitude input current remains below −60 dB up to 100 kHz for the SB-CB2 and up to 30 kHz for the SB-CB1. Figure 6 shows THD versus frequency for both configurations. Figure 7 shows the time response to a 30 µA pp input current step for both SB-CBs. For the SB-CB1, the rise time is 1.23 µs and the fall time is 898 ns, both considering the response within 0.1% of the output signal. As for the SB-CB2 the rise time is 947 ns and the fall time is 1.13 µs under the same conditions. Table 2 summarizes the main electrical characteristics of the proposed buffers SB-CB1 and SB-CB2. As expected, SB-CB2 shows higher linearity and lower input resistance than SB-CB1 with a slight increment in power consumption. Table 2 also shows the characteristics of two other widely used class AB current buffers with a virtual ground at the input node. For a fair comparison, these buffers were redesigned in the same 0.18 µm CMOS process with 1.8 V supply and for the same input current range I in = ±15 µA.  The Quasi-Floating Gate Current-Buffer (QFG-CB) is presented in [26] and, as in the proposed SB-CB, the bias transistors act as dynamic current sources. The two-stage differential amplifier shown in Figure 4 was used in the design of the QFG-CB, and, again, nested-Miller compensation was used to ensure stability. The second configuration considered for comparison is the Current Conveyor based Current Buffer (CC-CB) [36][37][38][39][40][41]. Figure 8 shows both the schematic circuits and the transistor sizes of the aforementioned class AB current buffers. According to Table 2, the QFG-CB and the proposed circuit have higher estimated active area than the CC-CB due the MIM capacitors used for the QFG technique. However, if only the number of transistors is considered, the proposed circuit has the smallest area.
The bias current I Bias is lowest for the QFG-CB, which results in the lowest power consumption, both static and dynamic. However, it should be mentioned that both the QFG-CB and CC-CB require additional biasing schemes which are not considered in the comparison.
The QFG-CB and the proposed SB-CB2 show the lowest relative error in the copy of current. At an input current I in = 100 nA, the relative error remains below 0.1% for both circuits, and, even considering an input current I in = 10 nA, the relative error remains below 0.8% in both cases, whereas the error of the CC-CB rises to 45%, which is unbearable in practical cases. As for the THD@30 µA pp , it remains below −60 dB up to 100 kHz both for the SB-CB2 and for the QFG-CB. The CC-CB, in contrast, shows a THD higher than −55 dB even at low frequencies. The proposed buffer shows the lowest input resistance, thanks both to the negative feedback established by the amplifier and to the diode-connection of the PMOS transistors. However, as expected, it also shows the lowest output resistance. A transistor working in saturation could be added in series with the diode-connected transistor to increase R out . To keep the circuit symmetry, it would be necessary to also add another transistor to the input branch, but, from Equations (2)-(4), it can be seen that the input resistance may still be very low as long as the amplifier gain is sufficiently high. Finally, the proposed buffer shows the highest bandwidth.
To prove the robustness of the proposed self-biased buffers, corner process simulations were carried out and Table 3 shows the results. To ensure proper operation under all conditions, even when the bias current is reduced because of process variations, the transistors M p1 and M p2 were oversized in the design stage. The bias current I Bias decreases down to 6.5 µA in the slow-slow corner but performance is not affected and the THD for a 30 µA pp input current at 1 kHz remains below −80 dB for all cases. In the fast-fast corner, I Bias increases up to 10 µA, therefore increasing the total power consumption to 38.7 µW for the SB-CB1 and 41.6 µW for the SB-CB2. As for the QFG-CB and CC-CB topologies, their robustness to process variations depends on the robustness of the external biasing circuit.
Finally, Monte Carlo simulations were carried out to verify the circuit operation under mismatch. The mean value and the standard deviation of main electrical parameters considering 500 samples are summarized in Table 4. In the proposed buffers, SB-CB1 and SB-CB2, the mean value for the gain distribution is practically 1 with the same 0.7% standard deviation. The SB-CB1 shows a higher mean offset value than SB-CB2, but the latter presents a higher standard deviation. As for THD, the mean value is lower than −66 dB for both circuits considering a 15 µA amplitude and 1 kHz frequency input signal. Linearity is therefore primarily degraded by mismatch and, according to these results, the actual THD is almost the same for the single-stage and the two-stage implementations. The SB-CB2 implementation may still be preferred if a very low input resistance is required, as is the case for example in configurations based on MOS current dividers [17,18]. Table 4 also shows that I Bias is very robust to mismatch variations, and therefore so is the overall power consumption.  By comparing the proposed SB-CB2 with the two other buffers, results show that the three implementations have a mean value in gain of nearly 1, showing the CC-CB the lowest standard deviation and the SB-CB2 the highest. The proposed SB-CB2 and the QFG-CB show similar offset mean value, but the SB-CB2 shows again the highest standard deviation. In Figure 9 the THD distribution is represented for all three implementations. The CC-CB shows the worst mean value of THD but the lowest standard deviation. The proposed self-biased buffer, in turn, is the most sensitive to mismatching, but still shows the highest linearity.

Experimental Results
The self-biased current buffer SB-CB2 was integrated in the UMC (United Microelectronics Corporation) 0.18 µm CMOS technology with 1.8 V power supply. Figure 10 shows the microphotograph of the circuit and the layout. The circuit implementation occupies an area of 143 µm × 43 µm and exhibits a power consumption of 48 µW. Accordingly, the bias current is estimated to be 12 µA, which is a bit higher than expected from the results in Table 3. This increase in the bias current in turn results in an increase in the current capability of the buffer. A PCB (Printed Circuit Board) was designed to carry out the characterization process. Figure 11a shows this PCB, and Figure 11b shows the photograph of the test setup. As the circuit processes the signal in the current domain, current conversion is necessary at both the input and the output. By means of a 10 kΩ resistance connected at the input node, the input current was generated, whereas the output current was measured through an external transimpedance amplifier configured with a TL081 integrated circuit [42]. This is detailed in Figure 12, which shows a block diagram of the interconnections within the PCB, as well as the methodology followed to carry out the experimental measurements after the circuit has been fabricated. First, the current buffer was characterized under static conditions to obtain the DC characteristics and verify that the prototype is properly biased. Then, the time response was observed in the oscilloscope to test the current capability and accuracy of the buffer, as well as the settling time and input resistance. Finally, the frequency response and the harmonic distortion were characterized.
The circuit response to a 60 µA pp sine input current at 1 kHz frequency is shown in Figure 13. This is the maximum output current that the buffer can handle before the signal starts getting distorted. The input-output characteristic is shown in Figure 14 for a −30 µA to +30 µA current range. A maximum relative error e r = 1.35% is obtained, as also shown in Figure 14.
The input resistance was estimated from the response in the time domain, by measuring the input node voltage and calculating the derivative with respect to the input current. A 89 Ω input resistance was obtained.  If a 60 µA pp input current step is considered, the circuit shows a rise time of 8.6 µs and a fall time of 8.4 µs, both considering the response within 0.1% of the output signal. Figure 15 shows the oscilloscope screenshots of the buffer response to both the rising and falling edges of the input step for this dynamic characterization. The THD characterization was done using the signal analyzer ROHDE & SCHWARZ FSV-Signal Analyzer (10 Hz-6 GHz) [43]. Figure 16 shows the spectrum analyzer screenshots when considering a 60 µA pp sine input signal at 1 kHz ( Figure 16a) and 10 kHz (Figure 16b). Both the frequency spectrum and the THD calculation are shown, considering ten harmonic components. The integrated prototype shows a −61 dB THD for the 60 µA pp input current at 1 kHz, and −53 dB at 10 kHz. These values correspond to the distortion specifications of the signal generator, so lower distortion values are actually expected.
Finally, the transfer function in the frequency domain was determined using the network analyzer E5061B ENA [44], as shown in Figure 17. Note that the bandwidth was reduced because of the parasitic capacitances of the chip package and the interconnection setup used for the characterization.
The self-biased current buffer electrical characteristics are summarized in Table 5, where a comparison with other topologies found in the literature is also presented. All the buffers presented in the table are based on the quasi-floating gate technique.
Note that, although the proposed circuit requires the highest bias current, it does not have a significant impact on the final consumption. Furthermore, the bias circuit of the other topologies has not been considered when estimating their power consumption.
The buffer in [26] and the proposed circuit show the lowest input resistance of 25 Ω and 89 Ω, respectively, so that a virtual ground is set at the input node, and therefore a higher linearity is observed when the maximum input current is considered in each case. The best experimental distortion figure is obtained in [26], at the cost of increased power consumption, which is almost three times the proposed SB-CB consumption. The buffers in [28,29] both present competitive power consumption, but with a rather high R in (934 Ω and 4.8 kΩ, respectively). A higher distortion of −40 dB is observed in [28] for the maximum input current; even if a lower input current of 30 µA amplitude is considered, the THD is not higher than −53 dB. Similarly, the buffer presented in [29] shows a THD of −41 dB for a current I in = 100 µA pp .
Finally, the proposed SB-CB shows the lowest integration area, whereas the circuit presented in [29] has the highest dimensions because it uses three capacitors to achieve the class-AB operation.

Conclusions
A self-biased class AB 1.8 V-0.18 µm CMOS current buffer based on the QFG approach is proposed in this paper. It shows the lowest input resistance and highest linearity when compared to other class AB current buffers with a virtual ground at the input node, at a cost of higher power consumption. However, as the proposed topology is self-biased, it does not require any additional circuitry, whereas other buffers require a biasing scheme. Monte Carlo and process corner simulations show that, even though the proposed buffer is more sensitive to process variations, it still shows the best performance in terms of linearity.
The integrated prototype was able to copy an input current ranging from −30 µA to +30 µA with a maximum relative error of 1.35% and 48 µW static power consumption. The prototype has a reduced area of 143 × 43 µm 2 , making it a viable solution for battery-operated systems where minimum dimensions and low power operation are mandatory. The THD for the same amplitude input current remains below −53 dB up to 10 kHz, showing a high linearity characteristic even when the maximum input current is considered. The circuit also has a very low input resistance R in = 89 Ω, thus setting a virtual ground at the input node, a relatively high output impedance and a circuit response time of 8.6 µs.