AlGaN / GaN MIS-HEMT with PECVD SiN x , SiON , SiO 2 as Gate Dielectric and Passivation Layer

Three different insulator layers SiNx, SiON, and SiO2 were used as a gate dielectric and passivation layer in AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMT). The SiNx, SiON, and SiO2 were deposited by a plasma-enhanced chemical vapor deposition (PECVD) system. Great differences in the gate leakage current, breakdown voltage, interface traps, and current collapse were observed. The SiON MIS-HEMT exhibited the highest breakdown voltage and Ion/Ioff ratio. The SiNx MIS-HEMT performed well in current collapse but exhibited the highest gate leakage current density. The SiO2 MIS-HEMT possessed the lowest gate leakage current density but suffered from the early breakdown of the metal–insulator–semiconductor (MIS) diode. As for interface traps, the SiNx MIS-HEMT has the largest shallow trap density and the lowest deep trap density. The SiO2 MIS-HEMT has the largest deep trap density. The factors causing current collapse were confirmed by Photoluminescence (PL) spectra. Based on the direct current (DC) characteristics, SiNx and SiON both have advantages and disadvantages.


Introduction
In the past decades, the wide bandgap semiconductor material, gallium nitride (GaN), attracted great attention due to its wide bandgap, high breakdown electric field, and excellent thermal properties [1].Gate leakage current and current collapse are the main issues that limit the performance of AlGaN/GaN high-electron-mobility transistors (HEMTs).To overcome these problems, different dielectric materials have been proposed for the fabrication of metal-insulator-semiconductor (MIS) HEMTs, such as SiO 2 [2][3][4][5][6], SiN x [7][8][9][10][11], SiONe [12][13][14], ZrO 2 [15], Al 2 O 3 [16][17][18], and HfO 2 [19], etc.Each material has advantages and disadvantages.Some groups studied stack dielectric layers like SiN x /Al 2 O 3 [20] and SiN x /SiO 2 [21] to improve leakage current and stability.The Al 2 O 3 and HfO 2 gate dielectric layer deposited by atomic layer deposition (ALD) has shown advantages in reducing gate leakage and eliminating current collapse [22,23].However, Al 2 O 3 and HfO 2 are not suitable as passivation layers due to the low deposition rate of ALD.The plasma-enhanced chemical vapor deposition (PECVD) is one of the key sectors in conventional GaN-based light emitting diode (LED) production lines and complementary metal-oxide-semiconductor (CMOS) production lines.Thus, lots of work has been done on PECVD-deposited silicon nitride, silicon oxide, and silicon oxynitride.Compared to SiN x , SiO 2 has a larger conduction band offset with GaN, which is related to leakage current.However, SiN x has a relatively higher dielectric constant (~7), which contributes to better gate control of two dimensional electron gas ( 2DEG).As a trade-off, SiON can be modulated to retain some advantages from both SiN x and SiO 2 and has been proved to be a good candidate for a gate dielectric [12].Considering the passivation effect, these dielectric layers can reduce the surface states, modulate the strain, and improve the reliability [24][25][26].Although some comparisons have been made on the above materials [13,27,28], some published data are often controversial and the overall result is still not sufficiently clear.This shows that many questions are still unanswered and a better understanding of the passivation effect on the device performance is required.
In this work, we have made comprehensive comparisons between MIS-HEMTs with PECVDdeposited SiN x , SiON, and SiO 2 as a gate dielectric and passivation layer.The differences in direct current (DC) static characteristics and current collapse were investigated.The interface traps were studied by Capacitance versus Voltage (C-V) measurements and a pulse mode drain current versus gate-to-source voltage (Id-V gs ) test.The Photoluminescence (PL) spectra test was also applied to confirm the passivation effectiveness.

Materials and Methods
The AlGaN/GaN epilayer used in this work is grown on Si (111) substrate using metal-organic chemical vapor deposition (MOCVD).The epitaxial structure consists of a 3.5 µm GaN buffer layer, a 300 nm GaN channel layer, a 1 nm AlN interlayer, a 22 nm Al 0.23 Ga 0.77 N barrier layer, and a 3 nm GaN cap layer.A 2DEG mobility of 1831 cm 2 /V•s and a sheet carrier concentration of 8.3 × 10 12 cm −2 are measured by Hall effect measurement.
The device fabrication of MIS-HEMT started with the cleaning of the epitaxial wafer with a standard solvent.Then, devices were isolated using BCl 3 and Cl 2 etching in an Inductively Coupled Plasma (ICP) system.Prior to the deposition of ohmic metal, surface treatment was performed by immersing in HCL for 60 s.The Ti/Al/Ni/Au metal stack was then deposited by E-beam evaporation.Rapid temperature annealing at 850 • C for 1 min in a N 2 environment was then performed to form ohmic contact.The contact resistance was 2.11 Ω•mm and the specific contact resistance was 1.75 × 10 −4 Ω cm 2 , as extracted by a circular transmission line model.After that, SiN x , SiON, and SiO 2 dielectric layers with a thickness of 20 nm were deposited separately on the surfaces of different AlGaN/GaN samples using PECVD.Additionally, a Si dummy wafer and an AlGaN/GaN dummy wafer were loaded, together with the sample, in each deposition process.The dielectric/AlGaN/GaN samples were used for PL spectra measurement.The thickness and refractive index of deposited thin films were measured for the dummy wafer using an ellipsometer.The deposition properties of SiN x , SiON, and SiO 2 are listed in Table 1.The dielectric layers above drain and source electrodes were then removed by ICP.Finally, all samples were carried out using the same gate contact process.A Ni/Au (50/150 nm) gate metal was deposited by E-Beam evaporation.All samples have the same epitaxial structure and fabrication process, except for the type of dielectric layers.The MIS-HEMTs with different dielectric layers are labeled as SiN x MIS-HEMT, SiON MIS-HEMT, and SiO 2 MIS-HEMT, respectively.Figure 1 shows the schematic cross-sectional view of MIS-HEMT.The gate length L G , gate width W G , gate to drain distance L GD , and gate to source distance L GS are 3, 150, 20, and 10 µm, respectively.

Results and Discussion
Table 2 shows some selected properties of MIS-HEMTs.The typical DC output characteristics of SiNx MIS-HEMT, SiON MIS-HEMT, and SiO2 MIS-HEMT are shown in Figure 2a-c.The drain current densities at drain-to-source voltage Vds = 20 V and gate-to-source voltage Vgs = 8 V are 623 mA/mm, 590 mA/mm, and 620 mA/mm, respectively, for SiNx MIS-HEMT, SiON MIS-HEMT, and SiO2 MIS-HEMT.The specific on-resistance extracted at Vds = 3 V is 9.89 Ω•mm, 11.6 Ω•mm, and 11.4 Ω•mm, respectively.These output characteristics show that the SiNx MIS-HEMT has the highest maximum drain current and lowest static on-resistance.Figure 2d shows the off-state breakdown characteristics measured at Vgs = −18 V. SiON MIS-HEMT exhibits a higher breakdown voltage compared with the other two samples.SiNx performs slightly better in improving the saturated drain current of MIS-HEMT, and SiON can withstand a higher electric field strength.

Results and Discussion
Table 2 shows some selected properties of MIS-HEMTs.The typical DC output characteristics of SiN x MIS-HEMT, SiON MIS-HEMT, and SiO 2 MIS-HEMT are shown in Figure 2a-c.The drain current densities at drain-to-source voltage Vds = 20 V and gate-to-source voltage V gs = 8 V are 623 mA/mm, 590 mA/mm, and 620 mA/mm, respectively, for SiN x MIS-HEMT, SiON MIS-HEMT, and SiO 2 MIS-HEMT.The specific on-resistance extracted at Vds = 3 V is 9.89 Ω•mm, 11.6 Ω•mm, and 11.4 Ω•mm, respectively.These output characteristics show that the SiN x MIS-HEMT has the highest maximum drain current and lowest static on-resistance.Figure 2d shows the off-state breakdown characteristics measured at V gs = −18 V. SiON MIS-HEMT exhibits a higher breakdown voltage compared with the other two samples.SiN x performs slightly better in improving the saturated drain current of MIS-HEMT, and SiON can withstand a higher electric field strength.

Results and Discussion
Table 2 shows some selected properties of MIS-HEMTs.The typical DC output characteristics of SiNx MIS-HEMT, SiON MIS-HEMT, and SiO2 MIS-HEMT are shown in Figure 2a-c.The drain current densities at drain-to-source voltage Vds = 20 V and gate-to-source voltage Vgs = 8 V are 623 mA/mm, 590 mA/mm, and 620 mA/mm, respectively, for SiNx MIS-HEMT, SiON MIS-HEMT, and SiO2 MIS-HEMT.The specific on-resistance extracted at Vds = 3 V is 9.89 Ω•mm, 11.6 Ω•mm, and 11.4 Ω•mm, respectively.These output characteristics show that the SiNx MIS-HEMT has the highest maximum drain current and lowest static on-resistance.Figure 2d shows the off-state breakdown characteristics measured at Vgs = −18 V. SiON MIS-HEMT exhibits a higher breakdown voltage compared with the other two samples.SiNx performs slightly better in improving the saturated drain current of MIS-HEMT, and SiON can withstand a higher electric field strength.Figure 3d plots the gate-to-source two-terminal leakage current curve when V gs changes from 5 to −40 V with drain electrode dangling.The gate-to-source leakage current (Igs) density of SiN x MIS-HEMT is 4.46 × 10 −4 mA/mm at V gs = 20 V, which is 1 order larger than that of SiON or SiO 2 MIS-HEMT.This can be attributed to the lower conduction band offset of SiN x from GaN [12].As for SiO 2 MIS-HEMT, there is a rapid increase of leakage current when the gate voltage bias is lower than −35 V.This phenomenon means that the SiO 2 dielectric layers are more easily damaged than SiN x and SiON. Figure 3d plots the gate-to-source two-terminal leakage current curve when Vgs changes from 5 V to −40 V with drain electrode dangling.The gate-to-source leakage current (Igs) density of SiNx MIS-HEMT is 4.46 × 10 −4 mA/mm at Vgs = 20 V, which is 1 order larger than that of SiON or SiO2 MIS-HEMT.This can be attributed to the lower conduction band offset of SiNx from GaN [12].As for SiO2 MIS-HEMT, there is a rapid increase of leakage current when the gate voltage bias is lower than −35 V.This phenomenon means that the SiO2 dielectric layers are more easily damaged than SiNx and SiON.The transfer curves of the three samples are shown in Figure 3a-c.The drain voltage was fixed at 15 V, and the minimum gate voltage was −20 V, −14 V, and −12 V, respectively, for SiNx MIS-HEMT, SiON MIS-HEMT, and SiO2 MIS-HEMT.The drain current, Id, is almost equal to the gate current, Ig, in the off-state for all samples.This result reveals that the off-state drain leakage current is mainly from the gate electrode.As a result, the comparison of the off-state drain currents of these two samples agrees with the two-terminal gate leakage current.A high Ion/Ioff ratio > 10 7 was observed on SiON MIS-HEMT and SiO2 MIS-HEMT, which is two orders larger than SiNx MIS-HEMT.
To investigate the interface condition of the three samples, a forward and backward C-V measurement with a frequency of 1 MHz was applied.As shown in Figure 4, each C-V curve has two rising slopes.The 1st slope represents the completed depletion of 2DEG and the 2nd slope indicates the electron transfer from AlGaN/GaN to dielectric/AlGaN interface [29,30].A relatively low voltage corresponding to the 1st slope is observed in the SiNx MIS structure.This may be attributed to the fixed charge in the dielectric/AlGaN interface.Some researches show that a large amount of fixed The transfer curves of the three samples are shown in Figure 3a-c.The drain voltage was fixed at 15 V, and the minimum gate voltage was −20 V, −14 V, and −12 V, respectively, for SiN x MIS-HEMT, SiON MIS-HEMT, and SiO 2 MIS-HEMT.The drain current, Id, is almost equal to the gate current, Ig, in the off-state for all samples.This result reveals that the off-state drain leakage current is mainly from the gate electrode.As a result, the comparison of the off-state drain currents of these two samples agrees with the two-terminal gate leakage current.A high I on /I off ratio > 10 7 was observed on SiON MIS-HEMT and SiO 2 MIS-HEMT, which is two orders larger than SiN x MIS-HEMT.
To investigate the interface condition of the three samples, a forward and backward C-V measurement with a frequency of 1 MHz was applied.As shown in Figure 4, each C-V curve has two rising slopes.The 1st slope represents the completed depletion of 2DEG and the 2nd slope indicates the electron transfer from AlGaN/GaN to dielectric/AlGaN interface [29,30].A relatively low voltage corresponding to the 1st slope is observed in the SiN x MIS structure.This may be attributed to the fixed charge in the dielectric/AlGaN interface.Some researches show that a large amount of fixed charges exist in the dielectric layer and dielectric/AlGaN interface [31][32][33][34][35], differing from interface traps analyzed in the work, these kinds of fixed charges are not modulated by the gate voltage and do not lead to voltage hysteresis.Therefore, they have a negligible effect on the CV hysteresis measurement.However, the positive fixed charge would cause a negative voltage shift of the flat band voltage (V FB ), and thus lead to a low threshold voltage, V th [33].More investigation concerning fixed charges is needed in the future.In the CV curve, the backward hysteresis and threshold voltage shifts are always attributed to interface traps.The inset of Figure 4 shows that there is little voltage shift on the 2nd slope while obvious hysteresis occurred on the 1st slope of the SiON and SiO 2 MIS sample.This phenomenon occurs because larger number of deep traps with long emission time constants appear in the SiON and SiO 2 MIS structure.We also used dielectric capacitance in series with the barrier capacitance model to extract the Cox of the three samples [36].The Cox is 297.86,277.82, and 364.82 nF/cm −2 for SiN x , SiON, and SiO 2 MIS-HEMT, respectively.C-V measurement provides a rough comparison of the three structures but its precision is limited by the sweeping rates.The pulsemode Id-V gs measurement was employed for a more accurate extraction of interface states.
charges exist in the dielectric layer and dielectric/AlGaN interface [31][32][33][34][35], differing from interface traps analyzed in the work, these kinds of fixed charges are not modulated by the gate voltage and do not lead to voltage hysteresis.Therefore, they have a negligible effect on the CV hysteresis measurement.However, the positive fixed charge would cause a negative voltage shift of the flat band voltage (VFB), and thus lead to a low threshold voltage, Vth [33].More investigation concerning fixed charges is needed in the future.In the CV curve, the backward hysteresis and threshold voltage shifts are always attributed to interface traps.The inset of Figure 4 shows that there is little voltage shift on the 2nd slope while obvious hysteresis occurred on the 1st slope of the SiON and SiO2 MIS sample.This phenomenon occurs because larger number of deep traps with long emission time constants appear in the SiON and SiO2 MIS structure.We also used dielectric capacitance in series with the barrier capacitance model to extract the Cox of the three samples [36].The Cox is 297.86,277.82, and 364.82 nF/cm −2 for SiNx, SiON, and SiO2 MIS-HEMT, respectively.C-V measurement provides a rough comparison of the three structures but its precision is limited by the sweeping rates.The pulse-mode Id-Vgs measurement was employed for a more accurate extraction of interface states.In this work, the pulse period was fixed at 500 ms and the selected measured pulse widths were 100 μs, 1 ms, 10 ms, 100 ms, and 200 ms.Vds was kept at 1 V to reduce drain-to-gate field-assisted detrapping [29].The inset of Figure 5b shows the forward sweep and backward sweep measurement conditions of Vgs.It is reported that the acceptor-like interface states were originally empty and would capture electrons during the forward sweep of Vgs with a low Vgs base [29]; therefore, the forward sweep curve was chosen to be the basic line.In the backward sweep of Vgs, interface traps with emission times longer than the measurement pulse width would remain occupied by electrons, which would lead to a positive shift of Vth.The detectable traps emission time is related to its energy using Shockley-Read-Hall statistics: In this work, the pulse period was fixed at 500 ms and the selected measured pulse widths were 100 µs, 1 ms, 10 ms, 100 ms, and 200 ms.Vds was kept at 1 V to reduce drain-to-gate field-assisted detrapping [29].The inset of Figure 5b shows the forward sweep and backward sweep measurement conditions of V gs .It is reported that the acceptor-like interface states were originally empty and would capture electrons during the forward sweep of V gs with a low V gs base [29]; therefore, the forward sweep curve was chosen to be the basic line.In the backward sweep of V gs , interface traps with emission times longer than the measurement pulse width would remain occupied by electrons, which would lead to a positive shift of V th .The detectable traps emission time τ is related to its energy using Shockley-Read-Hall statistics: where v th , σ n , and N C are the electron thermal velocity, electron capture cross-section, and electron concentration at the effective density of states in the conduction band in GaN.∆E = E C − E T is the energy gap between the conduction band and interface trap.k is the Boltzman constant and T is the temperature.
where Cox values were extracted from C-V curves and the threshold voltage shift ∆ values were extracted from the results shown in Figure 5a-c.
Using Equations ( 1) and ( 2), Qit with different ranges of ∆E were extracted and are shown in Figure 5d.At ∆E > 0.460 eV, the Qit is 1.02 × 10 cm , 3.54 × 10 , and 4.49 × 10 for SiNx, SiON, and SiO2 MIS-HEMT, respectively.At ∆E > 0.657 eV, the Qit turns out to be 1.38 × 10 , 2.31 × 10 , and 4.13 × 10 , respectively.SiN MIS-HEMT has the largest detected Qit at ∆E > 0.460 eV.These kinds of interface traps have an emission time longer than 100 μs.In the backward sweep of Vgs, these traps would remain occupied by an electron, and lead to the largest Vth shift observed in SiNx MIS-HEMT.In addition, the detectable Qit density of the SiNx sample includes a number of 8.81 × 10 located at 0.460 eV < ∆E < 0.657 eV.These kind of traps (acceptor like) are regarded as shallow traps with short emission times.As for the SiO2 MIS-HEMT, the difference between Qit at ∆E > 0.460 eV and Qit at ∆E > 0.657 eV is small, which indicates For SiN x MIS-HEMT, the forward V gs base was −20 V.For SiON and SiO 2 MIS-HEMT, the forward V gs base was −14 V.The backward V gs base was 5 V for all three samples.As shown in Figure 5a-c, SiN x MIS-HEMT shows a strong correlation between the measurement pulse width and the threshold voltage shift.SiO 2 MIS-HEMT shows little V th change with different pulse widths.The corresponding interface-trapped charge density (Q it ) can be determined by: where C ox values were extracted from C-V curves and the threshold voltage shift ∆V th values were extracted from the results shown in Figure 5a-c.Using Equations ( 1) and ( 2), Q it with different ranges of ∆E were extracted and are shown in Figure 5d.At ∆E > 0.460 eV, the Q it is 1.02 × 10 13 cm −2 , 3.54 × 10 12 cm −2 , and 4.49 × 10 12 cm −2 for SiN x , SiON, and SiO 2 MIS-HEMT, respectively.At ∆E > 0.657 eV, the Q it turns out to be 1.38 × 10 12 cm −2 , 2.31 × 10 12 cm −2 , and 4.13 × 10 12 cm −2 , respectively.SiN MIS-HEMT has the largest detected Q it at ∆E > 0.460 eV.These kinds of interface traps have an emission time longer than 100 µs.In the backward sweep of V gs , these traps would remain occupied by an electron, and lead to the largest V th shift observed in SiN x MIS-HEMT.In addition, the detectable Q it density of the SiN x sample includes a number of 8.81 × 10 12 cm −2 located at 0.460 eV < ∆E < 0.657 eV.These kind of traps (acceptor like) are regarded as shallow traps with short emission times.As for the SiO 2 MIS-HEMT, the difference between Q it at ∆E > 0.460 eV and Q it at ∆E > 0.657 eV is small, which indicates that most of its interface traps are deep traps.In conclusion, SiN x MIS-HEMT has the largest density of shallow interface traps and the lowest density of deep traps among the three samples.SiO 2 MIS-HEMT has the lowest density of shallow traps and largest density of deep traps.The performance of SiON MIS-HEMT is between the SiN x and SiO 2 sample.These results explain the difference in hysteresis in the 1st slope of the C-V curve.The larger deep trap densities of SiON and SiO 2 MIS-HEMT are responsible for the hysteresis in the 1st slope of the C-V curve.In addition, these calculated results show that shallow energy levels are more likely to be occupied by traps in the SiN x /AlGaN interface than in the SiON/AlGaN interface and SiO 2 /AlGaN interface.This offers chances for electron hopping, which could partially explain why SiN x MIS-HEMT has the highest gate leakage current and the lowest I on /I off ratio among the three samples.
The Off-state Current collapse characteristic was measured by a slow switching test using an Agilent B1505A power device analyzer [37].Various stress voltages from 5 V up to 50 V were applied on drain-to-source electrodes when V gs was fixed at −18 V to ensure that the channel was pinched off.After the stress situation for 10 s, V gs was changed to 0 V and the on-state Id-Vd curve was measured.In addition, the time interval was 10 ms between the two data points.This would lead to trap discharging and recover the current collapse to some extent.Therefore, the deep traps would be the major factor causing current collapse.Figure 6a-c shows that the degradation of the drain current was 11.6%, 71.26%, and 84.14%, respectively, for SiN x MIS-HEMT, SiON MIS-HEMT, and SiO 2 MIS-HEMT.As Figure 6d shows, the dynamic Ron increases more quickly along with off-state drain bias stress (Vdstress) for SiO 2 MIS-HEMT.After 50 V Vdstress was applied to the devices, the ratio of dynamic Ron and static Ron turns out to be 1.18, 5.64, and 24.5, respectively, for SiN x MIS-HEMT, SiON MIS-HEMT, and SiO 2 MIS-HEMT.Among these three samples, SiN x MIS-HEMT shows better performance with regard to suppressing the current collapse than the other two samples.Though SiN x MIS-HEMT has the largest detected interface trap density, most of them are relatively shallow traps located at 0.46 eV < ∆E < 0.657 eV.These kinds of shallow traps contribute less to current collapse.SiON and SiO 2 MIS-HEMT have higher trap density than SiN x MIS-HEMT at ∆E > 0.657 eV.This leads to more serious current collapse observed in SiON and SiO 2 MIS-HEMT.The current collapse performance coincides with the extracted results of C-V and pulse Id-V gs measurements for interface deep traps, which indicates that deep interface traps strongly influence the collapse characteristic.The Off-state Current collapse characteristic was measured by a slow switching test using an Agilent B1505A power device analyzer [37].Various stress voltages from 5 V up to 50 V were applied on drain-to-source electrodes when Vgs was fixed at −18 V to ensure that the channel was pinched off.After the stress situation for 10 s, Vgs was changed to 0 V and the on-state Id-Vd curve was measured.In addition, the time interval was 10 ms between the two data points.This would lead to trap discharging and recover the current collapse to some extent.Therefore, the deep traps would be the major factor causing current collapse.Figure 6a-c shows that the degradation of the drain current was 11.6%, 71.26%, and 84.14%, respectively, for SiNx MIS-HEMT, SiON MIS-HEMT, and SiO2 MIS-HEMT.As Figure 6d shows, the dynamic Ron increases more quickly along with off-state drain bias stress (Vdstress) for SiO2 MIS-HEMT.After 50 V Vdstress was applied to the devices, the ratio of dynamic Ron and static Ron turns out to be 1.18, 5.64, and 24.5, respectively, for SiNx MIS-HEMT, SiON MIS-HEMT, and SiO2 MIS-HEMT.Among these three samples, SiNx MIS-HEMT shows better performance with regard to suppressing the current collapse than the other two samples.Though SiNx MIS-HEMT has the largest detected interface trap density, most of them are relatively shallow traps located at 0.46 eV < ∆E < 0.657 eV.These kinds of shallow traps contribute less to current collapse.SiON and SiO2 MIS-HEMT have higher trap density than SiNx MIS-HEMT at ∆E > 0.657 eV.This leads to more serious current collapse observed in SiON and SiO2 MIS-HEMT.The current collapse performance coincides with the extracted results of C-V and pulse Id-Vgs measurements for interface deep traps, which indicates that deep interface traps strongly influence the collapse characteristic.To further investigate the difference in characteristics of SiN x , SiON and SiO 2 MIS-HEMT, room temperature photoluminescence (PL) spectra were recorded.As shown in the inset of Figure 7, the relative intensities of the yellow band (wavelength at approximately 560 nm) of the three dielectric/AlGaN/GaN samples are quite different.It has been reported that Si and O impurity, which would act as shallow donors, can effectively impact the yellow luminescence (YL) [38,39].The largest YL intensity observed on SiO 2 /AlGaN/GaN sample implies that it has a maximum number of Si and O shallow donors among the three samples.During the deposition of SiON and SiO 2 , the reactive gas N 2 O would cause uncontrollable oxidation of the AlGaN interface and therefore generate several kinds of surface states [40].The SiN x chemical deposition process involves NH 3 plasma treatment, which would be effective to suppress the N-vacancies-related surface defects at the AlGaN surface [41].When the off-state stress is applied to the devices, the shallow donors, oxides, and defects mentioned above would capture electrons and cause the phenomenon of the virtual gate [42].The formation of the virtual gate would increase the depletion region and thus cause the decrease of drain current.The above factors together lead to the different performance on current collapse of the three samples.To further investigate the difference in characteristics of SiNx, SiON and SiO2 MIS-HEMT, room temperature photoluminescence (PL) spectra were recorded.As shown in the inset of Figure 7, the relative intensities of the yellow band (wavelength at approximately 560 nm) of the three dielectric/AlGaN/GaN samples are quite different.It has been reported that Si and O impurity, which would act as shallow donors, can effectively impact the yellow luminescence (YL) [38,39].The largest YL intensity observed on SiO2/AlGaN/GaN sample implies that it has a maximum number of Si and O shallow donors among the three samples.During the deposition of SiON and SiO2, the reactive gas N2O would cause uncontrollable oxidation of the AlGaN interface and therefore generate several kinds of surface states [40].The SiNx chemical deposition process involves NH3 plasma treatment, which would be effective to suppress the N-vacancies-related surface defects at the AlGaN surface [41].When the off-state stress is applied to the devices, the shallow donors, oxides, and defects mentioned above would capture electrons and cause the phenomenon of the virtual gate [42].The formation of the virtual gate would increase the depletion region and thus cause the decrease of drain current.The above factors together lead to the different performance on current collapse of the three samples.

Conclusions
In conclusion, we have fabricated AlGaN/GaN MIS-HEMTs with PECVD-deposited SiNx, SiON, and SiO2 as the gate dielectric and passivation layer.The DC static characteristics, interface traps, and current collapse of MIS-HEMTs with different dielectrics were comprehensively compared.The SiNx sample performs well with regard to suppressing the current collapse but suffers from high leakage current and high shallow trap density.The SiON MIS-HEMT exhibits a low gate leakage current of 3.86 × 10 −5 mA/mm and a high breakdown voltage of 428 V, which indicates it is a great candidate as a gate dielectric and passivation layer.However, its deposition parameters need to be further optimized in order to enhance the reliability and stability.

Conclusions
In conclusion, we have fabricated AlGaN/GaN MIS-HEMTs with PECVD-deposited SiN x , SiON, and SiO 2 as the gate dielectric and passivation layer.The DC static characteristics, interface traps, and current collapse of MIS-HEMTs with different dielectrics were comprehensively compared.The SiN x sample performs well with regard to suppressing the current collapse but suffers from high leakage current and high shallow trap density.The SiON MIS-HEMT exhibits a low gate leakage current of 3.86 × 10 −5 mA/mm and a high breakdown voltage of 428 V, which indicates it is a great candidate as a gate dielectric and passivation layer.However, its deposition parameters need to be further optimized in order to enhance the reliability and stability.

Figure 3 .
Figure 3. Transfer characteristic of (a) SiNx MIS-HEMT, (b) SiON MIS-HEMT, and (c) SiO2 MIS-HEMT, and (d) gate leakage current curve measured at two terminals for the three samples.

Figure 3 .
Figure 3. Transfer characteristic of (a) SiN x MIS-HEMT, (b) SiON MIS-HEMT, and (c) SiO 2 MIS-HEMT, and (d) gate leakage current curve measured at two terminals for the three samples.

Figure 4 .
Figure 4. Forward and backward capacitance versus voltage (C-V) measurement with frequency of 1 MHz.Inset: magnified voltage range of 0~5 V.

Figure 4 .
Figure 4. Forward and backward capacitance versus voltage (C-V) measurement with frequency of 1 MHz.Inset: magnified voltage range of 0~5 V.
are the electron thermal velocity, electron capture cross-section, and electron concentration at the effective density of states in the conduction band in GaN.∆E = EC − ET is the energy gap between the conduction band and interface trap.k is the Boltzman constant and T is the temperature.

Figure 5 .
Figure 5. Pulse mode Id-Vgs curves with pulse width variations of 100 μs, 1 ms, 10 ms, 100 ms, and 200 ms.The pulse period is 500 ms.The Vds was kept at 1 VThe backward Vgs base is 5 V. (a) SiNx MIS-HEMT with forward Vgs base of −20 V (b) SiON MIS-HEMT with forward Vgs base of −14 V. Inset: pulse Vgs condition with forward sweep and backward sweep (c) SiO2 MIS-HEMT with forward Vgs base of −14 V (d) Interface trap charge density Qit at ∆E > x(eV) of three samples.

Figure 5 .
Figure 5. Pulse mode Id-V gs curves with pulse width variations of 100 µs, 1 ms, 10 ms, 100 ms, and 200 ms.The pulse period is 500 ms.The Vds was kept at 1 VThe backward V gs base is 5 V. (a) SiN x MIS-HEMT with forward V gs base of −20 V (b) SiON MIS-HEMT with forward V gs base of −14 V. Inset: pulse V gs condition with forward sweep and backward sweep (c) SiO 2 MIS-HEMT with forward V gs base of −14 V (d) Interface trap charge density Q it at ∆E > x(eV) of three samples.

Electronics 2018, 7 ,
x FOR PEER REVIEW 7 of 11 that most of its interface traps are deep traps.In conclusion, SiNx MIS-HEMT has the largest density of shallow interface traps and the lowest density of deep traps among the three samples.SiO2 MIS-HEMT has the lowest density of shallow traps and largest density of deep traps.The performance of SiON MIS-HEMT is between the SiNx and SiO2 sample.These results explain the difference in hysteresis in the 1st slope of the C-V curve.The larger deep trap densities of SiON and SiO2 MIS-HEMT are responsible for the hysteresis in the 1st slope of the C-V curve.In addition, these calculated results show that shallow energy levels are more likely to be occupied by traps in the SiNx/AlGaN interface than in the SiON/AlGaN interface and SiO2/AlGaN interface.This offers chances for electron hopping, which could partially explain why SiNx MIS-HEMT has the highest gate leakage current and the lowest Ion/Ioff ratio among the three samples.

Figure 7 .
Figure 7. Photoluminescence (PL) spectra at room temperature of three samples.

Figure 7 .
Figure 7. Photoluminescence (PL) spectra at room temperature of three samples.

Author
Contributions: Conceptualization, K.G. and D.C.; Formal analysis, K.G. and D.C.; Investigation, Q.Z.; Methodology, K.G. and Q.Z.; Supervision, H.W.; Writing original draft, K.G. and D.C.; D.C. designed the experiment, prepared the samples and performed the measurements.K.G. contributed to the conception of the study and designed the experiment.Q.Z.contributed to the data analysis and wrote the manuscript.H.W. supervised the study and reviewed the manuscript.

Table 1 .
Deposition properties of SiN x , SiON, and SiO 2.

I dmax (mA/mm) g m max (mS/mm) V th Gate Leakage 1 (mA/mm) Off-State Breakdown Voltage (V) %I 2 Dynamic Ron/Static Ron 3 SiN x
−20 V;2Reduction of drain current and increase of Ron due to current collapse at off-state V gs = −18 V, Vdstress = 50 V for 10 s; 3 Dynamic Ron at off-state Vds stress = 50 V and static Ron without stress.
1Gate leakage current density at two-terminal reverse voltage =