Optimized Digital Controllers for Switching-Mode DC-DC Step-Down Converter

In this paper, a nonlinear least squares optimization method is employed to optimize the performance of pole-zero-cancellation (PZC)-based digital controllers applied to a switching converter. An extensively used step-down converter operating at 1000 kHz is considered as a plant. In the PZC technique, the adverse effect of the (unwanted) poles of the buck converter power stage is diminished by the complex or real zeros of the compensator. Various combinations of the placement of the compensator zeros and poles can be considered. The compensator zeros and poles are nominally/roughly placed while attempting to cancel the converter poles. Although PZC techniques exhibit satisfactory performance to some extent, there is still room for improvement of the controller performance by readjusting its poles and zeros. The (nominal) digital controller coefficients thus obtained through PZC techniques are retuned intelligently through a nonlinear least squares (NLS) method using the Levenberg-Marquardt (LM) algorithm to ameliorate the static and dynamic performance while minimizing the sum of squares of the error in a quicker way. Effects of nonlinear components such as delay, ADC/DAC quantization error, and so forth contained in the digital control loop on performance and loop stability are also investigated. In order to validate the effectiveness of the optimized PZC techniques and show their supremacy over the traditional PZC techniques and the ones optimized by genetic algorithms (GAs), simulation results based on a MATLAB/Simulink environment are provided. For experimental validation, rapid hardware-in-the-loop (HiL) implementation of the compensated buck converter system is also performed.


Introduction
Modern-day digital devices such as cellular phones, camcorders, calculators, digital cameras, portable electronic devices, microprocessors, DSP core, handheld computers and PDAs, MP3 personal players, and so on utilize switch-mode power supplies (SMPSs).The devices need to have regulated output voltages irrespective of the perturbation in the input voltage or load current.For this purpose, traditionally, analog controllers have been applied to SMPSs to ensure regulated voltages for the digital devices.Analog controllers, however, show limitations in the form of poor design portability, large size, low reliability, and low flexibility.Digital controllers, on the other hand, offer advantages in the form of high flexibility and programmability, competency to implement complex control strategies, no need to alter hardware upon changing algorithms, high performance/cost ratio, and excellent dynamic performance, among others [1].Consequently, SMPS designers are more interested in developing efficient and optimized digital controllers as compared to the predominately used analog controllers.In this paper, well-recognized PZC techniques-based optimized digital controllers are designed for buck converters to display much-improved performance.One of the optimization techniques, named the nonlinear least squares technique, is employed to optimize the performance of PZC-based digital controllers.
As far as the literature review is concerned, in [2], a pole-zero-cancellation technique-based digital controller for a buck converter was suggested by Abe et al. to improve the performance characteristics.The effect of the resonance peak and ESR-zero is nullified by completely cancelling the poles and the zero of the buck converter with the help of the complex zeros and the pole of the compensator, respectively.An additional pole representing a simple low-pass filter is introduced to gain control of the characteristics of the composite buck converter system.A two-pole two-zero analog controller is mapped into the digital controller using bilinear transformation.In [3], the same authors (Abe et al.) applied successfully the two-pole two-zero analog compensator to the buck and boost converters to ensure superior performance, yet without cancelling the RHP-zero in the case of the boost converter.The effect of change in the capacitance of the output capacitor in a PZC-based digitally controlled buck converter on the stability margin, and thus the performance, was investigated in [4].Reference [5] also suggested the application of a three-pole two-zero (analog) compensator with complex as well as real zeros to a switching converter exhibiting nonminimum phase characteristics.Such a converter possesses RHP-zero in its transfer function, which limits the bandwidth, thus causing the response to be slow and sluggish.Reference [6] suggested a slightly different approach for designing a PZC-based digital controller for the step-down converter.Rather than using the real or complex zeros by the compensator close to the resonant frequency of the converter's power stage, the compensator zeros are selected on the basis of the quality factor and output impedance of the plant.The effect of the quality factor on compensator design is also investigated efficiently.In [7], the task of providing feedback compensation to the relatively complicated switching converters (as they involve RHP-zero), namely boost and flyback working in continuous conduction mode, was efficiently performed through various combinations of PZC-based controllers.The PZC-based digital controllers mentioned in the aforementioned references show somewhat satisfactory performance.Their performance may even be improved by retuning their coefficients through some optimization techniques.
Many researchers successfully applied advanced numerically based or metaheuristic optimization techniques to tune the compensator parameters to ameliorate performance.Reference [8] suggested the tuning of the parameters of the digital controller designed on the basis of a Chebyshev polynomial approach for the fifth-order boost converter through a genetic algorithm (GA).The problem with the GA is that it has to employ its three operators, namely selection, crossover, and mutation, at each iteration, thus resulting in slower responses.In addition, it shows enhanced sensitivity to the initial population and does not use gradients.In [9], although metaheuristic techniques such as particle swarm optimization (PSO) and the gravitational search algorithm (GSA) were successfully employed for the fine-tuning of parameters of Type II and Type III compensators applied to a step-up converter, but they may converge prematurely.Mercader et al. in [10] tried to overcome the problem of convergence to the local minimum of convex optimization and proposed a convex-concave procedure (CCP) for the fine-tuning of PID controller coefficients that controlled the loop shape efficiently to ensure better dynamic performance.On the other hand, the NLS method capitalizes on the structure of the Hessian, which can be attained through the computation of Jacobian (first-order derivatives only) and minimizes the errors (residuals) quickly, and thus ensures better set-point tracking.
In addition, many instances in the literature have been reported where the nonlinear least squares (NLS) method has been successfully employed to optimize the performance of various types of compensators used for various applications.In [11], optimization of the discrete root locus-based discrete-time controller applied to a buck converter was accomplished through the NLS method.In [12], tuning of the PID-based track-keeping controllers of a remotely controlled autonomous in-scale fast-ferry model was carried out through the NLS method and a genetic algorithm (GA), where the former showed superiority over the latter one while doing sea trials.Reference [13] suggested the use of the NLS method for the optimization of offline pulse patterns for arbitrary modulation indices and arbitrary numbers of modules per branch, while minimizing the harmonic content of the load current (specifically measured in the total demand distortion (TDD)), instead of using selective harmonic elimination, in the case of the indirect modular multilevel converter (MMC).In [14], a Levenberg-Marquardt (LM) and quasi-Newton (QN)-based NLS hybrid method was used efficiently to improve the performance of the designed linear-phase quadrature mirror filter (QFM) bank in the form of mean squares error in passband and stopband regions, as well as peak reconstruction error (PRE) and error in the transition band at quadrature frequency.This was accomplished by optimizing the quadratic measure of the ideal characteristics of the prototype filter and filter bank at quadrature frequency.In [15], a predictive current controller with an extended-state observer (ESO), suggested for the grid integration of wind energy systems, utilized the NLS method to minimize a cost function, defined as a sum of the squared values of d-axis and q-axis current errors, while computing the optimal converter switching time.In [16], calibration of the roadside camera employed in traffic surveillance systems was accomplished on the basis of the least squares optimization method, which involved camera-intrinsic parameters and rotation angles.In [17], for anticipating the epileptic seizure via EEG signals in epileptic individuals suffering from unexpected and momentary electrical deterioration in the brain, fitting of the EEG signals filtered through singular spectrum analysis into the exponential curve was carried out using the NLS method.Statistical examination of the features extracted from exponential curves assists in diagnosis.In [18], nonlinear rational systems were identified using an NLS-based, globally consistent two-step estimator.In [19], a high face recognition rate was achieved by performing NLS computations, while taking into account the 'holistic' and 'detailed' features of the face.
Although enormous numbers of examples of the application of the NLS method to control plants of various types are found in the literature, to the best knowledge of the authors, very limited instances are found in the literature where pole-zero-cancellation-based digital controllers have been optimized through the NLS method.In this paper, PZC-based optimized digital controllers are, thus, suggested for the buck converter to achieve much-improved performance.
The paper is formulated in the following way.Section 2 describes the dynamics of the buck converter, which is considered to be the plant in the paper.Three types of pole-zero-cancellation (with complex and real zeros)-based digital controllers are designed in Section 3. The digital controller design techniques are essentially of the types digital redesign or emulation.The NLS method involving the LM algorithm to optimize the digital controllers is detailed in Section 4. Nonlinearities involved in the digital control loop are modelled in Section 5. Section 6 involves the redesigning and reoptimizing of the digital controllers when the nonlinear effects in the digital control loop are considered.Section 7 is dedicated to additional simulation results.HiL implementation is described in Section 8. Concluding remarks are given in Section 9.

Buck Converter Modelling
For the sake of reducing higher unregulated DC input voltage, V in , to lower regulated DC output voltage, V out , a realistic buck converter circuit (see Figure 1) is used, as it takes into consideration the parasitic resistances, i.e., capacitor equivalent series resistance (ESR) and inductor direct current resistance (DCR), denoted explicitly by r C and r L , respectively.Owing to capacitor ESR, a zero is introduced into the buck converter transfer function [20].The component values to be considered for the converter throughout the paper are the following: V in = 3.6 V, V out = 2.0 V, L = 4.7 µH, C = 4.7 µF, r L = 505 mΩ, r C = 5 mΩ, f s = 1000 kHz, and T s = 1/f s = 1 µs.The block diagram of the closed-loop (digital) control system containing the buck converter power stage, ADC and DAC converters, and the digital controller is shown in Figure 1.
The buck converter's dynamics (transfer function) imperative for the controller design can be derived through its small-signal AC-equivalent circuit model (see Figure 2), where the nonlinear power switches Q1 and Q2 are replaced by their equivalent linear small-signal models [21].By applying the averaging and linearization technique adopted in [22] to the small-signal model, the small-signal transfer functions, such as duty cycle-to-output voltage ( ) vd G s , input voltage-to-output voltage ( ) vg G s , and load current-to-output voltage (loaded power converter output impedance ( ) o Z s ), can be computed and are described by Equations ( 1)-(3), respectively [22,23].
where The buck converter's dynamics (transfer function) imperative for the controller design can be derived through its small-signal AC-equivalent circuit model (see Figure 2), where the nonlinear power switches Q 1 and Q 2 are replaced by their equivalent linear small-signal models [21].By applying the averaging and linearization technique adopted in [22] to the small-signal model, the small-signal transfer functions, such as duty cycle-to-output voltage G vd (s), input voltage-to-output voltage G vg (s), and load current-to-output voltage (loaded power converter output impedance Z o (s)), can be computed and are described by Equations ( 1)-(3), respectively [22,23]. where ) and and Here ω 0 , ω ZERO , and Q represent the filter resonance frequency, capacitor zero frequency, and the quality factor of the filter, respectively.
AC small-signal equivalent circuit for the buck converter power stage.
Among the transfer functions, the one described in Equation (1), i.e., duty cycle-to-output voltage, is controlled through the controller for output voltage regulation.To achieve the closed-loop characteristics, and thus required performance, a controller is applied to it as it behaves as a plant.The ( ) vd G s contains a complex conjugate pair whose effect can be nullified by the complex or real zeros of the compensator.
In order to design the digital controller, the continuous-time converter transfer function ( ) vd G s is discretized using zero-order-hold (ZOH) with a sampling period s T , as follows: For the component values mentioned above, the transfer function in the analog and digital form of the buck converter with a short description is presented in Table 1.Discretized form obtained using ZOH with Ts = 1 µs

PZC-Based Digital Controllers
The buck converter power stage contains two complex conjugate poles occurring at the LC filter's resonant frequency, which results in phase reduction, thus making the system unstable.In order to meet the required specifications, such as bandwidth, steady-state accuracy (ensured through static-error constant/DC gain of the system), robust relative stability, reduced sensitivity to parameter changes, superior transient response, and so on, appropriate gain and phase margins at a specific 0- Here ω 0 , ω ZERO , and Q represent the filter resonance frequency, capacitor zero frequency, and the quality factor of the filter, respectively.
Among the transfer functions, the one described in Equation (1), i.e., duty cycle-to-output voltage, is controlled through the controller for output voltage regulation.To achieve the closed-loop characteristics, and thus required performance, a controller is applied to it as it behaves as a plant.The G vd (s) contains a complex conjugate pair whose effect can be nullified by the complex or real zeros of the compensator.
In order to design the digital controller, the continuous-time converter transfer function G vd (s) is discretized using zero-order-hold (ZOH) with a sampling period T s , as follows: For the component values mentioned above, the transfer function in the analog and digital form of the buck converter with a short description is presented in Table 1.Discretized form obtained using ZOH with T s = 1 µs

PZC-Based Digital Controllers
The buck converter power stage contains two complex conjugate poles occurring at the LC filter's resonant frequency, which results in phase reduction, thus making the system unstable.In order to meet the required specifications, such as bandwidth, steady-state accuracy (ensured through static-error constant/DC gain of the system), robust relative stability, reduced sensitivity to parameter changes, superior transient response, and so on, appropriate gain and phase margins at a specific 0-dB crossover frequency and loop gain should be ensured.This can be accomplished by placing the compensation zeros, real or complex, near the LC filter's resonant frequency.Such a pole-zero-cancellation (PZC) technique in analog form is employed in the paper for designing the digital controllers (emulation technique), which are then optimized using the NLS method.Three types of PZC techniques, designed for a 100 kHz, 0-dB crossover frequency (10 times below the switching frequency, to satisfy the Nyquist criterion), unless otherwise stated, distinguished on the basis of placement of compensator's zeros and poles, are designed to ensure better static and transient responses.All the cases involve the same method of computing the compensator gain.For the design of PZC techniques, the same procedure is adopted, which is outlined in the flow chart shown in Figure 3. compensation zeros, real or complex, near the LC filter's resonant frequency.Such a pole-zerocancellation (PZC) technique in analog form is employed in the paper for designing the digital controllers (emulation technique), which are then optimized using the NLS method.Three types of PZC techniques, designed for a 100 kHz, 0-dB crossover frequency (10 times below the switching frequency, to satisfy the Nyquist criterion), unless otherwise stated, distinguished on the basis of placement of compensator's zeros and poles, are designed to ensure better static and transient responses.All the cases involve the same method of computing the compensator gain.For the design of PZC techniques, the same procedure is adopted, which is outlined in the flow chart shown in Figure 3.

Using Complex Zeros
In this type of PZC technique, the effect of a pair of complex poles of the converter is nullified by placing the two complex zeros of the compensator at the LC resonant frequency (ω 0 ).This actually adds to the phase to boost the phase margin.One of the compensator poles is placed at the ESR zero (ω ZERO ) to keep the gain of the open-loop transfer function at a slope of −1.For the rejection of high-frequency noises, the second high-frequency pole is moved from approximately 0.2 to 0.7 of the switching frequency.This additionally incorporated high-frequency pole not only makes the compensator less sensitive to high-frequency noise phenomena, but also assists in smoothing the quantization error in the compensator output.To achieve zero steady-state error, an integrator (a pole at origin) is also introduced.
With the mentioned placement of the compensator poles and zeros, the compensator transfer function takes the form where parameter k, ranging from 0.2 to 0.7, controls the location of the high-frequency pole; ω z = ω 0 designates the compensator complex zero frequencies, numerically equivalent to the plant poles' resonance frequencies; the dimensionless Q-factor, Q C , of the compensator is selected close to the power stage, Q; and the DC gain, K c , of the compensator is adjusted to meet the required 0-dB crossover frequency (100 kHz) denoted by ω x .Then, Assuming the condition that the compensated system's gain plot crosses 0-dB at a −1 slope, i.e., G p (s) With the placement of poles and zeros and calculation of the DC gain, the analog controller transfer function is given, numerically, by: The continuous-time compensator can be mapped into its discrete-time counterpart using one of the transformation techniques, such as 'Tustin' (in our case), expressed mathematically by s = 1+z −1 , with the sampling time equivalent T s = 1 µs.The corresponding discrete-time compensator is given by: G c (z) = 6.753z 3 −5.595z 2 −6.47z+5.877 With the help of an inverse z-transform, the compensator discrete-time transfer function can be translated into the difference equation given by where and u[n − 3] represent the present, one sample period, two sample period, and three sample period delayed values of the duty ratio, respectively.

Using Real Zeros
A compensator with three poles and two real zeros can also be realized and is expressed by Usually, the real zeros ω z1 and ω z2 are placed close to the resonant frequency, ω 0 .Their positions can be controlled using the relationships: ω z1 = m 1 ω 0 and ω z2 = m 2 ω 0 , where the coefficients m 1 and m 2 describe the deviation of the zeros from ω 0 .Here, in our case, it is observed that placement of one of the zeros at ω 0 , i.e., m 1 = 1, and the other slightly below ω 0 , i.e., m 2 = 0.8, ensures the increase in phase margin, thus the better performance.The compensator's three poles are placed in the same way as described in the complex zeros case.
With such an arrangement of poles and real zeros, the analog controller, numerically, takes the form The digital controller obtained from the analog controller using the bilinear mapping technique is then described by When comparing the analog compensators with real and complex zeros and the digital compensators, the following corollaries can be deduced.

•
It is revealed from the inspection of the Bode plots (see Figure 4) of the open-loop compensated buck converter system that the compensator using the complex zeros at the resonance frequency achieves a phase margin of 84.3 • , as compared to the one with real zeros, which attains a phase margin of 64.6 • .Both the compensators are designed for 100-kHz bandwidth (0-dB crossover frequency).This suggests that complex-zero compensation offers larger stability margins and reduced amplitude of the resonance peak, in comparison to that of the real-zero compensation.Consequently, complex-zero compensation displays excellent static properties.

•
Unlike the excellent static properties, complex-zero compensation shows poor dynamic properties.
In order to check the dynamicity, the load is changed from 4.5 Ω to 9 Ω and then from 9 Ω to 4.5 Ω.Although the output voltage settles to its steady-state value of 2 V for both compensators, the compensator with complex zeros shows more recovery time and spike voltage peak at the load transient as compared to that of the one with real zeros.This is due to the fact that a change in load displaces the converter poles from their original positions.Thus, the predetermined compensator zeros are not able to perfectly annul the effects of the converter's complex poles.If the compensator zeros are made adaptive according to the perturbation in the load current, then the complete cancellation effect can be ensured.MATLAB/Simulink-based simulation results shown in Figure 5 highlight this fact.
Transformation of the continuous-time controller into the discrete-time controller results in frequency distortions.Consequently, the discrete-time controller shows a slightly deviated behavior from its analog counterpart at frequencies close to the Nyquist frequency.The Bode plot of the analog and digital compensators (see Figure 6) pinpoints the phenomenon of frequency distortions.load current, then the complete cancellation effect can be ensured.MATLAB/Simulink-based simulation results shown in Figure 5 highlight this fact.
Transformation of the continuous-time controller into the discrete-time controller results in frequency distortions.Consequently, the discrete-time controller shows a slightly deviated behavior from its analog counterpart at frequencies close to the Nyquist frequency.The Bode plot of the analog and digital compensators (see Figure 6) pinpoints the phenomenon of frequency distortions.simulation results shown in Figure 5 highlight this fact.
Transformation of the continuous-time controller into the discrete-time controller results in frequency distortions.Consequently, the discrete-time controller shows a slightly deviated behavior from its analog counterpart at frequencies close to the Nyquist frequency.The Bode plot of the analog and digital compensators (see Figure 6) pinpoints the phenomenon of frequency distortions.Reasonable compensation can also be achieved using two poles (with two complex zeros), rather

3.2.
A Two-Pole (with One Pole at the Origin) Two-Zero Compensator-Case 2

Using Complex Zeros
Reasonable compensation can also be achieved using two poles (with two complex zeros), rather than using three poles.The poles and the (complex) zeros are placed in the same way as described in case 1.For example, in a two-pole two-zero compensator, a pair of matching complex zeros is placed exactly at the resonance frequency to nullify the effects of a pair of complex conjugate poles introduced by the converter power stage.In order to avoid undesirable ripples in the output voltage introduced by the output capacitor ESR, one of the compensator poles is placed at the ESR zero frequency to compensate for the capacitor ESR zero.For the sake of ensuring high low-frequency gain to achieve low static error and good input rejection, a pole (an integrator) is placed at the origin.Such a two-pole two-zero compensator, in transfer function form, is described by [24] as follows: With K c computed from the condition G p (s) s=s x • G c (s)| s=s x = 1, the compensator's transfer function in the s-domain, numerically, takes the form as follows: The analog controller is mapped into the digital one with the help of the Tustin mapping technique using a sampling time of 1 µs, as follows:

Using Real Zeros
With the real zeros replacing the complex zeros, the transfer function of a two-pole two-zero compensator is then described by Regarding the placement of the zeros, one of the real zeros is placed at ω 0 , i.e., m 1 = 1, and the other slightly below ω 0 , i.e., m 2 = 0.8.This combination ensures the increase in phase margin, thus better response characteristics.With the placement of compensator poles and zeros and the adjustment of gain K c to achieve the desired crossover frequency, the analog controller reduces to Using the bilinear transformation with 1 µs, the discrete controller, equivalently, is expressed by Electronics 2018, 7, 412 11 of 25

Using Complex Zeros
Another type of a two-pole two-zero compensator can be achieved by placing a pole at the origin with a low-frequency pole.In such a compensator, the buck converter transfer function is completely cancelled with the complex zeros (occurring at resonance frequency) and a pole (placed at the ESR zero frequency) of the compensator.Thus, the phase shift introduced by an LC filter complex double pole and output capacitor ESR zero is annulled by making the converter characteristics ineffective.Through the remaining part of the compensator (gain and a low-frequency pole), which is essentially a low-pass filter, the composite system's response is thus controlled.Mathematically, the transfer function of the compensator is given by With the low-frequency pole placed far below (approximately 10 3 times) f s , the compensator is described, numerically, by G c (s) = 6.825 × 10 −10 s 2 + 9.567 × 10 −5 s + 30.9 3.74 × 10 −12 s 2 + 1.592 × 10 −4 s + 1 Using the Tustin mapping technique, the analog controller is mapped in to the digital controller as follows: For the controllers designed for the 100-kHz crossover frequency, the analog control system offers a phase margin of about 90.6 • , whereas the digital control system provides a phase margin of 72.7 • (see Figure 7).Frequency distortion due to the mapping from the s-plane to z-plane deteriorates the performance of the digital controller.This requires the retuning of the coefficients of the digital controller.

Using Real Zeros
A two-pole two-zero compensator with one of the poles lying at low frequency and real zeros lying in the vicinity of the resonance frequency is characterized by the transfer function as follows:

Using Real Zeros
A two-pole two-zero compensator with one of the poles lying at low frequency and real zeros lying in the vicinity of the resonance frequency is characterized by the transfer function as follows: Numerically, the analog controller is given by The equivalent discrete-time controller using the bilinear transformation is expressed by

NLS Method-Based Optimized Digital Controllers
In the context of optimization, the nonlinear least squares (NLS) method bears a tempting structure that can be exploited with great effectiveness in algorithm design.Regarding the compensated buck converter system, minimization of the voltage error signal essentially constitutes the NLS problem.Specifically, the NLS technique can be employed to retune the discrete-time controller coefficients for fast setpoint tracking.This is accomplished by adjusting the controller coefficients to speedily reduce the error e(t) = V out − V ref at all steps of the simulation time.As the minimization of the sum of squares of the error functions is carried out by the algorithm at each step, this constitutes the multiobjective optimization problem.
In the paper, for calculating the sum of error squares, among the different large-scale algorithms [25], such as the trust-region-reflective (TRR), variable projection (VP), and Levenberg-Marquardt (LM) algorithms, LM is employed.Linear algebra is exploited in large-scale algorithms which do not require or store full matrices for its operation.It is a well-established fact that the LM algorithm performs better when bound constraints are not considered in the problem.
The algorithm starts with the initial design vector, x 0 , indicating the initial design variables in the form of coefficients of the digital controller computed through the pole-zero-cancellation techniques.For the considered cases, no restriction has been imposed on the lower and upper bounds of the design variables.
Mathematically speaking, the NLS method using the LM algorithm involves minimizing the sum of squares of the error signal, i.e., subject to the constraints: where x = (x 1 , x 2 , . . ., x n ) ⊂ n , l ⊂ ( ∪ (−∞)) n , and u ⊂ ( ∪ (∞)) n .Here, A and A eq , and C and C eq are the matrices of doubles for linear inequalities and equalities, and nonlinear inequalities and equalities, respectively.Similarly, b and b eq are the vectors of doubles for linear inequalities and equalities, respectively, and l and u represent the lower and upper bounds, respectively, on each x component.In our case, since no restriction is imposed on the bounds of design variables for the unconstrained multiobjective optimization problem, all matrices and vectors are empty sets.
Here, the function to be minimized, f (x) = e(x) 2 2 , representing the l2-norm of error, is assumed to be continuously differentiable at point x 0 .It is assumed that m ≥ n.As remarked, the vector x represents the number of design/decision variables, which are specifically the coefficients of the digital controllers.
In the compensated control systems, in order to achieve the targeted trajectories realistically, the residual e(x) , being a function from n to m , described in Equation ( 31) is made small optimally and converged speedily.Rapidly converged minimum residuals result in better set-point tracking.A unique solution is guaranteed due to the convex nature of the minimizer.
In order to get deep mathematical insight, the algorithm forces the output v o (x, t) to track the continuous required trajectory v re f (t) for the decision vector x and scaler t.That is to say, min Discretization of the integral through an appropriate quadrature formula reduces Equation (32) to the least squares problem: A m-by-n-sized Jacobian matrix J(x) of the residual e(x) of n variables is computed by On the basis of J(x), the specially structured gradient vector G(x) and Hessian matrix H(x) of the NLS method are calculated by Equations ( 35) and (36), respectively. where The matrix Q(x) comes with the property that it tends to approach zero as the residual e(x) approaches zero on the occasion the decision variables x k , finally settling to optimal values.In other words, the matrix Q(x) gives an indication of how fast the minimization of the error is accomplished.
By amalgamating the salient characteristics of the Gauss-Newton (GN) and steepest descent (SD) algorithms, the LM method computes the search direction on the basis of a solution of the linear set of equations [26], i.e., More precisely, the LM method modifies the GN search direction by altering J(x k ) T J(x k ) with J(x k ) T J(x k ) + λ k I.By replacing the identity matrix with the diagonal of the Hessian, Equation (38) can be expressed alternatively as Or, equivalently, in terms of the least squares problem, Equation (39) takes the form min The magnitude and direction of d k is controlled through the scalar λ k , whose initial value λ 0 is set empirically, perhaps, as 100.The LM method therefore uses a search direction that falls within the directions calculated by the GN and SD methods.The LM algorithm, thus, essentially is an aggregation of the SD and GN algorithms.For example, when λ k is zero, the direction d k refers to the direction of the GN method, whereas when λ k tends to infinity, d k assumes the direction of SD, with its magnitude tending to zero.This comes with the observation that the term e(x k + d k ) < e(x k ) holds true for some adequately large values of λ k .Through the control of the term λ k , descent can be ensured even when second-order terms, which limit the GN method's efficiency, are experienced.The algorithm adjusts the value of λ k during each of the step as follows: when the move passes λ k × 10, when the move fails (41) In a nutshell, the LM algorithm works in the following way: • It starts with an initial guess x 0 and iterates for k = 1, 2, . . ., n.

•
The Lagrange multiplier λ k is then selected for each step k.

•
For the next iteration, k + 1, d k+1 = d k + ∆d k is calculated.

•
At the end, the solution is checked for convergence.
Although several stopping criteria, such as absolute function criterion, sequence convergence criterion, maximum iteration count criterion, and so on, can be adopted, here, the algorithm stops when the final change in the sum of squares relative to its initial value is less than the default value of the function tolerance.One must remember that although the algorithm ensures optimal performance, convergence to the global minimum of the objective function cannot be guaranteed.To realize the LM algorithm based on the NLS method, a MATLAB/Simulink environment is used.Termination tolerance for both the objective function and the parameter estimation is appropriately selected.
When the NLS method is applied to retune the coefficients of the digital controllers, tremendous improvement in performance is observed.All the controllers, traditional and optimized, in transfer function form, are summarized in Table 2. Correspondingly, step response characteristics displayed by all the controllers, traditional and optimized, are shown in Figure 8.The performance parameters in the form of maximum overshoot, settling time, and rise time, computed from the step response characteristics, are summarized and compared in Table 3. From Table 3, it is inferred that the optimized digital controllers offer much-improved performance as compared to their traditional counterparts.This validates the applicability and workability of the NLS method.Like the step response characteristics, the optimized controllers also offer superior transient behavior.A three-pole two-zero (complex)-based optimized digital controller offers reduced recovery time and peak-to-peak spike voltage at the time of load transient as compared to its traditional form (see Figure 9).In the same way, other optimized controllers also show fast transient response with regard to their unoptimized counterparts.
(a) (    The optimized controller not only offers excellent set-point tracking and load regulation characteristics, but also exhibits improved disturbance rejection abilities against the disturbance (due to variations in the converter power-stage parameters because of aging or model uncertainties) injected at the converter input (see Figure 10).
To gain more insight into the performance in terms of frequency-domain characteristics, the Bode plot of the unoptimized and optimized G p (z).G c (z) of case 1 shown in Figure 11 clearly depicts that the optimized digital controller assists in ensuring more phase margin (and thus system stability) for all the frequencies, as compared to the unoptimized digital controller.In order to validate the superiority of the proposed NLS method over the other optimization techniques, such as a genetic algorithm (GA), a comparison of the voltage response of the two-pole two-zero (complex)-based optimized digital controllers obtained through NLS and GA is presented in Figure 12.For the typical design example, the NLS method completely outshines GA performance-wise (overshoots, steady-state error, etc.).The GA parameters considered are the following: objective function = Integral Time Absolute Error (ITAE), population size = 200, generations = 25, crossover fraction = 0.65, and function tolerance = 1 × 10 −6 .

Digital Control Loop Elements Modelling
A digital control loop involves mixed signals.A continuous-time error signal digitized through the ADC is processed by the digital controller.The discrete-time controller output signal is then converted into the analog one through the DAC/DPWM to apply on-off pulses to the switching circuit.For the more realistic digitally compensated buck converter system, inherently existing nonlinearities occurring in the digital control loop should be modelled and considered.

Loop Delay
The digital control loop suffers from the delay introduced by various elements in the loop.The delay due to the ADC conversion time ADC t , the digital controller processing time P t , the DAC conversion time DAC t , the gate-driver propagation delay GD t , and so forth constitutes the total loop delay d t , which adversely limits the loop bandwidth, thus resulting in deteriorated performance.
However, the effect becomes less prominent if the loop delay remains within the one sampling period

Digital Control Loop Elements Modelling
A digital control loop involves mixed signals.A continuous-time error signal digitized through the ADC is processed by the digital controller.The discrete-time controller output signal is then converted into the analog one through the DAC/DPWM to apply on-off pulses to the switching circuit.For the more realistic digitally compensated buck converter system, inherently existing nonlinearities occurring in the digital control loop should be modelled and considered.

Loop Delay
The digital control loop suffers from the delay introduced by various elements in the loop.The delay due to the ADC conversion time t ADC , the digital controller processing time t P , the DAC conversion time t DAC , the gate-driver propagation delay t GD , and so forth constitutes the total loop delay t d , which adversely limits the loop bandwidth, thus resulting in deteriorated performance.However, the effect becomes less prominent if the loop delay remains within the one sampling period T s .With the availability of high-speed ADCs, DACs, processors, and FPGAs, the total loop delay can be reduced.A delay of half the period, i.e., t d = 0.5 µs, is considered in the design examples.The delay can be modelled mathematically by e −st d ≈ 1 + (1 + st d ), where the first-order lag approximation has been used to make the calculations simpler.

ADC and DAC Resolutions
In order to avoid unwanted oscillations, called limit cycle oscillations (LCOs), and thus to ensure steady-state behavior, ADC and DAC resolutions should be selected with care.Regarding the ADC resolution, LCOs can be avoided if the output error voltage is restricted within the allowed output voltage variation ∆V out .Alternatively, the ADC quantization step calculated by q v,ADC = V max /2 n ADC should be lesser in value than ∆V out , i.e., 1 Manipulation of Equation (42) gives the formula for ADC resolution n ADC as follows [27]: where V max , V out , and V re f represent the maximum output, output, and reference voltages, respectively; H signifies the scaling factor for the sensed output voltage and is set to one for concerned design examples; the function int [] refers to the upper rounded integer value of the argument.Without going into the mathematical detail, it has been observed experimentally that the DPWM resolution, n DPW M , should be finer than that of the ADC, n ADC .Mathematically, In Equation (44), addition of the term log 2 V re f /V max • D to n ADC indicates that n DPW M should at least be set one bit larger than n ADC in the steady state.This corresponds two DPWM levels to one ADC level.
Numerically, assuming the maximum ripples do not exceed 1% of the output voltage (the design specification considered for the design example) and V re f to be 80% of V max , the minimum resolution required by the ADC is 7 bits.The quantization step q v,ADC for the error signal ranging from −1 to +1 (ADC's dynamic range), thus, is calculated to be 2/2 7 = 0.0156.The n DPW M is, then, 8 bits.ADC and DPWM gains, being dependent on their resolutions, computed through K ADC = 2 n ADC and K DPW M = 1/(2 n DPW M − 1) respectively, are calculated to be 128 and 1/255, respectively.

Redesigning and Optimizing the Digital Controller
In order to compensate all the additionally incorporated effects in the digital control loop due to the inclusion of delay and ADC and DAC gains, the digital controller has to be resigned.More specifically, the controller has to be redesigned for the modified plant described by Following the same procedure as described above, a three-pole two-zero (complex)-based digital controller (instead of using all the controllers for saving space) for the modified plant G p (s) is given by G c (z) = Once the algorithm is run, as can be seen from Figure 13, with the progression of iterations, the residual decreases monotonically, thus ensuring the better set-point tracking.This certifies the fine-tuning of the digital controller coefficients by the NLS method.The algorithm stops when the final change in the sum of squares relative to its initial value is less than the default value of the function tolerance.Once the algorithm is run, as can be seen from Figure 13, with the progression of iterations, the residual decreases monotonically, thus ensuring the better set-point tracking.This certifies the finetuning of the digital controller coefficients by the NLS method.The algorithm stops when the final change in the sum of squares relative to its initial value is less than the default value of the function tolerance.

Additional Numerical Simulations
For the sake of investigating the effectiveness of the proposed optimized digital controllers, some additional simulation results for the digital control loop incorporating the delay and ADC and DAC gains using the MATLAB/Simulink environment are presented.A solver of the fixed-step type is used.The loop delay is considered to be half the switching period.ADC and DPWM gains are set to 128 and 0.0039, respectively.The step response offered by the three-pole two-zero (complex)-based unoptimized and optimized digital controllers described in Equations ( 46) and (47), respectively, for the modified plant described in Equation ( 45) is shown in Figure 14.
From the step response offered by the controllers, it is depicted that the optimized controller offers better static performance characteristics as compared to its unoptimized form (see Table 4).
In addition, at the time of transient, the response takes much less time to recover to its steadystate value with a controlled peak spike.For example, for a load current change of 0.44 A to 0.22 A and then from 0.22 A to 0.44 A, the optimized controller shows less recovery time as well as reduced voltage peak-to-peak spike with regard to its traditional form (see Figure 15).Simulation results reveal that the digital controllers are well-retuned by the NLS method and offer superior static and dynamic performance.

Additional Numerical Simulations
For the sake of investigating the effectiveness of the proposed optimized digital controllers, some additional simulation results for the digital control loop incorporating the delay and ADC and DAC gains using the MATLAB/Simulink environment are presented.A solver of the fixed-step type is used.The loop delay is considered to be half the switching period.ADC and DPWM gains are set to 128 and 0.0039, respectively.The step response offered by the three-pole two-zero (complex)-based unoptimized and optimized digital controllers described in Equations ( 46) and (47), respectively, for the modified plant described in Equation ( 45) is shown in Figure 14.From the step response offered by the controllers, it is depicted that the optimized controller offers better static performance characteristics as compared to its unoptimized form (see Table 4).In addition, at the time of transient, the response takes much less time to recover to its steady-state value with a controlled peak spike.For example, for a load current change of 0.44 A to 0.22 A and then from 0.22 A to 0.44 A, the optimized controller shows less recovery time as well as reduced voltage peak-to-peak spike with regard to its traditional form (see Figure 15).Simulation results reveal that the digital controllers are well-retuned by the NLS method and offer superior static and dynamic performance.

Rapid Hardware-in-the-Loop (HiL) Implementation
The Simulink plugged-in architecture-level design tool named Xilinx System Generator (XSG), for DSP from Xilinx, is employed for the implementation of a digital control algorithm on a highspeed, high-end, and high-density Basys 3 Artix-7 FPGA board after automatically generating portable, synthesizable, and vendor-neutral VHDL code.XSG automatically invokes both the Core Generator and ChipScope generator to construct the netlist and cores, and thus the configuration bitstream, once the target device/FPGA XC7A35T-1CPG236C from Xilinx, Inc. (an American technology company) and the compilation target (Hardware Co-Simulation JTAG) are set in its settings.High-level abstractions produced by a control design engineer in the Simulink model are translated into the low-level and executable VHDL code through the bitstream.FPGAs can be easily interfaced with Simulink through the XSG environment.This enables control design engineers to

Rapid Hardware-in-the-Loop (HiL) Implementation
The Simulink plugged-in architecture-level design tool named Xilinx System Generator (XSG), for DSP from Xilinx, is employed for the implementation of a digital control algorithm on a high-speed, high-end, and high-density Basys 3 Artix-7 FPGA board after automatically generating portable, synthesizable, and vendor-neutral VHDL code.XSG automatically invokes both the Core Generator and ChipScope generator to construct the netlist and cores, and thus the configuration bitstream, once the target device/FPGA XC7A35T-1CPG236C from Xilinx, Inc. (an American technology company) and the compilation target (Hardware Co-Simulation JTAG) are set in its settings.High-level abstractions produced by a control design engineer in the Simulink model are translated into the low-level and executable VHDL code through the bitstream.FPGAs can be easily interfaced with Simulink through the XSG environment.This enables control design engineers to build sophisticated digital control algorithms quickly, with respect to the traditional Resistor-Transistor Logic (RTL) development times without having the knowledge of VHDL language, and then implement it on an FPGA, thus shortening the design and testing time.and cycle-true characteristic of the XSG makes the numerical simulations such as if they were attained through the real hardware implementation.

Conclusions
In this paper, optimization of the PZC technique-based digital controllers through the NLS method is performed to enhance the static and dynamic performance.In the proposed control methodology, which is essentially a digital redesign or emulation technique, the analog compensators with complex and real zeros designed on the basis of the PZC technique are mapped into the digital compensators by using a bilinear transformation technique with an appropriate sampling period.Discrete-time approximation of continuous-time controllers, even when accomplished through using the 'best' Tustin transformation, introduces frequency distortion.Although low analog frequencies are relatively well-mapped into the same digital frequencies, high frequencies result in highly nonlinear mapping.As a result, the performance of the digital controllers deteriorates.The coefficients of the digital controllers are retuned through the NLS optimization method to enhance their performance.There occur also opportunities for improvement in compensator performance, as the placing of the compensator's real or complex zeros in the vicinity of the plant's poles ensures only nominal performance.Numerical results reveal that NLS-based optimized digital controllers exhibit superior static and dynamic performance as compared to the conventional (unoptimized) digital controllers, thus validating the effectiveness of the NLS optimization method.When comparing their performance, the NLS method outshines metaheuristic techniques such as GA.Rapid HiL implementation of the compensated buck converter system is also successfully performed.

Conclusions
In this paper, optimization of the PZC technique-based digital controllers through the NLS method is performed to enhance the static and dynamic performance.In the proposed control methodology, which is essentially a digital redesign or emulation technique, the analog compensators with complex and real zeros designed on the basis of the PZC technique are mapped into the digital compensators by using a bilinear transformation technique with an appropriate sampling period.Discrete-time approximation of continuous-time controllers, even when accomplished through using the 'best' Tustin transformation, introduces frequency distortion.Although low analog frequencies are relatively well-mapped into the same digital frequencies, high frequencies result in highly nonlinear mapping.As a result, the performance of the digital controllers deteriorates.The coefficients of the digital controllers are retuned through the NLS optimization method to enhance their performance.There occur also opportunities for improvement in compensator performance, as the placing of the compensator's real or complex zeros in the vicinity of the plant's poles ensures only nominal performance.Numerical results reveal that NLS-based optimized digital controllers exhibit superior static and dynamic performance as compared to the conventional (unoptimized) digital controllers, thus validating the effectiveness of the NLS optimization method.When comparing their performance, the NLS method outshines metaheuristic techniques such as GA.Rapid HiL implementation of the compensated buck converter system is also successfully performed.

Figure 2 .
Figure 2. AC small-signal equivalent circuit for the buck converter power stage.

1 Figure 3 .
Figure 3. Flow chart explaining the design procedure adopted for the various cases.PZC: polezero-cancellation.
e[n], e[n − 1], e[n − 2], and e[n − 3] designate the current, one sample period, two sample period, and three sample period delayed values of the error signals, respectively, whereas u

Figure 4 .
Figure 4. Bode plot of the open-loop compensated system using (a) the complex zeros and (b) the real zeros.

Figure 5 .Frequency
Figure 5. Load regulation by real and complex zeros-based compensators.

Figure 4 .
Figure 4. Bode plot of the open-loop compensated system using (a) the complex zeros and (b) the real zeros.

Figure 4 .
Figure 4. Bode plot of the open-loop compensated system using (a) the complex zeros and (b) the real zeros.

Figure 5 .Frequency
Figure 5. Load regulation by real and complex zeros-based compensators.

Figure 7 .
Figure 7. Bode plot of the open-loop compensated buck converter system.

Figure 11 .
Figure 11.Bode plot of the unoptimized and optimized G p (z) • G c (z).

Figure 11 .
Figure 11.Bode plot of the unoptimized and optimized

Figure 12 .
Figure 12.Output voltage response of the optimized digital controllers.

sT.Figure 12 .
Figure 12.Output voltage response of the optimized digital controllers.

Figure 13 .
Figure 13.Iterative process offered by the nonlinear least squares (NLS) method.

Figure 13 .
Figure 13.Iterative process offered by the nonlinear least squares (NLS) method.

Figure 15 .
Figure 15.Response of the controllers against the changes in load current.

Figure
FigureResponse of the controllers against the changes in load current.

Figure 17 .
Figure 17.Output voltage response obtained through the Simulink and Xilinx System Generator (XSG)-based compensated system.

Figure 17 .
Figure 17.Output voltage response obtained through the Simulink and Xilinx System Generator (XSG)-based compensated system.

Table 1 .
Buck converter transfer function.

Table 1 .
Buck converter transfer function.

Table 3 .
Comparative analysis of controllers' performance characteristics.

Table 3 .
Comparative analysis of controllers' performance characteristics.
14.1z 3 − 11.68z 2 − 13.51z + 12.27 z 3 + 0.4273z 2 − 0.9566z − 0.4707 (46)On the optimization of this digital controller through the nonlinear least squares method, somewhat deviated coefficients are observed this time.The optimized digital controller for the modified plant comes out to be

Table 4 .
Comparison of performance characteristics.

Table 4 .
Comparison of performance characteristics.

Table 4 .
Comparison of performance characteristics.