FPGA Implementation of a Three-Level Boost Converter-fed Seven-Level DC-Link Cascade H-Bridge inverter for Photovoltaic Applications

This paper presents an optimized single-phase three-level boost DC-link cascade H-bridge multilevel inverter (TLBDCLCHB MLI) system to generate a seven-level stepped output voltage waveform for photovoltaic (PV) applications. The proposed TLBDCLCHB MLI system is obtained by integrating a three-level boost converter (TLBC) with a seven-level DC-link cascade H-bridge (DCLCHB) inverter. It consists of a TLBC, level generation unit (LGU) and phase sequence generation unit (PSGU). When compared with traditional boost converter-fed multilevel inverter systems, the proposed TLBDCLCHB MLI system requires a single DC source, fewer power switches and gate drivers. Reduction in the switch count and number of DC sources makes the system cost effective and requires a smaller installation area. Pulse generation for the power switches of an LGU in a DCLCHB inverter is accomplished by providing proper conducting angles that are generated by optimized conducting angle determination (CAD) techniques. In this paper two CAD techniques i.e., equal-phase CAD (EPCAD) and step pulse wave CAD (SPWCAD) techniques are proposed to evaluate the performance of the proposed system in terms of the total harmonic distortion (THD) and the quality of the stepped output voltage waveform. The proposed system has been modeled and simulated using MATLAB/SIMULINK software. Results are presented and discussed. Also, a prototype model of a single-phase TLBDCLCHB MLI system is developed using a field-programmable gate array (FPGA)-based pulse generation with a resistive load and its performance is analyzed for various operating conditions.


Introduction
Development in power electronics lay down a widespread scope for the resourceful operation of power converters.A few setups of power converters are produced to do the sun-powered photovoltaic (PV) applications with enhanced adequacy [1,2].PV power generation is an encouraging elective source of energy and has numerous focal points compared to the other elective energy sources like wind, ocean, biomass, fuel, geothermal, and so on.In PV power generation, boost converters and multilevel inverters (MLIs) are playing a major role in power conversion.These power converters are broadly being utilized as a connection between load and supply.As most of the renewable power source generation is DC in nature, the DC-DC boost converters are utilized to increase the voltage level, and the DC must be changed over to AC for grid connection.Therefore, MLIs are used for DC to AC conversion [3,4].The power generation using a traditional boost converter and inverter consists of a greater number of components, requires a larger installation area, is bulky in size, and costly.Also, the traditional boost converters are unable to produce a high boost ratio [5,6].This paper proposes a three-level boost converter (TLBC) with a high boost ratio, based on one switch, one inductor, (2N-1) capacitors, and (2N-1) diodes for 'N' levels.It is a pulse width modulation (PWM)-controlled boost converter capable of maintaining an equal voltage in all 'N' output levels and controlling the input current.
In this paper, the structure of single-phase three-level boost DC-link cascade H-bridge multilevel inverter (TLBDCLCHB MLI) system is proposed to generate a seven-level stepped output voltage waveform for PV applications.The proposed system is obtained by integrating a three-level boost converter (TLBC) with a seven-level DC-link cascade H-bridge (DCLCHB) [7,8].Also, the objective of the proposed work is to investigate the performance of a single-phase seven-level DCLCHB inverter [9,10] using conducting angle determination (CAD) techniques [11] in terms of the total harmonic distortion (THD) and the quality of the stepped output voltage waveform.Here, equal-phase CAD (EPCAD) based on equal-area distribution and step pulse wave CAD (SPWCAD) based on volt-second area equal to step pulse wave techniques are proposed to evaluate the performance of the DCLCHB inverter [12].The proposed TLBDCLCHB MLI system is modeled, simulated and validated through experimental setup using field-programmable gate array (FPGA)-based pulse generation.

Structure of TLBDCLCHB MLI System
The block diagram of the proposed TLBDCLCHB MLI system is shown in Figure 1.The proposed TLBDCLCHB MLI system consists of single DC voltage source, TLBC, and DCLCHB inverter to generate a seven-level stepped output waveform.The DCLCHB inverter is composed of level generation unit (LGU) and phase sequence generation unit (PSGU).LGU is used to generate the required number of levels and PSGU is used to generate positive and negative sequence voltage levels [13].The equivalent structure of TLBDCLCHB MLI system is shown in Figure 2.
Electronics 2018, 7, x FOR PEER REVIEW 2 of 22 converter and inverter consists of a greater number of components, requires a larger installation area, is bulky in size, and costly.Also, the traditional boost converters are unable to produce a high boost ratio [5,6].This paper proposes a three-level boost converter (TLBC) with a high boost ratio, based on one switch, one inductor, (2N-1) capacitors, and (2N-1) diodes for 'N' levels.It is a pulse width modulation (PWM)-controlled boost converter capable of maintaining an equal voltage in all 'N' output levels and controlling the input current.
In this paper, the structure of single-phase three-level boost DC-link cascade H-bridge multilevel inverter (TLBDCLCHB MLI) system is proposed to generate a seven-level stepped output voltage waveform for PV applications.The proposed system is obtained by integrating a three-level boost converter (TLBC) with a seven-level DC-link cascade H-bridge (DCLCHB) [7,8].Also, the objective of the proposed work is to investigate the performance of a single-phase seven-level DCLCHB inverter [9,10] using conducting angle determination (CAD) techniques [11] in terms of the total harmonic distortion (THD) and the quality of the stepped output voltage waveform.Here, equal-phase CAD (EPCAD) based on equal-area distribution and step pulse wave CAD (SPWCAD) based on volt-second area equal to step pulse wave techniques are proposed to evaluate the performance of the DCLCHB inverter [12].The proposed TLBDCLCHB MLI system is modeled, simulated and validated through experimental setup using field-programmable gate array (FPGA)-based pulse generation.

Structure of TLBDCLCHB MLI System
The block diagram of the proposed TLBDCLCHB MLI system is shown in Figure 1.The proposed TLBDCLCHB MLI system consists of single DC voltage source, TLBC, and DCLCHB inverter to generate a seven-level stepped output waveform.The DCLCHB inverter is composed of level generation unit (LGU) and phase sequence generation unit (PSGU).LGU is used to generate the required number of levels and PSGU is used to generate positive and negative sequence voltage levels [13].The equivalent structure of TLBDCLCHB MLI system is shown in Figure 2. The number of power switches 'NSwitches' and the number of levels 'm' for a single-phase TLBDCLCHB MLI system are calculated using Equations ( 1) and (2), respectively.

𝑚 = (2𝐶 + 1)
(1) where 'C' is the number of DC link capacitors integrated to a DCLCHB inverter and 'H' is the number of H-Bridge circuits.The number of power switches 'N Switches ' and the number of levels 'm' for a single-phase TLBDCLCHB MLI system are calculated using Equations ( 1) and (2), respectively.m = (2C + 1) H (1) where 'C' is the number of DC link capacitors integrated to a DCLCHB inverter and 'H' is the number of H-Bridge circuits.Table 1 demonstrates the required number of power switches and DC sources for the traditional and proposed boost DC-link-based inverter to generate a stepped output waveform from seven levels to fifteen levels.From the investigation, it is gathered that the proposed TLBDCLCHB MLI system has reduced the switch count and requires just a single DC source compared to traditional boost multilevel inverter (MLI) systems [14,15].

Three-Level Boost Converter (TLBC)
The circuit configuration of DC-DC TLBC is represented in Figure 2. It consists of a traditional boost converter, (2N-1) capacitors, and (2N-1) diodes.The main advantages of using the TLBC topology are; it can be extended to any number of levels by adding only diodes and capacitors without changing the main circuit; no need of additional voltage balance circuit; and voltage gain can be increased without the use of a transformer by operating at minimum duty ratio.The TLBC circuit consists of three stages which are operated by varying duty cycles of 0.4, 0.5, and 0.6.The operation of the TLBC is explained in [16].

Analysis of DC-DC TLBC
Considering the presence and absence of inductor power loss for both traditional and proposed TLBCs gives important information to designers.From basic principles, the voltage gain or the boost factor of the traditional boost converter [14] is given by Equation (3): where 'Vo' is the output voltage, 'Vdc' is the input voltage and 'D' is the duty cycle.Table 1 demonstrates the required number of power switches and DC sources for the traditional and proposed boost DC-link-based inverter to generate a stepped output waveform from seven levels to fifteen levels.From the investigation, it is gathered that the proposed TLBDCLCHB MLI system has reduced the switch count and requires just a single DC source compared to traditional boost multilevel inverter (MLI) systems [14,15].

Three-Level Boost Converter (TLBC)
The circuit configuration of DC-DC TLBC is represented in Figure 2. It consists of a traditional boost converter, (2N-1) capacitors, and (2N-1) diodes.The main advantages of using the TLBC topology are; it can be extended to any number of levels by adding only diodes and capacitors without changing the main circuit; no need of additional voltage balance circuit; and voltage gain can be increased without the use of a transformer by operating at minimum duty ratio.The TLBC circuit consists of three stages which are operated by varying duty cycles of 0.4, 0.5, and 0.6.The operation of the TLBC is explained in [16].

Analysis of DC-DC TLBC
Considering the presence and absence of inductor power loss for both traditional and proposed TLBCs gives important information to designers.From basic principles, the voltage gain or the boost factor of the traditional boost converter [14] is given by Equation (3): where 'V o ' is the output voltage, 'V dc ' is the input voltage and 'D' is the duty cycle.By considering the lossless system, the voltage gain for the N-level boost converter can be expressed as: For a lossless system, the input current, I dc , can be expressed as: From Equation ( 5), the input current, I dc , can be controlled using duty cycle 'D' in the PWM.Now the voltage gain or boost factor expression for the N-level boost converter can be derived as follows: Based on the condition that the average voltage across the inductor 'L' is equal to zero.The total inductor voltage during the ON-OFF condition can be expressed as, where, 'I L ' is the inductor current which is equivalent to 'I dc ' and 'R L ' is the inductor resistance or parasitic resistance.
Here, the first term of Equation ( 6) is valid when the switch 'S' is turned ON, and the second term can write when the switch 'S' is turned OFF.From Equation ( 6) it can be written as, From Equation ( 7), Therefore, from Equations (3)-( 7), the input voltage, V dc can be expressed as, Therefore, Equation ( 9) can be expressed as follows: Equation ( 10) is equal to Equation (3) if N = 1 and R L = 0. From Equation (10), it can be observed that the voltage gain reaches a maximum before D = 1, and then becomes 0. The effect of parasitic resistance 'R L ' is responsible for the limitation in the boost factor.The actual boost factor or voltage gain against the duty cycle is analyzed by varying 'R L ' in Equation (10).Figures 3 and 4 describe the graph between voltage gain versus duty cycle for the traditional boost converter, i.e., N = 1 and for the proposed TLBC, i.e., N = 3 using different values of R L /Ro.Equation ( 10) is equal to Equation (3) if N = 1 and RL = 0. From Equation (10), it can be observed that the voltage gain reaches a maximum before D = 1, and then becomes 0. The effect of parasitic resistance 'RL' is responsible for the limitation in the boost factor.The actual boost factor or voltage gain against the duty cycle is analyzed by varying 'RL' in Equation (10).Figures 3 and 4 describe the graph between voltage gain versus duty cycle for the traditional boost converter, i.e., N = 1 and for the proposed TLBC, i.e., N = 3 using different values of RL/Ro.From the Figures 3 and 4, it can be noticed that the voltage gain of the traditional boost converter is quasi-linear when the duty cycle varies from 0 to 0.5, but beyond that, the boost factor of a traditional boost converter becomes non-linear; therefore, the control of a traditional boost converter is complicated.
Similarly, from Figure 4, i.e., when N = 3, it can be observed that the quasi-linear region is extended with a high voltage gain for the TLBC.Therefore, the TLBC achieves a high voltage gain compared to the traditional boost converter, and, also a better operating point of the duty cycle for the TLBC, which is from 0.4 to 0.6.
In the next section, the effect of the voltage drop across the switch and diodes is studied.

TLBC Voltage Drop Across Switch and Diodes
In actual operation of TLBC, the voltage drop across the switch and diodes must be considered since it avoids full charge across the capacitors [17,18].Therefore, it reduces the conversion efficiency of the TLBC topology.In general, the voltage drop in the power switches and diodes can be around 2 V, and it can be neglected in medium-and high-voltage applications but must be considered in low-voltage applications.Here, the voltage drop across the switch and diodes is assumed to be equal to 'Vd'.
From Figure 5, it can be noticed that the voltage across the C5 becomes, From the Figures 3 and 4, it can be noticed that the voltage gain of the traditional boost converter is quasi-linear when the duty cycle varies from 0 to 0.5, but beyond that, the boost factor of a traditional boost converter becomes non-linear; therefore, the control of a traditional boost converter is complicated.
Similarly, from Figure 4, i.e., when N = 3, it can be observed that the quasi-linear region is extended with a high voltage gain for the TLBC.Therefore, the TLBC achieves a high voltage gain compared to the traditional boost converter, and, also a better operating point of the duty cycle for the TLBC, which is from 0.4 to 0.6.
In the next section, the effect of the voltage drop across the switch and diodes is studied.

TLBC Voltage Drop Across Switch and Diodes
In actual operation of TLBC, the voltage drop across the switch and diodes must be considered since it avoids full charge across the capacitors [17,18].Therefore, it reduces the conversion efficiency of the TLBC topology.In general, the voltage drop in the power switches and diodes can be around 2 V, and it can be neglected in medium-and high-voltage applications but must be considered in low-voltage applications.Here, the voltage drop across the switch and diodes is assumed to be equal to 'V d '.
From Figure 5, it can be noticed that the voltage across the C 5 becomes, where, '2V d ' is the voltage drop across the switch 'S' and diode 'D 5 .
Similarly, V C2 and V C1 can be written as, where, V C2 and V C1 are the expressions for the voltage output of two-level and three-level boost converters, respectively.The generalized output voltage expression for the N-level boost converter can be expressed as follows: where, 'V C ' is the lower capacitor output voltage, and follows Equation (3).Equation ( 14) gives the output voltage for the multiple stages of the boost converter.The efficiency of the proposed converter for the N-level is given by the Equation ( 15).
Form Equation ( 15), the efficiency of the TLBC circuit can be reduced by considering the voltage drop across the switch and diode.
Form Equation ( 15), the efficiency of the TLBC circuit can be reduced by considering the voltage drop across the switch and diode.

Closed-Loop Control of TLBC
From Figure 5 and Equation (10), it can be observed that the output voltage gain depends on the ratio of load resistance (RO) and source resistance (RL), i.e., if there is any variation between the load and source resistances, the output voltage of TLBC is not kept constant, and, from Equation ( 13), there will be a variation in the duty cycle to get the required amount of output voltage by considering the voltage drop across the switch and diodes.Therefore, the proposed TLBC circuit is modeled in closed-loop mode using an integral controller to maintain the constant output voltage.
Figure 6 represents the TLBC circuit in closed-loop mode.In the case of any variation in the load side or source side, the output changes, so a suitable controller is designed to change the duty cycle by comparing 'Vref' with 'Vout' in order to maintain the required output voltage.

Closed-Loop Control of TLBC
From Figure 5 and Equation (10), it can be observed that the output voltage gain depends on the ratio of load resistance (R O ) and source resistance (R L ), i.e., if there is any variation between the load and source resistances, the output voltage of TLBC is not kept constant, and, from Equation ( 13), there will be a variation in the duty cycle to get the required amount of output voltage by considering the voltage drop across the switch and diodes.Therefore, the proposed TLBC circuit is modeled in closed-loop mode using an integral controller to maintain the constant output voltage.
Figure 6 represents the TLBC circuit in closed-loop mode.In the case of any variation in the load side or source side, the output changes, so a suitable controller is designed to change the duty cycle by comparing 'V ref ' with 'V out ' in order to maintain the required output voltage.

Closed-Loop Control of TLBC
From Figure 5 and Equation ( 10), it can be observed that the output voltage gain depends on the ratio of load resistance (RO) and source resistance (RL), i.e., if there is any variation between the load and source resistances, the output voltage of TLBC is not kept constant, and, from Equation ( 13), there will be a variation in the duty cycle to get the required amount of output voltage by considering the voltage drop across the switch and diodes.Therefore, the proposed TLBC circuit is modeled in closed-loop mode using an integral controller to maintain the constant output voltage.
Figure 6 represents the TLBC circuit in closed-loop mode.In the case of any variation in the load side or source side, the output changes, so a suitable controller is designed to change the duty cycle by comparing 'Vref' with 'Vout' in order to maintain the required output voltage.Switches in the LGU are used to generate the required number of levels and it is formed by connecting half-bridge cells in series.Each half-bridge cell consists of a DC source controlled by two switches.PSGU consists of an H-bridge circuit, which is used to generate the positive and negative sequence voltage levels.Table 2 gives a component requirement to generate a seven-level output voltage for the proposed and existing MLIs.It clearly shows a substantial component reduction Switches in the LGU are used to generate the required number of levels and it is formed by connecting half-bridge cells in series.Each half-bridge cell consists of a DC source controlled by two switches.PSGU consists of an H-bridge circuit, which is used to generate the positive and negative sequence voltage levels.Table 2 gives a component requirement to generate a seven-level output voltage for the proposed and existing MLIs.It clearly shows a substantial component reduction when using a DCLCHB structure [7,8].In this DCLCHB inverter topology, all the magnitudes of DC voltage sources are equal (V dc1 = V dc2 = V dc3 ).

DC-Link Cascade H-Bridge (DCLCHB) Inverter
i.e., V dci = V dc , where i = 1, 2, and 3 The maximum value of the output phase voltage is obtained by using Equation (17).
The number of output phase voltage levels can be obtained from Equation (1).The number of power switches for the DCLCHB inverter can be calculated using Equation (18).
Equation ( 16) gives the output level of the LGU.By using PSGU, the positive and negative levels are obtained at the load (V o ), the synthesized stepped AC output phase voltage will be obtained by using the Equations ( 19) and (20).
For a single-phase seven-level DCLCHB inverter, the switching sequences to generate the required levels are given in Table 3.

Conducting Angle Determination (CAD) Techniques
CAD techniques are a vital part of any inverter since they are directly related to the efficiency of the entire system [6,12].It is used to control the proposed DCLCHB inverter output phase voltage and also for the calculation of the two main parameters such as %THD and V rms .In this paper, a step pulse wave CAD (SPWCAD) technique has been employed to trigger the switches of LGU in the DCLCHB inverter and is compared with a conventional CAD technique, i.e., equal-phase CAD (EPCAD) technique.The generation of the seven-level stepped voltage waveform using CAD techniques is shown in Figure 8.

Conducting Angle Determination (CAD) Techniques
CAD techniques are a vital part of any inverter since they are directly related to the efficiency of the entire system [6,12].It is used to control the proposed DCLCHB inverter output phase voltage and also for the calculation of the two main parameters such as %THD and Vrms.In this paper, a step pulse wave CAD (SPWCAD) technique has been employed to trigger the switches of LGU in the DCLCHB inverter and is compared with a conventional CAD technique, i.e., equal-phase CAD (EPCAD) technique.The generation of the seven-level stepped voltage waveform using CAD techniques is shown in Figure 8.In the presented EPCAD and SPWCAD techniques, for an m-level stepped waveform in the period of the first quadrant, i.e., 0 to 90 • , 2(m − 1)/2 conducting angles need to be determined.From Figure 8, to generate a seven-level stepped waveform in the first quadrant, i.e., 0 to 90 • , three conducting angles need to be determined.They are defined as the main conducting angles, i.e., α 1 , α 2 and α 3 using the time-sequence.From Figure 8, it can be noticed that only the main conducting angles need to be determined; the rest of the conducting angles can be derived from the main conducting angles.The solution of the main conducting angles, i.e., α 1 , α 2 and α 3 must satisfy the following condition:

EPCAD Technique
In the EPCAD technique the main conducting angles are derived by taking an average distribution of the conducting angles from 0 to180 • .In this technique, the main conducting angles are obtained by using Equation (22).

2
, m = number of levels.

SPWCAD Technique
In the proposed SPWCAD technique, conducting angles are acquired by computing the volt-second areas of the sine reference voltage waveform that is equivalent to the stepped output phase voltage waveform of the DCLCHB inverter.In the seven-level DCLCHB inverter, since three half-bridge cells are connected in series, the reference voltage 'V ref ' and output-phase voltage 'V out-phase ' can be obtained by the Equations ( 23) and ( 24) respectively: where, 'M i ' is the modulation index, and 'i' is the integer number.Figure 9 demonstrates the dummy conducting angles (α i 1 ) in the case of M i = π/4.The areas of In the EPCAD technique the main conducting angles are derived by taking an average distribution of the conducting angles from 0 to180°.In this technique, the main conducting angles are obtained by using Equation ( 22).

SPWCAD Technique
In the proposed SPWCAD technique, conducting angles are acquired by computing the volt-second areas of the sine reference voltage waveform that is equivalent to the stepped output phase voltage waveform of the DCLCHB inverter.In the seven-level DCLCHB inverter, since three half-bridge cells are connected in series, the reference voltage 'Vref' and output-phase voltage 'Vout-phase' can be obtained by the Equations ( 23) and ( 24) respectively: where, 'Mi' is the modulation index, and 'i' is the integer number.Figure 9 demonstrates the dummy conducting angles (αi 1 ) in the case of Mi = π/4.The areas of A1 1 , A2 1 , and A3 1 are encompassed by the sine reference voltage wave and the stepped output-phase voltage levels in the positive half-cycle of the seven-level DCLCHB inverter.The generation of a step pulse wave in the DCLCHB inverter to meet the equivalent areas as A1 1 , A2 1 , and A3 1 .Here, main conducting angles ( ) are defined as the switching timing angles of step Area, A 1 1 can be obtained from Equation (25): Therefore, from Equation (25), A 1 1 can be written as: From Figure 10, Area, A 1 can be expressed as, Since A 1 1 is equal to A 1 , the real conducting angle α 1 of the proposed SPWCAD technique is obtained as, Similarly, by equating A 2 1 to A 2 , the angle α 2 can be expressed as, α 3 can be obtained by equating A 3 1 to A 3 or by using Equation (30): For a seven-level DCLCHB inverter, the conducting angles are calculated by using Equations ( 31)-(33).
Therefore, for a seven-level stepped waveform using the SPWCAD technique, three main conducting angles need to determined using Equations ( 31 From Figure 10, Area, A1 can be expressed as, Since A1 1 is equal to A1, the real conducting angle  of the proposed SPWCAD technique is obtained as, Similarly, by equating A2 1 to A2, the angle  can be expressed as, can be obtained by equating A3 1 to A3 or by using Equation (30): For a seven-level DCLCHB inverter, the conducting angles are calculated by using Equations (31)-(33).

Comparison of the SPWCAD and EPCAD Technique
The conducting angles acquired by the SPWCAD technique are different from those acquired by the EPCAD technique.In the SPWCAD technique, conducting angles are acquired based on the modulation index (M i ) whereas the EPCAD technique gives the same conducting angles irrespective of the M i .The proposed SPWCAD technique method can be applied to different modulation indices.The range of M i and the number of conducting angles are listed in Table 4. Also, the values of conducting angles for the proposed SPWCAD technique using various modulation indices are listed in Table 5 for the DCLCHB inverter.

THD Calculation of the Seven-Level Stepped Output Phase Voltage using CAD Techniques
The general THD expression for a periodic output phase voltage for a proposed DCLCHB inverter can be expressed as, where V 1 is the RMS (root mean square) value of the fundamental component and V rms is the RMS value of the output phase voltage.For the proposed seven-level RV MLI, V rms and V 1 can be obtained by using Equations ( 35) and (36).
The output phase voltage THD expression for the proposed seven-level DCLCHB inverter can be obtained by substituting Equations ( 35) and (36) into Equation (34) and is given by: Theoretical values of the output phase voltage THD for the seven-level DCLCHB inverter using EPCAD and the proposed SPWCAD techniques with the corresponding main conducting angles are given in Table 6.

Simulation and Experimental Validation of the Proposed TLBDCLCHB Inverter System
The simulation of the proposed single-phase seven-level TLBDCLCHB inverter system is analyzed using MATLAB Simulink and validated experimentally through FPGA-based pulse generation.

TLBC Simulation Results in Open-Loop Mode
The simulation of the TLBC is carried out and analyzed in open-loop mode by considering the DC input voltage V dc of 50 V, which should be boosted to a total DC-link voltage of 250 V, 300 V, and 375 V for the duty cycles of 0.4, 0.5, and 0.6, respectively, and the voltage across each of the capacitors at the output should be boosted to 83.33 V, 100 V, and 125 V for the duty cycles of 0.4, 0.5, and 0.6, respectively, as shown in Figures 11-13.

Simulation and Experimental Validation of the Proposed TLBDCLCHB Inverter System
The simulation of the proposed single-phase seven-level TLBDCLCHB inverter system is analyzed using MATLAB Simulink and validated experimentally through FPGA-based pulse generation.

TLBC Simulation Results in Open-Loop Mode
The simulation of the TLBC is carried out and analyzed in open-loop mode by considering the DC input voltage Vdc of 50 V, which should be boosted to a total DC-link voltage of 250 V, 300 V, and 375 V for the duty cycles of 0.4, 0.5, and 0.6, respectively, and the voltage across each of the capacitors at the output should be boosted to 83.33 V, 100 V, and 125 V for the duty cycles of 0.4, 0.5, and 0.6, respectively, as shown in Figures 11-13.

Simulation and Experimental Validation of the Proposed TLBDCLCHB Inverter System
The simulation of the proposed single-phase seven-level TLBDCLCHB inverter system is analyzed using MATLAB Simulink and validated experimentally through FPGA-based pulse generation.

TLBC Simulation Results in Open-Loop Mode
The simulation of the TLBC is carried out and analyzed in open-loop mode by considering the DC input voltage Vdc of 50 V, which should be boosted to a total DC-link voltage of 250 V, 300 V, and 375 V for the duty cycles of 0.4, 0.5, and 0.6, respectively, and the voltage across each of the capacitors at the output should be boosted to 83.33 V, 100 V, and 125 V for the duty cycles of 0.4, 0.5, and 0.6, respectively, as shown in Figures 11-13.

Simulation and Experimental Validation of the Proposed TLBDCLCHB Inverter System
The simulation of the proposed single-phase seven-level TLBDCLCHB inverter system is analyzed using MATLAB Simulink and validated experimentally through FPGA-based pulse generation.

TLBC Simulation Results in Open-Loop Mode
The simulation of the TLBC is carried out and analyzed in open-loop mode by considering the DC input voltage Vdc of 50 V, which should be boosted to a total DC-link voltage of 250 V, 300 V, and 375 V for the duty cycles of 0.4, 0.5, and 0.6, respectively, and the voltage across each of the capacitors at the output should be boosted to 83.33 V, 100 V, and 125 V for the duty cycles of 0.4, 0.5, and 0.6, respectively, as shown in Figures 11-13.From Figures 11-13, it is observed that the total DC-link output voltage for the duty cycles of 0.4, 0.5, and 0.6 has been boosted to 242.6, 291.4 V, and 361.4 V as opposed to 250 V, 300 V, and 375 V, respectively, due to the voltage drop across the switch and diodes.Similarly, the voltage drops across each of the capacitors are boosted to 82.17 V, 98.5 V, and 121.8 V as opposed to 83.33 V, 100 V, and 125 V. Also, it is noticed that the ripple in the total DC-link output voltage and voltage across each capacitor are increased by increasing the duty cycle from 0.4 to 0.6 to achieve the maximum DC-link output voltage with minimum ripple.Further, the open-loop mode of TLBC is extended to operate in closed-loop mode to maintain the required amount of DC-link output voltage by compensating the voltage drop across the switch and diodes, and, also, to reduce the ripple.

TLBC Simulation Results in Closed-Loop Mode
The proposed TLBC is implemented in closed-loop to maintain the constant output voltage using the voltage control loop.Here, the output of TLBC is measured and fed to an integral controller by comparing with the required reference output voltage to vary the duty cycle.Figure 14 shows the total DC-link output voltage and the voltage across each capacitor of the TLBC in closed-loop mode for D = 0.5.The corresponding change in duty cycle due to the reference output voltage is shown in Figure 15.
Electronics 2018, 7, x FOR PEER REVIEW 13 of 22 From Figures 11-13, it is observed that the total DC-link output voltage for the duty cycles of 0.4, 0.5, and 0.6 has been boosted to 242.6, 291.4 V, and 361.4 V as opposed to 250 V, 300 V, and 375 V, respectively, due to the voltage drop across the switch and diodes.Similarly, the voltage drops across each of the capacitors are boosted to 82.17 V, 98.5 V, and 121.8 V as opposed to 83.33 V, 100 V, and 125 V. Also, it is noticed that the ripple in the total DC-link output voltage and voltage across each capacitor are increased by increasing the duty cycle from 0.4 to 0.6 to achieve the maximum DC-link output voltage with minimum ripple.Further, the open-loop mode of TLBC is extended to operate in closed-loop mode to maintain the required amount of DC-link output voltage by compensating the voltage drop across the switch and diodes, and, also, to reduce the ripple.

TLBC Simulation Results in Closed-Loop Mode
The proposed TLBC is implemented in closed-loop to maintain the constant output voltage using the voltage control loop.Here, the output of TLBC is measured and fed to an integral controller by comparing with the required reference output voltage to vary the duty cycle.Figure 14 shows the total DC-link output voltage and the voltage across each capacitor of the TLBC in closed-loop mode for D = 0.5.The corresponding change in duty cycle due to the reference output voltage is shown in Figure 15.From Figures 11-13, it is observed that the total DC-link output voltage for the duty cycles of 0.4, 0.5, and 0.6 has been boosted to 242.6, 291.4 V, and 361.4 V as opposed to 250 V, 300 V, and 375 V, respectively, due to the voltage drop across the switch and diodes.Similarly, the voltage drops across each of the capacitors are boosted to 82.17 V, 98.5 V, and 121.8 V as opposed to 83.33 V, 100 V, and 125 V. Also, it is noticed that the ripple in the total DC-link output voltage and voltage across each capacitor are increased by increasing the duty cycle from 0.4 to 0.6 to achieve the maximum DC-link output voltage with minimum ripple.Further, the open-loop mode of TLBC is extended to operate in closed-loop mode to maintain the required amount of DC-link output voltage by compensating the voltage drop across the switch and diodes, and, also, to reduce the ripple.

TLBC Simulation Results in Closed-Loop Mode
The proposed TLBC is implemented in closed-loop to maintain the constant output voltage using the voltage control loop.Here, the output of TLBC is measured and fed to an integral controller by comparing with the required reference output voltage to vary the duty cycle.Figure 14 shows the total DC-link output voltage and the voltage across each capacitor of the TLBC in closed-loop mode for D = 0.5.The corresponding change in duty cycle due to the reference output voltage is shown in Figure 15.From the Figures 14 and 15, it is observed that the total DC-link output voltage and the voltage across each capacitor of the TLBC is boosted to 300 V and 100 V, respectively, as per the reference output voltage by changing the duty cycle using an integral controller.

TLBDCLCHB Inverter Output using CAD Techniques
Simulation results of TLBC-fed DCLCHB inverter to generate a seven-level stepped output waveform using EPCAD and SPWCAD techniques and its THD analysis are shown in Figures 16-21 for D = 0.5.
Electronics 2018, 7, x FOR PEER REVIEW 14 of 22 From the Figures 14 and 15, it is observed that the total DC-link output voltage and the voltage across each capacitor of the TLBC is boosted to 300 V and 100 V, respectively, as per the reference output voltage by changing the duty cycle using an integral controller.

TLBDCLCHB Inverter Output using CAD Techniques
Simulation results of TLBC-fed DCLCHB inverter to generate a seven-level stepped output waveform using EPCAD and SPWCAD techniques and its THD analysis are shown in Figures 16-21 for D = 0.5.From the Figures 14 and 15, it is observed that the total DC-link output voltage and the voltage across each capacitor of the TLBC is boosted to 300 V and 100 V, respectively, as per the reference output voltage by changing the duty cycle using an integral controller.

TLBDCLCHB Inverter Output using CAD Techniques
Simulation results of TLBC-fed DCLCHB inverter to generate a seven-level stepped output waveform using EPCAD and SPWCAD techniques and its THD analysis are shown in Figures 16-21 for D = 0.5.From the Figures 14 and 15, it is observed that the total DC-link output voltage and the voltage across each capacitor of the TLBC is boosted to 300 V and 100 V, respectively, as per the reference output voltage by changing the duty cycle using an integral controller.

TLBDCLCHB Inverter Output using CAD Techniques
Simulation results of TLBC-fed DCLCHB inverter to generate a seven-level stepped output waveform using EPCAD and SPWCAD techniques and its THD analysis are shown in Figures 16-21 for D = 0.5.

Using the EPCAD Technique
Figure 16 shows the output voltage across the LGU in the DCLCHB inverter.Referring to Figure 16, the LGU generates a unipolar stepped waveform, and it can be converted to a bipolar stepped wave using PSGU.Figures 17 and 18 show the seven-level stepped output phase voltage and its THD analysis of the TLBDCLCHB inverter using the EPCAD technique for the duty cycle of 0.5.It is observed that the magnitude of the fundamental output phase voltage and its RMS value is 229.9V and 162.5 V, respectively.Also, the THD of the proposed TLBDCLCHB inverter output using the EPCAD technique is 30.08%.

Using the EPCAD Technique
Figure 16 shows the output voltage across the LGU in the DCLCHB inverter.Referring to Figure 16, the LGU generates a unipolar stepped waveform, and it can be converted to a bipolar stepped wave using PSGU.Figures 17 and 18 show the seven-level stepped output phase voltage and its THD analysis of the TLBDCLCHB inverter using the EPCAD technique for the duty cycle of 0.5.It is observed that the magnitude of the fundamental output phase voltage and its RMS value is 229.9V and 162.5 V, respectively.Also, the THD of the proposed TLBDCLCHB inverter output using the EPCAD technique is 30.08%.

Using the EPCAD Technique
Figure 16 shows the output voltage across the LGU in the DCLCHB inverter.Referring to Figure 16, the LGU generates a unipolar stepped waveform, and it can be converted to a bipolar stepped wave using PSGU.Figures 17 and 18 show the seven-level stepped output phase voltage and its THD analysis of the TLBDCLCHB inverter using the EPCAD technique for the duty cycle of 0.5.It is observed that the magnitude of the fundamental output phase voltage and its RMS value is 229.9V and 162.5 V, respectively.Also, the THD of the proposed TLBDCLCHB inverter output using the EPCAD technique is 30.08%.

Using the EPCAD Technique
Figure 16 shows the output voltage across the LGU in the DCLCHB inverter.Referring to Figure 16, the LGU generates a unipolar stepped waveform, and it can be converted to a bipolar stepped wave using PSGU.Figures 17 and 18 show the seven-level stepped output phase voltage and its THD analysis of the TLBDCLCHB inverter using the EPCAD technique for the duty cycle of 0.5.It is observed that the magnitude of the fundamental output phase voltage and its RMS value is 229.9V and 162.5 V, respectively.Also, the THD of the proposed TLBDCLCHB inverter output using the EPCAD technique is 30.08%.

Using the SPWCAD Technique
The unipolar output phase voltage across the LGU in the DCLCHB inverter using the SPWCAD technique is shown in Figure 19.Figures 20 and 21 show the seven-level stepped output phase voltage and its THD analysis of the TLBDCLCHB inverter using the SPWCAD technique for the duty cycle of 0.5 with M i = 0.8.It is observed that the magnitude of the fundamental output phase voltage and its RMS value is 307.9V and 217.7 V, respectively.Also, the THD of the proposed TLBDCLCHB inverter output using the SPWCAD technique is 12.04%.The model of the proposed TLBDCLCHB inverter system-fed R-load is implemented employing Xilinx Spartan FPGA-based pulse generation [19,20] to validate the Simulink results.The block diagram, Xilinx Spartan6 development board, and the prototype model of the TLBDCLCHB inverter system using an FPGA is shown in Figures 22-24, respectively.It consists of TLBC, the DCLCHB inverter, a personal computer (PC), an FPGA controller, R-load, buffer circuit, optocoupler, and driver circuit.The output of TLBC-fed DCLCHB inverter using an FPGA controller is shown in Figure 25.

Using the SPWCAD Technique
The unipolar output phase voltage across the LGU in the DCLCHB inverter using the SPWCAD technique is shown in Figure 19.Figures 20 and 21 show the seven-level stepped output phase voltage and its THD analysis of the TLBDCLCHB inverter using the SPWCAD technique for the duty cycle of 0.5 with Mi = 0.8.It is observed that the magnitude of the fundamental output phase voltage and its RMS value is 307.9V and 217.7 V, respectively.Also, the THD of the proposed TLBDCLCHB inverter output using the SPWCAD technique is 12.04%.

Experimental Validation of the TLBDCLCHB Inverter System Using an FPGA-Based Pulse Generation
The model of the proposed TLBDCLCHB inverter system-fed R-load is implemented employing Xilinx Spartan FPGA-based pulse generation [19,20] to validate the Simulink results.The block diagram, Xilinx Spartan6 development board, and the prototype model of the TLBDCLCHB inverter system using an FPGA is shown in Figures 22-24, respectively.It consists of TLBC, the DCLCHB inverter, a personal computer (PC), an FPGA controller, R-load, buffer circuit, optocoupler, and driver circuit.The output of TLBC-fed DCLCHB inverter using an FPGA controller is shown in Figure 25.The unipolar output phase voltage across the LGU in the DCLCHB inverter using the SPWCAD technique is shown in Figure 19.Figures 20 and 21 show the seven-level stepped output phase voltage and its THD analysis of the TLBDCLCHB inverter using the SPWCAD technique for the duty cycle of 0.5 with Mi = 0.8.It is observed that the magnitude of the fundamental output phase voltage and its RMS value is 307.9V and 217.7 V, respectively.Also, the THD of the proposed TLBDCLCHB inverter output using the SPWCAD technique is 12.04%.

Experimental Validation of the TLBDCLCHB Inverter System Using an FPGA-Based Pulse Generation
The model of the proposed TLBDCLCHB inverter system-fed R-load is implemented employing Xilinx Spartan FPGA-based pulse generation [19,20] to validate the Simulink results.The block diagram, Xilinx Spartan6 development board, and the prototype model of the TLBDCLCHB inverter system using an FPGA is shown in Figures 22-24, respectively.It consists of TLBC, the DCLCHB inverter, a personal computer (PC), an FPGA controller, R-load, buffer circuit, optocoupler, and driver circuit.The output of TLBC-fed DCLCHB inverter using an FPGA controller is shown in Figure 25.Figures 27 and 28 show the generation of the pulse for the LGU switches (S 1 to S 6 ) in the DCLCHB inverter to generate the stepped output waveform using EPCAD and SPWCAD techniques, respectively, for the modulation index of 0.8. Figure 29 shows the generation of the pulse for the PSGU switches (P 1 to P 4 ) in the DCLCHB inverter to generate the positive and negative levels using an H-bridge inverter.
Figures 27 and 28 show the generation of the pulse for the LGU switches (S1 to S6) in the DCLCHB inverter to generate the stepped output waveform using EPCAD and SPWCAD techniques, respectively, for the modulation index of 0.8. Figure 29 shows the generation of the pulse for the PSGU switches (P1 to P4) in the DCLCHB inverter to generate the positive and negative levels using an H-bridge inverter.Figures 30 and 31 represent the TLBDCLCHB inverter system experimental output phase voltage and its harmonic spectrum using the EPCAD technique for the generation of a seven-level stepped output voltage.Referring to Figures 30 and 31, it is observed that the RMS value of the output phase voltage is 161.7 V and its THD is 31.5%.
Figures 32 and 33 represent the TLBDCLCHB inverter system experimental output phase voltage and its harmonic spectrum using the SPWCAD technique for the generation of a seven-level stepped output voltage.Referring to Figures 32 and 33, it is observed that the RMS value of the output phase voltage is 216 V and its THD is 11.5%.Figures 27 and 28 show the generation of the pulse for the LGU switches (S1 to S6) in the DCLCHB inverter to generate the stepped output waveform using EPCAD and SPWCAD techniques, respectively, for the modulation index of 0.8. Figure 29 shows the generation of the pulse for the PSGU switches (P1 to P4) in the DCLCHB inverter to generate the positive and negative levels using an H-bridge inverter.Figures 30 and 31 represent the TLBDCLCHB inverter system experimental output phase voltage and its harmonic spectrum using the EPCAD technique for the generation of a seven-level stepped output voltage.Referring to Figures 30 and 31, it is observed that the RMS value of the output phase voltage is 161.7 V and its THD is 31.5%.
Figures 32 and 33 represent the TLBDCLCHB inverter system experimental output phase voltage and its harmonic spectrum using the SPWCAD technique for the generation of a seven-level stepped output voltage.Referring to Figures 32 and 33, it is observed that the RMS value of the output phase voltage is 216 V and its THD is 11.5%.Figures 27 and 28 show the generation of the pulse for the LGU switches (S1 to S6) in the DCLCHB inverter to generate the stepped output waveform using EPCAD and SPWCAD techniques, respectively, for the modulation index of 0.8. Figure 29 shows the generation of the pulse for the PSGU switches (P1 to P4) in the DCLCHB inverter to generate the positive and negative levels using an H-bridge inverter.Figures 30 and 31 represent the TLBDCLCHB inverter system experimental output phase voltage and its harmonic spectrum using the EPCAD technique for the generation of a seven-level stepped output voltage.Referring to Figures 30 and 31, it is observed that the RMS value of the output phase voltage is 161.7 V and its THD is 31.5%.
Figures 32 and 33 represent the TLBDCLCHB inverter system experimental output phase voltage and its harmonic spectrum using the SPWCAD technique for the generation of a seven-level stepped output voltage.Referring to Figures 32 and 33, it is observed that the RMS value of the output phase voltage is 216 V and its THD is 11.5%.Figures 30 and 31 represent the TLBDCLCHB inverter system experimental output phase voltage and its harmonic spectrum using the EPCAD technique for the generation of a seven-level stepped output voltage.Referring to Figures 30 and 31, it is observed that the RMS value of the output phase voltage is 161.7 V and its THD is 31.5%.
Figures 32 and 33 represent the TLBDCLCHB inverter system experimental output phase voltage and its harmonic spectrum using the SPWCAD technique for the generation of a seven-level stepped output voltage.Referring to Figures 32 and 33, it is observed that the RMS value of the output phase voltage is 216 V and its THD is 11.5%.experimental results with a tolerable error of ±2%.From the analysis, it is noticed that the magnitude of V rms varies with respect to the duty cycle, but there is only a slight deviation in THD from 0.4 to 0.6.

Conclusions
In this paper, a TLBC-fed DCLCHB inverter system has been suggested to generate a seven-level stepped output phase voltage using a single DC source for better performance, efficiency, and reduced cost and size of the inverter.It also presented two control techniques for the DCLCHB inverter based on conducting angle determination, namely, EPCAD and SPWCAD techniques.Here, the SPWCAD technique gives the most extreme output phase voltage and lower THD compared to the EPCAD technique but the SPWCAD technique involves several trigonometric functions.However, same trigonometric functions are repeated; therefore, it is easy to acquire the conducting angles once the equations are derived based on the volt-second balance.In addition, TLBC has been suggested to achieve auto voltage balance and high voltage gain.Therefore, upon considering all the advantages, the proposed TLBDCLCHB inverter system is a good alternative for PV applications compared to the conventional boost-based MLI systems.

Figure 3 .
Figure 3. Duty cycle versus voltage gain of a traditional boost converter for various values of RL/Ro (N = 1).

Figure 3 .
Figure 3. Duty cycle versus voltage gain of a traditional boost converter for various values of R L /Ro (N = 1).Electronics 2018, 7, x FOR PEER REVIEW 5 of 22

Figure 4 .
Figure 4. Duty cycle versus voltage gain of TLBC for various values of RL/Ro (N = 3).

Figure 4 .
Figure 4. Duty cycle versus voltage gain of TLBC for various values of R L /Ro (N = 3).

Figure 5 .
Figure 5. Charging C5 of a TLBC with switch and diode's voltage drop.

Figure 5 .
Figure 5. Charging C5 of a TLBC with switch and diode's voltage drop.

Figure 6 .
Figure 6.Model of TLBC in closed-loop mode.Figure 6. Model of TLBC in closed-loop mode.

Figure 6 .
Figure 6.Model of TLBC in closed-loop mode.Figure 6. Model of TLBC in closed-loop mode.

Figure 7 Figure 7
Figure 7 depicts the DCLCHB inverter topology for the generation of a single-phase seven-level output voltage waveform.It is composed of LGU and PSGU [12].

Figure 8 .
Figure 8. Generation of the seven-level stepped voltage waveform for DCLCHB inverter using CAD techniques.

Figure 8 .
Figure 8. Generation of the seven-level stepped voltage waveform for DCLCHB inverter using CAD techniques.
1 , and A 3 1 are encompassed by the sine reference voltage wave and the stepped output-phase voltage levels in the positive half-cycle of the seven-level DCLCHB inverter.

Figure 9 .
Figure 9. Reference voltage waveform with dummy conducting angles.

Figure 9 .
Figure 9. Reference voltage waveform with dummy conducting angles.The generation of a step pulse wave in the DCLCHB inverter to meet the equivalent areas as A 1 1 , A 2 1 , and A 3 1 .Here, main conducting angles (α i ) are defined as the switching timing angles of step pulse waves in the DCLCHB inverter.Figure 10 represents the main conducting angles and the stepped output phase voltage of the seven-level DCLCHB inverter during the positive half cycle.Assuming that the areas A 1 , A 2 , and A 3 made by the main conducting angles in Figure 10 are equivalent to A 1 1 , A 2 1 , and A 3 1 made by dummy conducting angles which are obtained as follows: )-(33), i.e., α 1 , α 2 and α 3 and their values are 9.43 • , 29.59 • , and 55.88 • , respectively, for the M i = 0.8.

Figure 10 .
Figure 10.Output phase-voltage of a seven-level DCLCHB inverter in the positive half-cycle voltage.

Figure 10 .
Figure 10.Output phase-voltage of a seven-level DCLCHB inverter in the positive half-cycle voltage.

Figure 15 .
Figure 15.Change in duty cycle of TLBC in closed-loop.

Figure 15 .
Figure 15.Change in duty cycle of TLBC in closed-loop.Figure 15.Change in duty cycle of TLBC in closed-loop.

Figure 15 .
Figure 15.Change in duty cycle of TLBC in closed-loop.Figure 15.Change in duty cycle of TLBC in closed-loop.

Figure 21 .
Figure 21.THD analysis of the TLBDCLCHB inverter output using the SWPCAD technique.

Figure 21 .
Figure 21.THD analysis of the TLBDCLCHB inverter output using the SWPCAD technique.

Figure 21 .
Figure 21.THD analysis of the TLBDCLCHB inverter output using the SWPCAD technique.

Figure 21 .
Figure 21.THD analysis of the TLBDCLCHB inverter output using the SWPCAD technique.

6. 4 .
Experimental Validation of the TLBDCLCHB Inverter System Using an FPGA-Based Pulse Generation

Figure 22 .
Figure 22.Block diagram of the TLBDCLCHB hardware implementation.

Figure 23 .
Figure 23.Hardware implementation of the TLBDCLCHB inverter system with an FPGA controller.

Figure 22 .
Figure 22.Block diagram of the TLBDCLCHB hardware implementation.

Figure 22 .
Figure 22.Block diagram of the TLBDCLCHB hardware implementation.

Figure 23 .
Figure 23.Hardware implementation of the TLBDCLCHB inverter system with an FPGA controller.Figure 23.Hardware implementation of the TLBDCLCHB inverter system with an FPGA controller.

Figure 23 .
Figure 23.Hardware implementation of the TLBDCLCHB inverter system with an FPGA controller.Figure 23.Hardware implementation of the TLBDCLCHB inverter system with an FPGA controller.

Figure 25 .
Figure 25.Seven-level stepped output voltage of TLBC-fed DCLCHB inverter system.Referring to Figure 26, the TLBC output voltage across each capacitor and the total DC-link voltage are shown in Channel 1 (CH1) and Channel (CH2), respectively, for D = 0.5.It is observed that CH1 and CH2 voltages are boosted to 100 V and 300 V, respectively.

Figure 26 .
Figure 26.Voltage across the capacitor CH1 and total DC-link voltage of TLBC CH2 for D = 0.5.

Figure 25 .
Figure 25.Seven-level stepped output voltage of TLBC-fed DCLCHB inverter system.Referring to Figure 26, the TLBC output voltage across each capacitor and the total DC-link voltage are shown in Channel 1 (CH1) and Channel (CH2), respectively, for D = 0.5.It is observed that CH1 and CH2 voltages are boosted to 100 V and 300 V, respectively.

Figure 26 .
Figure 26.Voltage across the capacitor CH1 and total DC-link voltage of TLBC CH2 for D = 0.5.

Figure 25 . 22 Figure 24 .
Figure 25.Seven-level stepped output voltage of TLBC-fed DCLCHB inverter system.Referring to Figure 26, the TLBC output voltage across each capacitor and the total DC-link voltage are shown in Channel 1 (CH1) and Channel (CH2), respectively, for D = 0.5.It is observed that CH1 and CH2 voltages are boosted to 100 V and 300 V, respectively.

Figure 25 .
Figure 25.Seven-level stepped output voltage of TLBC-fed DCLCHB inverter system.Referring to Figure 26, the TLBC output voltage across each capacitor and the total DC-link voltage are shown in Channel 1 (CH1) and Channel (CH2), respectively, for D = 0.5.It is observed that CH1 and CH2 voltages are boosted to 100 V and 300 V, respectively.

Figure 26 .
Figure 26.Voltage across the capacitor CH1 and total DC-link voltage of TLBC CH2 for D = 0.5.

Figure 26 .
Figure 26.Voltage across the capacitor CH1 and total DC-link voltage of TLBC CH2 for D = 0.5.

Figure 27 .
Figure 27.Generation of pulses for the LGU switches (S1 to S6) in the DCLCHB inverter using the EPCAD technique through Xilinx ISE.

Figure 28 .
Figure 28.Generation of pulses for the LGU switches (S1 to S6) in the DCLCHB inverter using the SPWCAD technique through Xilinx ISE.

Figure 29 .
Figure 29.Generation of pulses for the PSGU switches (P1 to P4) in the DCLCHB inverter using a pulse generator through Xilinx ISE.

Figure 27 .
Figure 27.Generation of pulses for the LGU switches (S 1 to S 6 ) in the DCLCHB inverter using the EPCAD technique through Xilinx ISE.

Figure 27 .
Figure 27.Generation of pulses for the LGU switches (S1 to S6) in the DCLCHB inverter using the EPCAD technique through Xilinx ISE.

Figure 28 .
Figure 28.Generation of pulses for the LGU switches (S1 to S6) in the DCLCHB inverter using the SPWCAD technique through Xilinx ISE.

Figure 29 .
Figure 29.Generation of pulses for the PSGU switches (P1 to P4) in the DCLCHB inverter using a pulse generator through Xilinx ISE.

Figure 28 .
Figure 28.Generation of pulses for the LGU switches (S 1 to S 6 ) in the DCLCHB inverter using the SPWCAD technique through Xilinx ISE.

Figure 27 .
Figure 27.Generation of pulses for the LGU switches (S1 to S6) in the DCLCHB inverter using the EPCAD technique through Xilinx ISE.

Figure 28 .
Figure 28.Generation of pulses for the LGU switches (S1 to S6) in the DCLCHB inverter using the SPWCAD technique through Xilinx ISE.

Figure 29 .
Figure 29.Generation of pulses for the PSGU switches (P1 to P4) in the DCLCHB inverter using a pulse generator through Xilinx ISE.

Figure 29 .
Figure 29.Generation of pulses for the PSGU switches (P 1 to P 4 ) in the DCLCHB inverter using a pulse generator through Xilinx ISE.

Figure 31 .
Figure 31.THD analysis of the TLBDCLCHB inverter output using the EPCAD technique.

Figure 31 .
Figure 31.THD analysis of the TLBDCLCHB inverter output using the EPCAD technique.

Figure 31 .
Figure 31.THD analysis of the TLBDCLCHB inverter output using the EPCAD technique.

Table 1 .
Component requirements for existing and proposed boost based MLI systems.

Table 1 .
Component requirements for existing and proposed boost based MLI systems.

Table 2 .
Component requirements for existing and proposed cascade MLI systems.

Table 3 .
Switching sequence to generate seven-level output for a DCLCHB inverter.

Table 4 .
Number of conducting angles and steps in output waveform SPWCAD technique for various M i .

Table 5 .
Conducting angles of SPWCAD technique for various M i .

Table 6 .
Conducting angles, theoretical output phase voltage THD, and V rms values for a seven-level DCLCHB inverter (m = 7).