A Novel Single-switch Phase Controlled Wireless Power Transfer System

Xin Liu 1 , Nan Jin 2 , Xijun Yang 1, Khurram Hashmi 1, Dianguan Ma 1,* and Houjun Tang 1 1 Key Laboratory of Control of Power Transmission and Transformation Ministry of Education, Shanghai Jiao Tong University, 800 Dongchuan RD., Shanghai 200240, China; Liu_xin@sjtu.edu.cn (X.L.); yangxijun@sjtu.edu.cn (X.Y.); khurram_hashmi@sjtu.edu.cn (K.H.); hjtang@sjtu.edu.cn (H.T.) 2 College of Electric and Information Engineering, Zhengzhou University of Light Industry, Zhengzhou 450002, China; jinnan@zzuli.edu.cn * Correspondence: dgma@sjtu.edu.cn; Tel.: +86-138-1758-7820


Introduction
WPT techniques can realize energy conversion without physical connections.It has gained tremendous attention in both research and industry.Recently, wireless charging is the focus of study.To improve battery life time, the system has special requirements for the charging current and voltage profiles.WPT systems can realize both CC and CV power transfer modes through either primary or secondary side control.However, primary side control requires an additional communication channel [1,2].It is more simplified and straightforward to directly achieve the CC and CV power transfer modes through secondary side control.Therefore, various DC-DC converters [3][4][5][6][7][8] are installed on the receiver side for power regulation, including buck converter [4], boost converter [5,9,10], and buck-boost converter [6,11].Although DC-DC converters have simpler controls, they require additional capacitors and inductors that increase the weight, volume, and cost of the receiver.In addition, more cascaded circuits result in more losses on the DC side.To address these drawbacks, researchers propose active rectifiers on the receiver side.Active rectifiers are initially put forward to reduce the conduction losses of the diode rectifier and transfer the power bi-directionally [12][13][14][15][16][17][18][19].Recently, Phase Control (PC) method is introduced to regulate resonant currents [20][21][22][23][24][25], which can further reduce the energy consumed by parasitic resistances.
Active rectifiers proposed for WPT systems can be classified into three categories: (i) full bridge rectifier with four switches; (ii) semi-bridgeless rectifier with two switches; and (iii) single-switch rectifier.Full active bridge rectifiers are used in various applications [12][13][14][15][16][17][18][19][20][21][22][23][24][25].Four Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and four isolated driver circuits are installed on the receiver side.Short circuit may appear in the full bridge topology due to faulty operation.Such a characteristic reduces the reliability of the WPT systems, especially battery charging systems where short circuit can lead to fire and explosion.It is desirable to investigate a more cost-effective and reliable approach to achieve secondary PC.Therefore, researchers in [26][27][28] develop two-switch rectifiers for WPT systems.In [26,27], a semi-bridgeless topology with two MOSFETs is proposed, where two switches are installed on the lower side of the rectifier.Secondary PC can be achieved as well.In [28], two MOSFETs are in reverse connection and controlled by one signal.Duty ratio control is applied to regulate the power.Furthermore, researchers in [29][30][31][32][33][34][35][36] investigate single-switch rectifiers.In [29], a switch is connected in parallel with a resonant compensation capacitor.Power regulation can be achieved by tuning/detuning through this variable capacitor.However, this method makes the system deviate from optimal resonant point, which may cause an efficiency drop.In [30][31][32], a switch is connected in series with parallel resonant tank.When the switch is turned off, the receiver transfers the power only in half the period.In addition, it is difficult to obtain a stable DC voltage.In [33], an active switch is inserted into the lower phase leg of a full diode bridge.When the switch is turned on, the resonant tank is shorted in half the period and the power can be regulated by duty ratio control.In [34][35][36], a boost converter is directly connected after the diode bridge which reduces one filter capacitor.
This paper proposes a novel single-switch phase controlled receiver for WPT systems for the first time.With this method, the secondary side inductor is removed and only a small filter capacitor is added, thereby reducing the size of the receiver and lessening the number of switches used.The salient contributions of this work are: (1) The proposed methodology reduces the number of active switches and isolated driver circuits as compared to conventional phase controlled receivers.(2) An APC method is applied to this improved receiver that circumvents synchronization algorithms and additional programming.APC method regulates the power automatically, which reduces the difficulty in design and implementation.(3) Most previously discussed single-switch methods are half-controlled and use duty ratio variation.
In this work, the receiver is fully controlled and has a stronger power regulation ability as compared to conventional single-switch receivers.(4) The proposed receiver fully utilizes the SiC MOSFET to reduce switching losses while avoiding high forward voltage losses through its intrinsic diode.
This paper is divided as follows: Section 2 shows the proposed single-switch receiver and illustrates its operating modes.Then, it presents the derivations for the CC and CV power transfer modes.Section 3 elaborates the detailed implementation techniques of the proposed DPC and APC methods.In Section 4, simulations and experiments are added to validate the feasibility and effectiveness of the proposed topology and control methods.Finally, Section 5 concludes this paper.

Modeling and Analysis
This section presents mathematical modeling and analysis for the proposed WPT system.

Proposed Topology
A WPT system with the proposed single-switch receiver is shown in Figure 1.U i and U o are the DC voltages, whereas v p and v s are the primary and secondary resonant voltages.L p and L s are the Electronics 2018, 7, 281 3 of 16 primary and secondary coil inductances, which are compensated by C p and C s , respectively.S 1 -S 5 are the SiC MOSFETs, and D 1 -D 5 are the diodes.C i and C o are the filter capacitors, and R L is the load.i 1 and i 2 are the currents flowing through S 5 and D 5 , respectively.I i and I o denote the input and output DC currents.
The typical waveforms of the proposed topology are shown in Figure 2, where 2β presents the phase angle of v s .According to the current directions and paths, the receiver has six operating modes as depicted in Figure 3.
Mode 1: i s > 0, and S 5 is on.There exist two current loops on the receiver side: L s -D 1 -S 5 -D 4 -C s and C o -R L .The diode bridge is short-circuited by S 5 , and I o is supplied by C o .Thus, v s is zero.
Mode 2: i s > 0, and S 5 is turned off at the beginning of Mode 2. C o charges, and U o increases.Thus, the current loop is Mode 3: i s > 0, and S 5 is turned on at the beginning of Mode 3.Then, i s flows through S 5 and v s becomes zero.U o is supplied by C o , and it begins to decrease.The current loops are: Mode 4: S 5 remains on and v s .remains zero, whereas i s changes its direction.U o continues to decrease.The current loop of i s becomes L s -C s -D 3 -S 5 -D 2 .
Mode 5: i s < 0, and S 5 is turned off at the beginning of Mode 5. C o charges via i s , and Mode 6: i s < 0, and S 5 is turned on at the beginning of Mode 6.The current loop of i s becomes L s -C s -D 3 -S 5 -D 2 , and U o is supplied by C o again.
To minimize switching losses, a SiC MOSFET can be used.Since the forward voltage of the intrinsic diode of the SiC MOSFET is high, a SiC diode is connected in parallel to overcome the high forward voltage loss of the intrinsic diode.However, no current freewheels through S 5 in the proposed receiver, which means the SiC diode is not necessary in this application.Therefore, the proposed receiver can fully utilize the SiC MOSFET to reduce switching losses while avoiding its drawback of high forward voltage losses through its intrinsic diode.The typical waveforms of the proposed topology are shown in Figure 2, where 2β presents the phase angle of vs.According to the current directions and paths, the receiver has six operating modes as depicted in Figure 3. Mode 1: is > 0, and S5 is on.There exist two current loops on the receiver side: Ls − D1 -S5 -D4 -Cs and Co -RL.The diode bridge is short-circuited by S5, and Io is supplied by Co.Thus, vs is zero.Mode 2: is > 0, and S5 is turned off at the beginning of Mode 2. Co charges, and Uo increases.Thus, the current loop is Ls -D1 -D5 -Uo -D4 -Cs.vs is basically equal to Uo.
Mode 3: is > 0, and S5 is turned on at the beginning of Mode 3.Then, is flows through S5 and vs becomes zero.Uo is supplied by Co, and it begins to decrease.The current loops are: Ls -D1 -S5 -D4 -Cs and Co -RL.
Mode 4: S5 remains on and vs. remains zero, whereas is changes its direction.Uo continues to decrease.The current loop of is becomes Ls -Cs -D3 -S5 -D2.
Mode 5: is < 0, and S5 is turned off at the beginning of Mode 5. Co charges via is, and Uo begins to increase.The current loop is Ls -Cs -D3 -D5 -Uo-D2.vs is basically equal to -Uo.
Mode 6: is < 0, and S5 is turned on at the beginning of Mode 6.The current loop of is becomes Ls -Cs -D3 -S5 -D2, and Uo is supplied by Co again.
To minimize switching losses, a SiC MOSFET can be used.Since the forward voltage of the intrinsic diode of the SiC MOSFET is high, a SiC diode is connected in parallel to overcome the high forward voltage loss of the intrinsic diode.However, no current freewheels through S5 in the proposed receiver, which means the SiC diode is not necessary in this application.Therefore, the proposed receiver can fully utilize the SiC MOSFET to reduce switching losses while avoiding its drawback of high forward voltage losses through its intrinsic diode.

Proposed receiver Primary inverter
Resonant tank i 1  The typical waveforms of the proposed topology are shown in Figure 2, where 2β presents the phase angle of vs.According to the current directions and paths, the receiver has six operating modes as depicted in Figure 3. Mode 1: is > 0, and S5 is on.There exist two current loops on the receiver side: Ls − D1 -S5 -D4 -Cs and Co -RL.The diode bridge is short-circuited by S5, and Io is supplied by Co.Thus, vs is zero.Mode 2: is > 0, and S5 is turned off at the beginning of Mode 2. Co charges, and Uo increases.Thus, the current loop is Ls -D1 -D5 -Uo -D4 -Cs.vs is basically equal to Uo.
Mode 3: is > 0, and S5 is turned on at the beginning of Mode 3.Then, is flows through S5 and vs becomes zero.Uo is supplied by Co, and it begins to decrease.The current loops are: Ls -D1 -S5 -D4 -Cs and Co -RL.
Mode 4: S5 remains on and vs. remains zero, whereas is changes its direction.Uo continues to decrease.The current loop of is becomes Ls -Cs -D3 -S5 -D2.
Mode 5: is < 0, and S5 is turned off at the beginning of Mode 5. Co charges via is, and Uo begins to increase.The current loop is Ls -Cs -D3 -D5 -Uo-D2.vs is basically equal to -Uo.
Mode 6: is < 0, and S5 is turned on at the beginning of Mode 6.The current loop of is becomes Ls -Cs -D3 -S5 -D2, and Uo is supplied by Co again.
To minimize switching losses, a SiC MOSFET can be used.Since the forward voltage of the intrinsic diode of the SiC MOSFET is high, a SiC diode is connected in parallel to overcome the high forward voltage loss of the intrinsic diode.However, no current freewheels through S5 in the proposed receiver, which means the SiC diode is not necessary in this application.Therefore, the proposed receiver can fully utilize the SiC MOSFET to reduce switching losses while avoiding its drawback of high forward voltage losses through its intrinsic diode.

Power Regulation
The CC and CV power transfer realizations are the basic requirements for battery charging systems.This section presents the theoretical analysis of secondary side control through proposed single-switch phase-controlled receiver.
The system operates at the resonant frequency, that is Rp and Rs represent primary and secondary coil resistances, respectively.Then, the following equations are obtained according to Kirchhoff Voltage Law (KVL).
According to Fourier series and fundamental harmonic analysis [23][24][25], the root-mean-square value of vs (Vs) can be denoted as: Without considering the switching losses, the input and output powers of the rectifier are equal.
Then, Io versus Is is deduced.
According to Equation (2), is can be rewritten as Thus, Io and Uo can be approximately derived as Equations ( 8) and ( 9).

Power Regulation
The CC and CV power transfer realizations are the basic requirements for battery charging systems.This section presents the theoretical analysis of secondary side control through proposed single-switch phase-controlled receiver.
The system operates at the resonant frequency, that is R p and R s represent primary and secondary coil resistances, respectively.Then, the following equations are obtained according to Kirchhoff Voltage Law (KVL).
According to Fourier series and fundamental harmonic analysis [23][24][25], the root-mean-square value of v s (V s ) can be denoted as: Without considering the switching losses, the input and output powers of the rectifier are equal.
Then, I o versus I s is deduced.
According to Equation (2), i s can be rewritten as Thus, I o and U o can be approximately derived as Equations ( 8) and (9).
A larger β means a larger I o and U o .Therefore, β can be utilized to achieve the CC and CV power transfer modes.

Implementation Methods
This section presents implementation techniques for realizing DPC and APC with the proposed receiver in WPT system.

Digital Phase Control
The schematic of the DPC system is shown in Figure 4, where two independent Digital Signal Processors (DSPs) are installed.Digital control is widely used for various applications due to its flexibility.Since the controller should be isolated from the main circuit for safety consideration, isolated driver circuits as well as isolated power supplies are installed on primary and secondary sides.Furthermore, isolated current and voltage sensors are required on the receiver side for output electrical information feedback.To avoid power oscillations, the synchronization of secondary receiver is of essential importance.In [24], secondary synchronization is realized by utilizing the resonant voltage across C s .The synchronization circuit consists of a comparator and an isolator, as shown in Figure 4, where R h and R l are the divider resistances.The operating frequency of the receiver-side switches in the full active bridge is equal to the current frequency, whereas it is twice that frequency in the proposed receiver.Thus, the receiver is synchronized once every two periods.
Electronics 2018, 7, x FOR PEER REVIEW 5 of 16 A larger β means a larger Io and Uo.Therefore, β can be utilized to achieve the CC and CV power transfer modes.

Implementation Methods
This section presents implementation techniques for realizing DPC and APC with the proposed receiver in WPT system.The schematic of the DPC system is shown in Figure 4, where two independent Digital Signal Processors (DSPs) are installed.Digital control is widely used for various applications due to its flexibility.Since the controller should be isolated from the main circuit for safety consideration,  The schematic of the DPC system is shown in Figure 4, where two independent Digital Signal Processors (DSPs) are installed.Digital control is widely used for various applications due to its flexibility.Since the controller should be isolated from the main circuit for safety consideration, isolated driver circuits as well as isolated power supplies are installed on primary and secondary TBPRD is determined by the inverter frequency, and the comparing values produce the desired β.Afterwards, the corresponding gate drive signal generates v s in the main circuit.

Digital Phase Control
As analyzed in Section 2, a larger β brings about larger I o and U o .Therefore, the output power regulation can be achieved by changing β.The algorithm flowchart of the CC and CV power transfer modes is shown in Figure 6, where I * o and U * o are the expected current and voltage values.Power transfer mode selection is determined by one bit, referred to as "Mode", which is defined in the controller.The designer can initialize the Mode by setting it at 1 or 0 in the software code.When the Mode is 1, the receiver operates at the CC power transfer mode, otherwise, it operates at the CV power transfer mode.I o is sampled for the CC power transfer mode, and U o for the CV power transfer mode.To obtain accurate sampling values, 20 samplings of I o or U o are averaged.β ranges from 0 • to 90 • .When I o or U o is smaller than the desired value, β is increased by 0.1 • .Otherwise, β is decreased by 0.1 • .This control algorithm is simple and effective.The primary controller is turned on and the primary active bridge inverts the high frequency voltage.The frequency locking signal is generated, whereas the receiver-side controllers remain on standby and the diode rectification is used by the receiver at first.When U o reaches the threshold value, the controller is turned on.

Analog Phase Control
The DPC method can achieve good control flexibility and performance.However, the receiver requires some auxiliary circuits.To further reduce the complexity and cost of the receiver, a novel APC method is presented as follows.In full active bridge receivers, four gate drive signals should be controlled to generate v s .However, β is determined by one signal in the proposed receiver, which makes the software code realization easier.

Analog Phase Control
The DPC method can achieve good control flexibility and performance.However, the receiver requires some auxiliary circuits.To further reduce the complexity and cost of the receiver, a novel APC method is presented as follows.
The schematic of the proposed APC system is shown in Figure 7. R 1 and R 2 are the divider resistances.R 3 and R 9 are the sampling resistances.The voltage across R 3 is fed back for the CC power transfer, and the divided voltage across R 2 for the CV power transfer.Since R 3 is small, and R 4 and R 5 are used to amplify the signal.In APC system, power transfer mode selection is realized by a 2:1 switch.R 1 -R 5 should satisfy Equation (12).
U o sampling

Analog Phase Control
The DPC method can achieve good control flexibility and performance.However, the receiver requires some auxiliary circuits.To further reduce the complexity and cost of the receiver, a novel APC method is presented as follows.The schematic of the proposed APC system is shown in Figure 7. R1 and R2 are the divider resistances.R3 and R9 are the sampling resistances.The voltage across R3 is fed back for the CC power transfer, and the divided voltage across R2 for the CV power transfer.Since R3 is small, and R4 and R5 are used to amplify the signal.In APC system, power transfer mode selection is realized by a 2:1 switch.R1-R5 should satisfy Equation (12).13) and (14).Different output current and voltage can be achieved by setting U ref and R 1 -R 5 .

+ -
R 6 and C 1 act as an integrator.Their values have a great influence on the dynamic and static performances of the system.To better demonstrate this characteristic, time constant τ is defined as Equation (15).
A smaller τ brings about a faster dynamic response with a larger overshoot, whereas a larger τ corresponds to a better static performance with a slower dynamic response.
Figure 8 shows the typical waveforms of the APC receiver.When I o (or U o ) is greater than I * o (or U * o ), v 1 is greater than U ref , and the comparator generates a zero v 2 .Otherwise, a positive v 2 is produced.v 3 decreases for a positive v 2 and increases for a zero v 2 .Since v 3 is negative, an inverting amplifier is used.The ratio of R 8 versus R 7 can regulate the response characteristic.i s flows through R 9 , and the voltage drop is amplified by R 10 and R 11 , which obtains a half-wave voltage v 5 .Then, v 4 and v 5 are sent to a comparator, and they can produce the desired control signal.After passing the non-isolated driver circuit, the gate drive signal is fed to the switch.When S 5 is turned on, the receiver is short-circuited, which results in a zero v s .When S 5 is turned off, v s becomes U o or −U o .β is automatically regulated by the feedback signals.
R6 and C1 act as an integrator.Their values have a great influence on the dynamic and static performances of the system.To better demonstrate this characteristic, time constant τ is defined as Equation (15).
A smaller τ brings about a faster dynamic response with a larger overshoot, whereas a larger τ corresponds to a better static performance with a slower dynamic response.
Figure 8 shows the typical waveforms of the APC receiver.When Io (or Uo) is greater than Io * (or Uo * ), v1 is greater than Uref, and the comparator generates a zero v2.Otherwise, a positive v2 is produced.v3 decreases for a positive v2 and increases for a zero v2.Since v3 is negative, an inverting amplifier is used.The ratio of R8 versus R7 can regulate the response characteristic.is flows through R9, and the voltage drop is amplified by R10 and R11, which obtains a half-wave voltage v5.Then, v4 and v5 are sent to a comparator, and they can produce the desired control signal.After passing the non-isolated driver circuit, the gate drive signal is fed to the switch.When S5 is turned on, the receiver is shortcircuited, which results in a zero vs.When S5 is turned off, vs becomes Uo or -Uo.β is automatically regulated by the feedback signals.The CC and CV power transfer modes can be achieved through the proposed analog controller.Meanwhile, the receiver does not require synchronization techniques and additional programming.Thus, the proposed APC method significantly reduces the difficulty in implementation, the cost, volume, and weight of the receiver.The CC and CV power transfer modes can be achieved through the proposed analog controller.Meanwhile, the receiver does not require synchronization techniques and additional programming.Thus, the proposed APC method significantly reduces the difficulty in implementation, the cost, volume, and weight of the receiver.

Simulation and Experiment
Results are obtained from simulation studies in PLECS and hardware prototype experiments.Both results are presented and compared to validate the feasibility of the proposed topology and control methods.The main parameters of the WPT system are listed in Table 1.L p and L s are 150 µH and 200 µH with a coil distance of 10 cm.The primary and secondary coils are compensated by 23 nF and 17 nF resonant capacitors, respectively.The inverting frequency of the transmitter is 85 kHz.The diodes are MUR3020PT, with a low forward voltage drop of 1 V. SiC MOSFETs are SCT3030KL.Heat sinks are installed on each diode and MOSFET.

Digital Phase Control
The prototype photograph of the DPC system is shown in Figure 9. Two TMS320F28335 chips are used as the primary and secondary controllers.The transmitter inverts the DC voltage into high frequency resonant voltage v p .Then, v s is induced by the magnetic field generated by i p .Afterwards, secondary resonant current i s is rectified into DC current I o by the proposed receiver.Finally, the power is consumed by Chroma programmable AC-DC electronic load model 63803.Current and voltage sensors are installed to sample the feedback signals for power regulation.ACPL-W346 chips are used as the isolated drivers which are supplied by isolated DC-DC converter G1212S-2W.

Digital Phase Control
The prototype photograph of the DPC system is shown in Figure 9. Two TMS320F28335 chips are used as the primary and secondary controllers.The transmitter inverts the DC voltage into high frequency resonant voltage vp.Then, vs is induced by the magnetic field generated by ip.Afterwards, secondary resonant current is is rectified into DC current Io by the proposed receiver.Figure 10 shows the typical waveforms of the DPC receiver.To ensure that the signal fed to the comparator stays within a proper range, the values of the divider resistances should be configured with the power level.In this paper, the high-side resistance Rh is 2 MΩ and the low-side resistance Rl is 10 kΩ.The voltage across Cp generates the synchronization signal, and it is fed to GPIO6 of the controller.vs and is are controlled to be in phase.The desired output voltage or current is realized by regulating β.
Figure 11a,b shows the simulated and experimental CC power transfer results by DPC.The reference current is set at 2 A, and RL changes from 25 Ω to 50 Ω.When RL is 25 Ω, the simulated and experimental values of β are 27.8° and 27.4°, respectively.The simulated and experimental output currents are 2.00 A and 1.96 A, which correspond to 83.3% and 80.8% DC-to-DC efficiencies, respectively.When RL is 50 Ω, the simulated and experimental values of β are 28.6° and 27.5°, respectively.The simulated and experimental output currents are 1.99A and 1.97 A, with DC-to-DC efficiencies of 90.0% and 86.2%, respectively.Io keeps unchanged against load variations.Figure 10 shows the typical waveforms of the DPC receiver.To ensure that the signal fed to the comparator stays within a proper range, the values of the divider resistances should be configured with the power level.In this paper, the high-side resistance R h is 2 MΩ and the low-side resistance R l is 10 kΩ.The voltage across C p generates the synchronization signal, and it is fed to GPIO6 of the controller.v s and i s are controlled to be in phase.The desired output voltage or current is realized by regulating β.

Analog Phase Control
A photograph of the APC receiver is shown in Figure 13.U ref is set at 2.5 V.The divider resistances R 1 and R 2 are 91 kΩ and 2.2 kΩ, respectively.The sampling resistances R 3 and R 9 are 10 mΩ.R 4 and R 5 are 0.5 kΩ (1 kΩ//1 kΩ) and 62 kΩ, respectively.The ratios of R 7 versus R 8 and R 11 versus R 10 are 1 and 22, which ensures v 4 and v 5 falling within proper ranges.TLV3502 and THS4062 are used as the comparator and the operational amplifier, respectively.The configurations of the simulations are identical to the experimental prototype.
Figure 14 shows the logical waveforms of the APC receiver, including v 4 , v 5 , v 6 , and v s .Regulation circuits are installed on the main circuit.v 4 and v 5 are sent to TLV3502 which generates the control signal.When v 5 is smaller than v 4 , v 6 becomes high level, and S 5 is turned on.Otherwise, v 6 becomes low level, and S 5 is turned off.Small oscillations appear in v 6 , which should be interferences caused by the switching processes.When I o or U o is smaller than the expected value, v 4 decreases which brings about a larger β.Otherwise, v 4 increases, and a smaller β is produced.
by the switching processes.When Io or Uo is smaller than the expected value, v4 decreases which brings about a larger β.Otherwise, v4 increases, and a smaller β is produced.
Figure 15 shows the typical waveforms of the APC receiver.In simulations, vs is in phase with is.However, in experiments, it takes some time for the signal to go through the operational amplifier, the comparator, the DSP, and the driver circuit.This time delay results in vs lagging is by some degrees.High performance devices can reduce this time delay.by the switching processes.When Io or Uo is smaller than the expected value, v4 decreases which brings about a larger β.Otherwise, v4 increases, and a smaller β is produced.
Figure 15 shows the typical waveforms of the APC receiver.In simulations, vs is in phase with is.However, in experiments, it takes some time for the signal to go through the operational amplifier, the comparator, the DSP, and the driver circuit.This time delay results in vs lagging is by some degrees.High performance devices can reduce this time delay.Figure 15 shows the typical waveforms of the APC receiver.In simulations, v s is in phase with i s .However, in experiments, it takes some time for the signal to go through the operational amplifier, the comparator, the DSP, and the driver circuit.This time delay results in v s lagging i s by some degrees.High performance devices can reduce this time delay.The simulated and experimental DC-to-DC efficiencies are 82.5% and 78.2%.When R L is 50 Ω, the simulated and experimental output currents are 1.99A and 1.94 A, which correspond to 89.5% and 85.2% DC-to-DC efficiencies, respectively.In the CC mode, I o maintains at the desired 2 A against load variations.When RL is 25 Ω, the simulated and experimental output currents are 1.99A and 1.98 A, respectively.The simulated and experimental DC-to-DC efficiencies are 82.5% and 78.2%.When RL is 50 Ω, the simulated and experimental output currents are 1.99A and 1.94 A, which correspond to 89.5% and 85.2% DC-to-DC efficiencies, respectively.In the CC mode, Io maintains at the desired 2 A against load variations.Figure 17a,b shows the simulated and experimental results of the CV power transfer by APC.The reference voltage is set at 100 V.When RL is 25 Ω, the simulated and experimental output voltages are 99.7 V and 103.7 V, whose DC-to-DC efficiencies are 92.2% and 88.9%, respectively.When RL is 50 Ω, the simulated and experimental output voltages are 99.5 V and 104.6 V, respectively.The overall simulated and experimental efficiencies are 89.4% and 84.7%, respectively.In the CV mode, Uo remains unchanged against load variations.
Since simulations are closer to an ideal system than experiments, their efficiencies are higher than experimental ones.However, the dynamic and static performance are generally the same, which verifies the feasibility of the APC system.

Comparisons between Proposed Methods
Figure 18 shows the photograph of the two proposed controllers.The DPC controller is 9.0 cm × 9.0 cm × 2.7 cm, whereas the APC controller is only 2.4 cm × 2.0 cm × 0.3 cm.The analog controller is much smaller than the digital one.The volume, weight, and cost of the analog receiver can be significantly reduced.Since simulations are closer to an ideal system than experiments, their efficiencies are higher than experimental ones.However, the dynamic and static performance are generally the same, which verifies the feasibility of the APC system.

Comparisons between Proposed Methods
Figure 18 shows the photograph of the two proposed controllers.The DPC controller is 9.0 cm × 9.0 cm × 2.7 cm, whereas the APC controller is only 2.4 cm × 2.0 cm × 0.3 cm.The analog controller is much smaller than the digital one.The volume, weight, and cost of the analog receiver can be significantly reduced.

Comparisons between Proposed Methods
Figure 18 shows the photograph of the two proposed controllers.The DPC controller is 9.0 cm × 9.0 cm × 2.7 cm, whereas the APC controller is only 2.4 cm × 2.0 cm × 0.3 cm.The analog controller is much smaller than the digital one.The volume, weight, and cost of the analog receiver can be significantly reduced.Although both the DPC and APC methods can realize the CC and CV power transfer modes, they differ in some aspects.Table 2 compares the differences of the two proposed methods.The DPC system is more complex: it requires a DSP controller, isolated power supplies and driver circuits, current and voltage sensors, and the synchronization circuit.However, the DPC system can eliminate the time delay caused by the regulation circuit and avoid additional power losses of the sampling and divider resistances in the APC receiver.The highest measured experimental efficiency of the APC system is 89.4%, whereas it is 91.4% in the DPC system.Thus, the DPC receiver contributes to a higher performance compared to the APC receiver.Furthermore, it is easier to change the received power through the software code as in the DPC system than changing the regulation resistances as in the APC system, i.e., the DPC system has a greater flexibility than the APC system.Conversely, the APC receiver is simpler since it does not require synchronization algorithms and dedicated programming.In addition, it needs fewer auxiliary devices, i.e., isolated power supplies and expensive sensors are not needed, as well as has a smaller printed circuit board layout.This makes the analog receiver lighter, more cost-effective, and compact.Although both the DPC and APC methods can realize the CC and CV power transfer modes, they differ in some aspects.Table 2 compares the differences of the two proposed methods.The DPC system is more complex: it requires a DSP controller, isolated power supplies and driver circuits, current and voltage sensors, and the synchronization circuit.However, the DPC system can eliminate the time delay caused by the regulation circuit and avoid additional power losses of the sampling and divider resistances in the APC receiver.The highest measured experimental efficiency of the APC system is 89.4%, whereas it is 91.4% in the DPC system.Thus, the DPC receiver contributes to a higher performance compared to the APC receiver.Furthermore, it is easier to change the received power through the software code as in the DPC system than changing the regulation resistances as in the APC system, i.e., the DPC system has a greater flexibility than the APC system.Conversely, the APC receiver is simpler since it does not require synchronization algorithms and dedicated programming.In addition, it needs fewer auxiliary devices, i.e., isolated power supplies and expensive sensors are not needed, as well as has a smaller printed circuit board layout.This makes the analog receiver lighter, more cost-effective, and compact.

DPC APC
Compared to DC-DC converters used in the WPT systems, the proposed receiver advances in two aspects.Firstly, fewer capacitors and no inductors are required in the proposed receiver.It can reduce the volume and weight of the receiver.Secondly, AC-DC and DC-DC conversions are achieved simultaneously by the proposed receiver.Fewer cascaded circuits, therefore, bring about a higher overall efficiency.
Compared to full bridge and semi-bridgeless topologies, the proposed receiver advances in two aspects: Firstly, the proposed receiver is more cost-effective since the number of SiC MOSFETs and driver circuits used in the proposed receiver have been reduced by 75% as compared to full bridge topology, and 50% as compared to semi-bridgeless topology.In addition, a SiC diode, aiming to reduce high forward voltage, is not needed in the proposed receiver.Therefore, the cost reduction can be significant.Secondly, the proposed receiver has a higher reliability.Dead time is required to avoid short circuit in full bridge applications, whereas the proposed receiver gets rid of short circuit due to the reverse blocking of the diode.
Most reported single-switch receivers are half-controlled, which may fail to achieve the CC and CV power transfer modes.Furthermore, the receivers require a large capacitor to stabilize the output voltage due to the usage of duty ratio control.However, the proposed receiver is full-controlled and has a strong power regulation ability.Owing to the utilization of PC, a small filter capacitor is needed in the proposed receiver.

Conclusions
This paper presents a novel single-switch phase controlled active rectifier as receiver for WPT systems.Improved DPC and APC methods are proposed based on the receiver topology to achieve effective CC and CV power transfer modes.The proposed method prevents forward voltage losses in SiC switches and accidental shoot through states with improved switching patterns.The system is easy to implement, has a lower cost, smaller volume, lighter weight, and a higher reliability than conventional phase controlled receivers.Detailed analyses of the operating modes and implementation techniques are presented.Simulated and experimental results of a 400-W WPT system are included which show more than 91% overall efficiency and thereby demonstrate the feasibility of the proposed system.

Figure 1 .
Figure 1.WPT system with proposed single-switch receiver.

Figure 5 Figure 4 .Figure 5 .
Figure 5 shows the typical synchronization waveforms.The comparator turns the divided sinusoidal voltage into a square-wave synchronization signal.After passing a digital isolator, it is sent to the synchronization port of the DSP controller.TBPRD, CMPA, and CMPB are the time base period and comparing values of the reserved registers of the controller, respectively.The 0 and TBPRD shown in Figure 5 are the minimum and maximum values of the counter of the controller, i.e., CMPA and CMPB fall within the range of [0, TBPRD].When the counter reaches CMPA, S 5 is turned off.When the counter reaches CMPB, S 5 is turned on.The relationships among TBPRD, CMPA, CMPB, and β are shown in Equations (10) and (11).CMPA = 180 − β 180 TBPRD (10) CMPB = β 180 TBPRD (11)

Figure 7 .
Figure 7. Schematic of APC system.U ref is a reference voltage.The relationships among U * o , I * o , and U ref are given in Equations (13) and (14).Different output current and voltage can be achieved by setting U ref and R 1 -R 5 .

Electronics 2018, 7 ,
Figure 12a,b shows the simulated and experimental CV power transfer results by DPC.The reference voltage is set at 100 V.When RL is 25 Ω, the simulated and experimental values of β are 73.9° and 73.5°, which produce 100.0V and 101.2 V output voltages, respectively.The simulated and experimental efficiencies are 93.1% and 91.4%, respectively.When RL is 50 Ω, the simulated and experimental values of β become 27.7° and 28.1°, respectively.The corresponding output voltages are 99.5 V and 100.5 V, with DC-to-DC efficiencies of 90.0% and 85.8%, respectively.During load variations, Uo remains at the desired level by regulating β accordingly.

IFigure 11 .
Figure 11.Simulated and experimental CC power transfer results of DPC system: (a) simulated; and

Figure
Figure 11a,b shows the simulated and experimental CC power transfer results by DPC.The reference current is set at 2 A, and R L changes from 25 Ω to 50 Ω.When R L is 25 Ω, the simulated and experimental values of β are 27.8 • and 27.4 • , respectively.The simulated and experimental output currents are 2.00 A and 1.96 A, which correspond to 83.3% and 80.8% DC-to-DC efficiencies, respectively.When R L is 50 Ω, the simulated and experimental values of β are 28.6 • and 27.5 • , respectively.The simulated and experimental output currents are 1.99A and 1.97 A, with DC-to-DC efficiencies of 90.0% and 86.2%, respectively.I o keeps unchanged against load variations.

Figure 11 .
Figure 11.Simulated and experimental CC power transfer results of DPC system: (a) simulated; and (b) experimental.Io, output current (blue lines); Uo, output voltage (green lines).

Figure 12 .
Figure 12.Simulated and experimental CV power transfer results of DPC system: (a) simulated; and (b) experimental.Io, output current (blue lines); Uo, output voltage (yellow lines).

Figure 11 .
Figure 11.Simulated and experimental CC power transfer results of DPC system: (a) simulated; and (b) experimental.I o , output current (blue lines); U o , output voltage (green lines).

Figure
Figure 12a,b shows the simulated and experimental CV power transfer results by DPC.The reference voltage is set at 100 V.When R L is 25 Ω, the simulated and experimental values of β are 73.9 • and 73.5 • , which produce 100.0V and 101.2 V output voltages, respectively.The simulated and experimental efficiencies are 93.1% and 91.4%, respectively.When R L is 50 Ω, the simulated and experimental values of β become 27.7 • and 28.1 • , respectively.The corresponding output voltages are 99.5 V and 100.5 V, with DC-to-DC efficiencies of 90.0% and 85.8%, respectively.During load variations, U o remains at the desired level by regulating β accordingly.

Figure 11 .
Figure 11.Simulated and experimental CC power transfer results of DPC system: (a) simulated; and (b) experimental.Io, output current (blue lines); Uo, output voltage (green lines).

Figure 12 .
Figure 12.Simulated and experimental CV power transfer results of DPC system: (a) simulated; and (b) experimental.Io, output current (blue lines); Uo, output voltage (yellow lines).

Figure 12 .
Figure 12.Simulated and experimental CV power transfer results of DPC system: (a) simulated; and (b) experimental.I o , output current (blue lines); U o , output voltage (yellow lines).

Figure
Figure 16a,b shows the simulated and experimental results of the CC power transfer by APC.When RL is 25 Ω, the simulated and experimental output currents are 1.99A and 1.98 A, respectively.The simulated and experimental DC-to-DC efficiencies are 82.5% and 78.2%.When RL is 50 Ω, the simulated and experimental output currents are 1.99A and 1.94 A, which correspond to 89.5% and 85.2% DC-to-DC efficiencies, respectively.In the CC mode, Io maintains at the desired 2 A against load variations.

Figure
Figure 16a,b shows the simulated and experimental results of the CC power transfer by APC.When R L is 25 Ω, the simulated and experimental output currents are 1.99A and 1.98 A, respectively.

Figure
Figure16a,b shows the simulated and experimental results of the CC power transfer by APC.When RL is 25 Ω, the simulated and experimental output currents are 1.99A and 1.98 A, respectively.The simulated and experimental DC-to-DC efficiencies are 82.5% and 78.2%.When RL is 50 Ω, the simulated and experimental output currents are 1.99A and 1.94 A, which correspond to 89.5% and 85.2% DC-to-DC efficiencies, respectively.In the CC mode, Io maintains at the desired 2 A against load variations.

Figure 16 .
Figure 16.Simulated and experimental CC power transfer results of APC system: (a) simulated; and (b) experimental.Io, output current (blue lines); Uo, output voltage (green lines).

Figure 16 .
Figure 16.Simulated and experimental CC power transfer results of APC system: (a) simulated; and (b) experimental.I o , output current (blue lines); U o , output voltage (green lines).

Figure 16 TimeFigure 17 .
Figure 17a,b shows the simulated and experimental results of the CV power transfer by APC.The reference voltage is set at 100 V.When R L is 25 Ω, the simulated and experimental output voltages are 99.7 V and 103.7 V, whose DC-to-DC efficiencies are 92.2% and 88.9%, respectively.When R L is 50 Ω, the simulated and experimental output voltages are 99.5 V and 104.6 V, respectively.The overall simulated and experimental efficiencies are 89.4% and 84.7%, respectively.In the CV mode, U o remains unchanged against load variations.Electronics 2018, 7, x FOR PEER REVIEW 13 of 16

Figure 17 .
Figure 17.Simulated and experimental CV power transfer results of APC system: (a) simulated; and (b) experimental.I o , output current (blue lines); U o , output voltage (green lines).

Figure 18 .
Figure 18.Photograph of two proposed controllers.

Figure 18 .
Figure 18.Photograph of two proposed controllers.
Electronics 2018, 7, x FOR PEER REVIEW 3 of 16 the SiC MOSFETs, and D1-D5 are the diodes.Ci and Co are the filter capacitors, and RL is the load.i1 and i2 are the currents flowing through S5 and D5, respectively.Ii and Io denote the input and output DC currents.
Typical waveforms of proposed receiver.S 5 , gate drive signal (blue line); i 1 , current flowing through MOSFET (yellow line); i 2 , current flowing through D 5 (light green line); i s , secondary resonant current (orange line); v s , secondary resonant voltage (black line).

Table 1 .
Main parameters of WPT system.

Table 2 .
Comparisons between DPC and APC.