Active EMI Reduction Using Chaotic Modulation in a Buck Converter with Relaxed Output LC Filter

: DC-DC buck converters are widely used in portable applications because of their high power efﬁciency. However, their inherent fast switching releases electromagnetic emissions, making them prominent sources of electromagnetic interference (EMI). This paper proposes a voltage-controlled buck converter that reduces EMI by using a chaotic pulse-width modulation (PWM) technique based on a chaotic triangular ramp generator. The chaotic triangular ramp generator is constructed from a simple on-chip chaotic circuit linked with a symmetrically triangular ramp circuit. The proposed converter can thus operate in the chaotic mode reducing the EMI without requiring any EMI ﬁlters. Additionally, using the triangular ramp signal can relax the requirement for a large LC output ﬁlter in chaotic mode. The effectiveness of the proposed scheme was experimentally veriﬁed with a chaotic triangular ramp generator embedded in a voltage-mode controller buck converter using a 0.18 µ m Complementary Metal Oxide Semiconductor (CMOS) process. The measurement results from a prototype showed that the EMI improvement from the proposed scheme is approximately 14.53 dB at the fundamental switching frequency with respect to the standard ﬁxed-frequency PWM reference case.


Introduction
The size of portable/wearable electronic devices is being decreased by integrating circuits, such as analog circuits, high-speed digital circuits, high-speed memories, RF circuits, and antennas, into a single system-on-chip (SoC) or system-in-package (SiP) [1].It is desirable that these devices be small and light-weight, and have a long battery life.Because of their high power conversion efficiency, switched-mode DC-DC converters are widely used in portable electronic devices [2].However, the high periodical switching frequency of DC-DC converters produces switching noise, which leads to spectrum noise tones at the fundamental switching frequency and its harmonics, causing serious EMI problems.Those problems are particularly serious in SoC/SiP applications that include sensitive blocks, especially RF or sensor circuits [3,4].
Several a posteriori solutions have been proposed to reduce the EMI of DC-DC converters.The work in [5] found that the printed circuit board (PCB) layout has a great effect on the EMI problem and proposed a method of PCB layout optimization to reduce EMI.The research in [6] presented a method to reduce ringing EMI noise by using a passive loss-less snubber cell.An EMI filter is also a common approach to solving the EMI problem [7].Those schemes, however, need extra Motivated by all those concerns, we here propose a dual-mode PWM/pulse-frequency modulation (PFM) voltage-controlled buck converter with EMI reduction under chaotic mode operation.The proposed solution achieves a significant EMI reduction and mitigates the aforementioned shortcomings of previous works.First, we propose a simple and fully on-chip CMOS chaos generator associated with a strict N-shaped chaos map to generate controllable chaotic signals.A strictly mathematical model for the proposed chaos map circuit is derived via the stroboscopic sampling method, and its chaotic behaviors are deeply analyzed via the Lyapunov exponent theory and a bifurcation diagram.Second, we design a symmetrical triangular ramp generator to work with the chaos-generator to form a chaotic ramp generator for EMI reduction.Finally, we design, fabricate, and test a prototype implementation of the dual-mode PWM/PFM buck converter with the chaotic triangular ramp generator using a 0.18 µm CMOS process.The result measured from the prototype shows an EMI improvement of approximately 14.53 dB with respect to the standard PWM reference case, while maintaining a reasonable output ripple magnitude.This proposed scheme can be applied to any voltage mode-controlled converter and has a feature that enables the user to tune a single converter to various electromagnetic compatibility norms.
The rest of this paper is organized as follows: in Section 2, the concept for the EMI-improved SiP buck converter and the requirements that affect the selection of the ramp generator for EMI reduction are presented.The section then deals with the implementation of the proposed chaotic circuit and the chaotic ramp generator.The simulation results are presented and discussed in Section 3, and the experimental results and EMI comparison with other state-of-the-art schemes are presented in Section 4. Finally, Section 5 concludes this research work.

SiP Dual-Mode PWM/PFM Buck Converter with Chaos-Based EMI Reduction Scheme
Buck converters are indispensable in most battery-powered devices due to their simple power conversion step and high power efficiency.To maintain high power efficiency over a wide range of load currents, dual-mode PWM/PFM buck converters are widely used [19,20].Figure 1 shows a simplified schematic diagram of our EMI-improved buck converter, along with the concept for a SiP buck converter powered by a battery represented by a voltage source (VBAT).The buck converter is controlled by a PWM/PFM controller to turn ON/OFF the high-side and low-side switches (HSW/LSW) with non-overlapping pulses CPWMP/CPWMN.To eliminate the conduction loss when the converter enters low load conditions, a comparator is utilized to output a zero-current detection (ZCD) signal to turn off the LSW by comparing the switching node voltage (VSW) and the ground.The bandgap reference (BGR) circuit outputs a reference level of 1.2 V to regulate the output voltage of the converter.Also, in the block diagram, (EA) represents the error amplifier, and equivalent series resistance (ESR) and direct current resistance (DCR) represent the parasitic resistances inside the inductor and capacitor of the LC filter, respectively.This work presents a DC-DC buck converter that features an automatic mode change between PWM and PFM depending on the load current level.The corresponding output to load is in the range from 50 mA to 500 mA.When the load current is higher than 200 mA, the converter operates in PWM mode.When the load current is lower than 200 mA, the converter automatically switches into PFM mode, in which the power stage operates intermittently, based on the load demand.In PFM mode, the switching activity is reduced to minimize the switching loss and maintain the high power efficiency of the converter.Figure 2 shows the proposed scheme for generating a chaotic PWM signal for EMI reduction in a type-III compensation network.Type-III compensation is normally used for its optimized loop bandwidth and fast transient response in a voltage-mode-controlled converter that operates in continuous conduction mode (CCM) mode, as compared to type-I and type-II counterparts [21].In this scheme, a fully on-chip N-shaped chaos generator circuit is proposed.Additionally, a new design for a symmetrically triangular ramp generator is implemented.The chaotic output of the N-shaped chaos generator (VChaos) is applied to control the triangular ramp generator (to VH or VBR) and generate a chaotic triangular signal (VCTR).The VCTR signal is then compared with the slow-varying signal at the output (VEA) of the error amplifier to generate the CPWM to control the high side switch (HSW) and low side switch (LSW) power switches.In chaotic operation mode, the switching period, TSW, varies chaotically, and the duty cycle also changes from cycle to cycle.However, the average duty cycle is constant, which means the output voltage follows the pre-determined value as expected.The inductor current and output voltage are also chaotic, so their associated spectra can spread over a certain frequency range.In this way, the EMI is significantly reduced using the characteristics of the broadband frequency spectrum in the chaotic signal.Most importantly, the scheme proposed here modulates the switching frequency (FSW) continuously in a defined range.This is equivalent to hopping among an infinite set of switching frequencies, which results in the full elimination of the peaks in the power spectrum present in the standard fixed-frequency PWM mode.Therefore, EMI reduction can be higher than that offered by previous solutions [17,18].Figure 2 shows the proposed scheme for generating a chaotic PWM signal for EMI reduction in a type-III compensation network.Type-III compensation is normally used for its optimized loop bandwidth and fast transient response in a voltage-mode-controlled converter that operates in continuous conduction mode (CCM) mode, as compared to type-I and type-II counterparts [21].In this scheme, a fully on-chip N-shaped chaos generator circuit is proposed.Additionally, a new design for a symmetrically triangular ramp generator is implemented.The chaotic output of the N-shaped chaos generator (V Chaos ) is applied to control the triangular ramp generator (to V H or V BR ) and generate a chaotic triangular signal (V CTR ).The V CTR signal is then compared with the slow-varying signal at the output (V EA ) of the error amplifier to generate the CPWM to control the high side switch (HSW) and low side switch (LSW) power switches.In chaotic operation mode, the switching period, T SW , varies chaotically, and the duty cycle also changes from cycle to cycle.However, the average duty cycle is constant, which means the output voltage follows the pre-determined value as expected.The inductor current and output voltage are also chaotic, so their associated spectra can spread over a certain frequency range.In this way, the EMI is significantly reduced using the characteristics of the broadband frequency spectrum in the chaotic signal.Most importantly, the scheme proposed here modulates the switching frequency (F SW ) continuously in a defined range.This is equivalent to hopping among an infinite set of switching frequencies, which results in the full elimination of the peaks in the power spectrum present in the standard fixed-frequency PWM mode.Therefore, EMI reduction can be higher than that offered by previous solutions [17,18].As described in the previous sections, EMI reduction via the spread-spectrum technique is always achieved at the cost of a performance reduction in the buck converter, including: (1) an increase in the output voltage ripple; (2) a increase in inductor current ripple; and (3) a reduction in power efficiency.However, those negative side-effects have often been neglected in the literature [16][17][18].All of those factors require an increase in the size of passive LC output filter [8,22].However, in the design of SiP buck converters, a large LC is not recommended, because the space inside the package is limited.This work mitigates those negative side-effects of the spread-spectrum technique by using a ramp generator to generate a triangular signal instead of a sawtooth.The triangular signal mitigates the ripple of the inductor current, thereby relaxing the requirement for large LC output filter.The overall specifications of our DC-DC converter are listed in Table 1.The details of the implementation of the proposed scheme are explained and discussed in Sections 2.2 and 2.3 below.

Fully Integrated On-Chip Chaos Generator with N-Shaped Map
Chaotic sources have previously been proposed as a cheap replacement for a random signal in the spread-spectrum technique [23].The chaotic signal plays a key role in the distribution of harmonics when a converter operates in the chaotic mode.So far, several CMOS chaos generators have been reported [23][24][25].Those circuits, however, are not completely straightforward to design due to their lack of governing models [23], non-robust chaos with regard to variable circuit parameters [24], bulk, low frequency, and high power requirements [25].
In this section, a new, fully integrated on-chip, CMOS chaos generator is presented with its associated mathematical chaos map.The chaos map model can be strictly derived from the circuit operation, thus making the analysis and design simple and accurate.Because the chaos exists in a As described in the previous sections, EMI reduction via the spread-spectrum technique is always achieved at the cost of a performance reduction in the buck converter, including: (1) an increase in the output voltage ripple; (2) a increase in inductor current ripple; and (3) a reduction in power efficiency.However, those negative side-effects have often been neglected in the literature [16][17][18].All of those factors require an increase in the size of passive LC output filter [8,22].However, in the design of SiP buck converters, a large LC is not recommended, because the space inside the package is limited.This work mitigates those negative side-effects of the spread-spectrum technique by using a ramp generator to generate a triangular signal instead of a sawtooth.The triangular signal mitigates the ripple of the inductor current, thereby relaxing the requirement for large LC output filter.The overall specifications of our DC-DC converter are listed in Table 1.The details of the implementation of the proposed scheme are explained and discussed in Sections 2.2 and 2.3 below.

Fully Integrated On-Chip Chaos Generator with N-Shaped Map
Chaotic sources have previously been proposed as a cheap replacement for a random signal in the spread-spectrum technique [23].The chaotic signal plays a key role in the distribution of harmonics when a converter operates in the chaotic mode.So far, several CMOS chaos generators have been reported [23][24][25].Those circuits, however, are not completely straightforward to design due to their lack of governing models [23], non-robust chaos with regard to variable circuit parameters [24], bulk, low frequency, and high power requirements [25].
In this section, a new, fully integrated on-chip, CMOS chaos generator is presented with its associated mathematical chaos map.The chaos map model can be strictly derived from the circuit operation, thus making the analysis and design simple and accurate.Because the chaos exists in a wide continuous range, the chaos robustness with respect to the unavoidable error introduced by physical variations in circuit devices can be significantly relaxed.Also, the compact design and low power consumption of the proposed chaos generator make it a good pseudo-random source.To achieve EMI reduction in the DC-DC buck converter, the output of the N-shaped chaos generator is injected into a triangular ramp generator to construct a chaotic ramp generator as explained in detail in Section 2.3.

N-Shaped Chaos Generator
For the simplicity of the analysis, the proposed N-shaped chaos generator (CG) is simplified and shown in Figure 3.The circuit consists of one capacitor C that is either charged or discharged through two current sources/sinks (I 1 and I 2 ), respectively; the remaining part contains a controller with two comparators, two SR latches, one AND gate, one XOR gate, and one SPDT (single pole double through) switch.In the proposed chaos generator, the only state variable is the capacitor voltage v(t).
Electronics 2018, 7, x FOR PEER REVIEW 6 of 25 wide continuous range, the chaos robustness with respect to the unavoidable error introduced by physical variations in circuit devices can be significantly relaxed.Also, the compact design and low power consumption of the proposed chaos generator make it a good pseudo-random source.To achieve EMI reduction in the DC-DC buck converter, the output of the N-shaped chaos generator is injected into a triangular ramp generator to construct a chaotic ramp generator as explained in detail in Section 2.3.

N-Shaped Chaos Generator
For the simplicity of the analysis, the proposed N-shaped chaos generator (CG) is simplified and shown in Figure 3.The circuit consists of one capacitor C that is either charged or discharged through two current sources/sinks (I1 and I2), respectively; the remaining part contains a controller with two comparators, two SR latches, one AND gate, one XOR gate, and one SPDT (single pole double through) switch.In the proposed chaos generator, the only state variable is the capacitor voltage v(t).The operation of the chaos generator can be represented by a finite state machine (FSM), as shown in Figure 4a.The state machines S1 and S3 correspond to the charging of capacitor C at every rising edge of the clock (CK) or when v(t) reaches the upper limit VHC; the state S2 corresponds to its discharging when v(t) reaches the low limit (VLC).The dynamics of the proposed chaotic circuit can be represented by a 1-D piece-wise map, a so-called stroboscopic map.Assuming that at tH, the capacitor voltage reaches VH, which triggers the control signal Vctrl to be HIGH (Q = 1), capacitor C is discharged through I2 as follows: Also, at the beginning of the next period (tk), Vctr is triggered to be LOW (Q = 0) by the clock signal, and capacitor C is charged by I1: The operation of the chaos generator can be represented by a finite state machine (FSM), as shown in Figure 4a.The state machines S1 and S3 correspond to the charging of capacitor C at every rising edge of the clock (CK) or when v(t) reaches the upper limit V HC ; the state S2 corresponds to its discharging when v(t) reaches the low limit (V LC ).The dynamics of the proposed chaotic circuit can be represented by a 1-D piece-wise map, a so-called stroboscopic map.Assuming that at t H , the capacitor voltage reaches V H , which triggers the control signal V ctrl to be HIGH (Q = 1), capacitor C is discharged through I 2 as follows: Also, at the beginning of the next period (t k ), V ctr is triggered to be LOW (Q = 0) by the clock signal, and capacitor C is charged by I 1 : The 3 possibilities that the FSM can evolve depend on the value of state variable v(t) at tk.First, the state space is separated into 2 sub-spaces (R1 and R2 + R3), depending on boundary condition Vb1, which is defined as the voltage level at which the capacitor voltage is charged from VLC to Vb1 within one clock cycle T. Vb1 is calculated from discharging Equation (2) as follows: • Sub space R1: At tk, if Vk < Vb1, the capacitor will continue charging on the next clock cycle as shown in Figure 4b, corresponding to FSM S1.However, if Vk > Vb1, the subspace higher than Vb1 can be divided into 2 other sub spaces, R2 and R3, depending on a second boundary condition, Vb2.

•
Sub space R2: The capacitor continues charging until v(t) reaches VHC and then discharge for the time durations ta and tb, respectively.Figure 4c shows the representative waveform for this case with the charging period ta and discharging period tb, which can be deduced from Equations ( 1) and ( 2): ta = I1/C × (VHC − Vk); tb = T − ta =T −I1/C × (VHC − Vk).For this case, ta + tb = T.

•
Sub space R3: The capacitor continues charging until v(t) reaches VHC, then it discharges to VLC for the periods ta, tb, and tc, as shown in Figure 4d.In this case, ta + tb < T; therefore, tc can be calculated as tc = T − ta − tb = T − I1/C × (VHC − Vk) − C/I2 (VHC − VLC).In this case, tb is different from before and can be calculated using the discharging equation VLC = VHC − I2/C × tb.The second boundary condition can be derived by the setup tc = 0: The 3 possibilities that the FSM can evolve depend on the value of state variable v(t) at t k .First, the state space is separated into 2 sub-spaces (R 1 and R 2 + R 3 ), depending on boundary condition V b1 , which is defined as the voltage level at which the capacitor voltage is charged from V LC to V b1 within one clock cycle T. V b1 is calculated from discharging Equation (2) as follows: • Sub space R1: At t k , if V k < V b1 , the capacitor will continue charging on the next clock cycle as shown in Figure 4b, corresponding to FSM S 1 .However, if V k > V b1 , the subspace higher than V b1 can be divided into 2 other sub spaces, R 2 and R 3 , depending on a second boundary condition, V b2 .

•
Sub space R2: The capacitor continues charging until v(t) reaches V HC and then discharge for the time durations t a and t b , respectively.Figure 4c shows the representative waveform for this case with the charging period t a and discharging period t b , which can be deduced from Equations ( 1) and (2): For this case, t a + t b = T.

•
Sub space R3: The capacitor continues charging until v(t) reaches V HC , then it discharges to V LC for the periods t a , t b , and t c , as shown in Figure 4d.In this case, t a + t b < T; therefore, t c can be calculated as In this case, t b is different from before and can be calculated using the discharging equation V LC = V HC − I 2 /C × t b .The second boundary condition can be derived by the setup t c = 0: Now, the N-shaped map of the chaos generator that relates the value of state variable v(t) at every clock instant can be written as follows: Furthermore, that N-shaped map can also be normalized and parametrized: Thus, the normalized chaos map of the proposed chaos generator can be presented as:

Dynamical Analysis of the Chaos Map
Before implementing the chaos generator at the circuit level, the proposed mathematical model for the chaos generator is realized to find the range of system parameters at which the circuit outputs chaotic signal.The dynamic behavior of a chaotic system can be qualitatively studied through Lyapunov exponents.The Lyapunov exponent of the N-shaped map is theoretically calculated as follows [26]: where f'(.) is the derivative of the chaotic map f (.) and can be derived as: Hence, the Lyapunov exponent is calculated as follows: where n is the number of x points use in the calculation, i, j, k are the number of times that x belongs to three ranges [0, x b1 ], [x b1 , x b2 ], and [x b2 , 1], respectively.According to Equation ( 7), when T 2 /T 1 > 1 and λ > 0, the map produces periodic doubling bifurcation; in other words, a chaotic signal is generated [26].Otherwise, if T 2 /T 1 <1 and λ < 0, the system output has a periodic state or converges to a stable point.The chaotic dynamics can also be observed via the bifurcation diagram.For example, when T 1 = 0.5 and T 2 is gradually increased from zero, the bifurcation diagram appears as shown in Figure 5, from which the dynamic behaviors of the point, periodicity, and chaos (dense area) can be observed.The bifurcation diagram also highlights the robustness of the chaos generation from the map versus the system parameter (T 2 ); there is no intermittent-periodic window inside the bifurcation diagram, unlike in previously reported work [16].The circuit parameters for designing the N-shaped chaos generator in the next section can be selected easily based on the bifurcation diagram shown in Figure 5.The dynamics behaviors of the chaotic map can be further examined in another reported work [27].
the point, periodicity, and chaos (dense area) can be observed.The bifurcation diagram also highlights the robustness of the chaos generation from the map versus the system parameter (T2); there is no intermittent-periodic window inside the bifurcation diagram, unlike in previously reported work [16].The circuit parameters for designing the N-shaped chaos generator in the next section can be selected easily based on the bifurcation diagram shown in Figure 5.The dynamics behaviors of the chaotic map can be further examined in another reported work [27].

Design of Chaotic Triangular Ramp Generator
In the voltage mode of a DC-DC buck converter, a ramp signal is needed to modulate the PWM signal.Basically, there are two different possible forms for the ramp signal, a sawtooth ramp signal and a triangular ramp signal.The studies in [4] demonstrated that a symmetrically triangular ramp signal with equal rising and falling slopes can effectively mitigate the inductor current imbalance effect; therefore, it can also mitigate the aforementioned side-effects of the spread-spectrum technique without influencing the inductor current spectrum (and therefore the EMI performance).We therefore propose a PWM ramp generator that generates a triangular signal to reduce EMI and minimize the side-effects caused by the inductor current imbalance in the chaotic operation mode.
The detailed implementation of the proposed chaotic triangular ramp generator is shown in Figure 6a.The proposed chaotic triangular ramp generator consists of a triangular ramp generator linked with the proposed N-shaped chaotic circuit.Unlike a sawtooth ramp generator, in which the discharging time is much smaller than the charging time, the time for charging and discharging should be equal in a triangular ramp generator.Therefore, a current source/sink is used to control the charging/discharging speed to optimize the accuracy.This requirement preserves the memoryless property of the steady state inductor current, especially, when the switching frequency changes from cycle-to-cycle in chaotic operation mode.In the proposed triangular ramp generator shown in Figure 6a, the V-I converter (constructed from a error amplifier (EA), resistor (R), transistor (M1) and a wide-swing current source using cascade current mirror (M2-M5)) controls a charging current IChg = VBR/R.This current is copied by the current mirrors M6 and M8M10 to form a current sink that controls the discharging current IDChg.As mentioned before, the charging and discharging time for timing capacitor C1 must be equal, so IDChr = 2IChg.This is implemented by setting a current ratio between current mirrors M4-M5 and M9-M10 as 2:1.The operation of the proposed triangular

Design of Chaotic Triangular Ramp Generator
In the voltage mode of a DC-DC buck converter, a ramp signal is needed to modulate the PWM signal.Basically, there are two different possible forms for the ramp signal, a sawtooth ramp signal and a triangular ramp signal.The studies in [4] demonstrated that a symmetrically triangular ramp signal with equal rising and falling slopes can effectively mitigate the inductor current imbalance effect; therefore, it can also mitigate the aforementioned side-effects of the spread-spectrum technique without influencing the inductor current spectrum (and therefore the EMI performance).We therefore propose a PWM ramp generator that generates a triangular signal to reduce EMI and minimize the side-effects caused by the inductor current imbalance in the chaotic operation mode.
The detailed implementation of the proposed chaotic triangular ramp generator is shown in Figure 6a.The proposed chaotic triangular ramp generator consists of a triangular ramp generator linked with the proposed N-shaped chaotic circuit.Unlike a sawtooth ramp generator, in which the discharging time is much smaller than the charging time, the time for charging and discharging should be equal in a triangular ramp generator.Therefore, a current source/sink is used to control the charging/discharging speed to optimize the accuracy.This requirement preserves the memoryless property of the steady state inductor current, especially, when the switching frequency changes from cycle-to-cycle in chaotic operation mode.In the proposed triangular ramp generator shown in Figure 6a, the V-I converter (constructed from a error amplifier (EA), resistor (R), transistor (M1) and a wide-swing current source using cascade current mirror (M2-M5)) controls a charging current I Chg = V BR /R.This current is copied by the current mirrors M6 and M8M10 to form a current sink that controls the discharging current I DChg .As mentioned before, the charging and discharging time for timing capacitor C 1 must be equal, so I DChr = 2I Chg .This is implemented by setting a current ratio between current mirrors M4-M5 and M9-M10 as 2:1.The operation of the proposed triangular ramp generator can be briefly described as follows: Assume that at the beginning, after an initial reset event (with the triangular signal at low threshold limit (V L )), the switch M7 is OFF and capacitor C1 is slowly charged with charge-current I Chg until the capacitor voltage (ramp) reaches the upper limit (V H ). At that point, the comparator trips, and the switch M7 switch is turned ON, which discharges the ramp to V L by the current sink M6 with I DChg = 2I Chg .When the triangular signal ramps down to V L , another cycle begins [28].To reduce the asymmetry of the triangular ramp signal caused by current mismatches in the current mirrors, the length of the transistors in the current mirror should be large.
capacitor C1 is slowly charged with charge-current IChg until the capacitor voltage (ramp) reaches the upper limit (VH).At that point, the comparator trips, and the switch M7 switch is turned ON, which discharges the ramp to VL by the current sink M6 with IDChg = 2IChg.When the triangular signal ramps down to VL, another cycle begins [28].To reduce the asymmetry of the triangular ramp signal caused by current mismatches in the current mirrors, the length of the transistors in the current mirror should be large.Figure 6b shows the implementation of the proposed N-shaped chaos generator.In this circuit, the inverter MN6-MP6 plays the role of the SPDT switch, whereas the transistors MPCS1 and MNCS1 act as the current source I1 and current sink I2, respectively.The one-shot circuit is used to generate short pulses for the SR latches because the clock signal (CLK) ideally consists of an impulse train at the rate f = 1/T.Practically, these impulses are approximated by narrow pulses and implemented using the one-shot circuit.The N-shaped chaotic circuit parameter was designed based on the selection of the mathematical model's parameters T1 and T2.For this work, T2 is selected inside the chaos region (as shown in Figure 5) for robust chaos generation against the variation inherent in process fabrication as mentioned in [27].With the proposed N-shaped chaos generator, the output is chaotic, as long as T2/T1 > 1.This condition can be easily met, irrespective of the variation of capacitor C2 (usually up to 30% of the design value).Because T1 = T × I1/(VHC), T2 = T × I2/(VHC); therefore, setting the ratio T2/T1 > 1 is equivalent to setting the ratio I2/I1 > 1.This can be easily controlled at the circuit level using a basic current mirror and matching the layout between the current source/sink (MPCS1 and MNCS1).
The triangular ramp generator and N-shaped chaotic circuit are connected together to construct the chaotic ramp generator.The switching frequency of the triangular ramp generator proposed in Figure 7 can be expressed as [29]: Figure 6b shows the implementation of the proposed N-shaped chaos generator.In this circuit, the inverter MN6-MP6 plays the role of the SPDT switch, whereas the transistors MPCS1 and MNCS1 act as the current source I 1 and current sink I 2 , respectively.The one-shot circuit is used to generate short pulses for the SR latches because the clock signal (CLK) ideally consists of an impulse train at the rate f = 1/T.Practically, these impulses are approximated by narrow pulses and implemented using the one-shot circuit.The N-shaped chaotic circuit parameter was designed based on the selection of the mathematical model's parameters T 1 and T 2 .For this work, T 2 is selected inside the chaos region (as shown in Figure 5) for robust chaos generation against the variation inherent in process fabrication as mentioned in [27].With the proposed N-shaped chaos generator, the output is chaotic, as long as T 2 /T 1 > 1.This condition can be easily met, irrespective of the variation of capacitor C 2 (usually up to 30% of the design value).Because T 1 = T × I 1 /(V H C), T 2 = T × I 2 /(V H C); therefore, setting the ratio T 2 /T 1 > 1 is equivalent to setting the ratio I 2 /I 1 > 1.This can be easily controlled at the circuit level using a basic current mirror and matching the layout between the current source/sink (M PCS1 and M NCS1 ).
The triangular ramp generator and N-shaped chaotic circuit are connected together to construct the chaotic ramp generator.The switching frequency of the triangular ramp generator proposed in Figure 7 can be expressed as [29]: where V H and V L are the high and low bounds of the triangular ramp signal, respectively.Clearly, Equation (7) shows that two parameters can define the switching frequency of the triangular ramp generator: the ramp bounds (V H and V L ) and the charging current I Chg of the triangular signal.To alter the switching frequency from cycle to cycle, one or both parameters can be modulated using the generated chaotic signal (V chaos ) from the N-shaped chaotic generator.
where VH and VL are the high and low bounds of the triangular ramp signal, respectively.Clearly, Equation (7) shows that two parameters can define the switching frequency of the triangular ramp generator: the ramp bounds (VH and VL) and the charging current IChg of the triangular signal.To alter the switching frequency from cycle to cycle, one or both parameters can be modulated using the generated chaotic signal (Vchaos) from the N-shaped chaotic generator.
(a) (b) For the first scheme (peak modulation), keeping the low bound (VL) and the charging current (IChg) unchanged causes the switching frequency of the ramp generator to depend only on the high bound (VH).The chaotic signal generated from the N-shaped chaos generator can then be fed directly into the VH of the comparator, making VH = Vchaos; therefore, the switching frequency of the ramp generator is chaotically modulated.Figure 7a depicts the timing diagram for that method.For the second method (slope modulation), the chaotic signal generated from the N-shaped chaos generator can be indirectly fed into the V-I converter at VBR, making VBR = Vchaos.Its timing diagram is shown in Figure 7b.In this scheme, the chaotic signal is converted into chaotic charging/discharging currents; therefore, the ramp signal and switching frequency are also chaotic.The chaotic signal from the N-shaped ramp generator cannot be fed directly into VBR because that continuous chaotic signal also changes the charge/discharging current within one cycle.Therefore, the chaotic signal is sampled only at the end of each cycle by an impulse (S) signal from the low-threshold comparator (U1) inside the ramp generator circuit.This configuration keeps the charging/discharging current (IChg/IDChg) unchanged until the end of the current cycle and eliminates disturbances on the triangular waveform.The switching frequency deviation (ΔFSW) in the chaotic mode is set near the fixed-frequency mode at 1.2 MHz and the frequency envelope of the chaotic triangular ramp signal is in the range of: for the peak modulation and: For the first scheme (peak modulation), keeping the low bound (V L ) and the charging current (I Chg ) unchanged causes the switching frequency of the ramp generator to depend only on the high bound (V H ). The chaotic signal generated from the N-shaped chaos generator can then be fed directly into the V H of the comparator, making V H = V chaos ; therefore, the switching frequency of the ramp generator is chaotically modulated.Figure 7a depicts the timing diagram for that method.For the second method (slope modulation), the chaotic signal generated from the N-shaped chaos generator can be indirectly fed into the V-I converter at V BR , making V BR = V chaos .Its timing diagram is shown in Figure 7b.In this scheme, the chaotic signal is converted into chaotic charging/discharging currents; therefore, the ramp signal and switching frequency are also chaotic.The chaotic signal from the N-shaped ramp generator cannot be fed directly into V BR because that continuous chaotic signal also changes the charge/discharging current within one cycle.Therefore, the chaotic signal is sampled only at the end of each cycle by an impulse (S) signal from the low-threshold comparator (U1) inside the ramp generator circuit.This configuration keeps the charging/discharging current (I Chg /I DChg ) unchanged until the end of the current cycle and eliminates disturbances on the triangular waveform.The switching frequency deviation (∆F SW ) in the chaotic mode is set near the fixed-frequency mode at 1.2 MHz and the frequency envelope of the chaotic triangular ramp signal is in the range of: for the peak modulation and: for the slope modulation.By using Equations ( 12) and ( 13), the circuit parameters of the chaotic ramp generator such as C1, I Chg , VH, VL, VHC, and VLC can be derived for implementation.
The derived values of VHC, VLC from Equations ( 12) and ( 13) in combination with the normalized and parametrized Equation ( 6) presented in Section 2.2 can then be used to calculate the circuit parameters for N-shape chaos generators T, I1, I2 and C. It should be noted that the N-shaped chaos generator confines its chaotic signal at the output within a defined band [V LC ; V HC ] by two comparators.This assures that the frequency deviation of the chaotic ramp signal can be accurately controlled.
This characteristic adds extra controllability to the chaotic ramp generator as the frequency deviation can be customized.
Of the two methods for generating the chaotic triangular ramp signal presented above, the peak level injection offers easier implementation.The slope modulation is more complex because it samples the chaotic signal and thus needs an additional sampling circuit.The slope modulation scheme also requires a high bandwidth V-I converter because the speed for converting the chaotic signal into chaotic current needs to be fast enough for the charging current to switch from one level to another at the beginning of each cycle.In practice, the bandwidth of the V-I converter is set to at least 10 times the switching frequency.In designing the triangular circuit, because the ramp down slope of the triangle is lower than that of the sawtooth ramp generator, the design of the comparator is simple, and the power consumption of the comparator is low.Additionally, because the ramp amplitude directly affects the stability of the buck converter in voltage mode [21], the compensation network of the converter using a triangular ramp generator with peak modulation should be designed carefully.For the slope modulation method, the amplitude of the ramp signal is kept constant, and the stability does not change once the compensation network is fixed.

Simulation Results
Before fabricating a chip, we examined the performance of the proposed EMI-improved buck converter through a simulation.The chaotic ramp generator presented in the previous section was applied to the dual-mode PWM/PFM buck converter in Figure 1 to examine the EMI reduction performance.The simulation was conducted for both the standard mode and the chaotic mode for ease of comparison.The nominal switching frequency F SW for the standard mode was set to 1.2 MHz, and the chaotic frequency range was set at +/−10% of the F sw (1.08 MHz to 1.32 MHz) and +/−20% of F sw (0.96 MHz to 1.44 MHz).
In the standard mode, the design parameters of the triangular ramp were set at V BR = 0.6 V, C = 3 pF, V H = 1.5 V and V L = 0.8 V to achieve a nominal of F SW = 1.2 MHz.To achieve the frequency deviations of +/−10% and +/−20% around the nominal switching frequency F SW , the bounds of the chaotic signal (V Chaos ) applied to the V BR of the ramp were set at V HC = 0.66 V, V LC = 0.514 V, V HC = 0.71 V, and V LC = 0.46 V, in accordance with Equation (9).In the chaotic mode, the mean value of F SW = 1.2 MHz is defined using the mean value of V HC and V LC .Following the condition of T2/T1 > 1 or I2/I1 > 1 to output the chaotic signal, the parameters of the N-shaped chaotic circuit were set at: C = 3 pF, I1 = 1 µA, I2 = 6 µA, and CK = 1 MHz for both cases.The simulation setup for the converter was: V IN = 3 V, V OUT = 1.8 V, I OUT = 250 mA, L = 2.2 µH and C OUT = 2.2 µF.The ESR value of the capacitor (ESR = 30 mΩ) and the other components of the compensation network were selected from commercial elements to give a good predictable result when comparing the simulation with the real test chip measurement results.
Figure 8 shows the simulation results for the converter when operating in the chaotic mode with the chaotic triangular ramp generator using slope modulation.Clearly, the chaotic signal from the N-shaped chaos generator is sampled at the beginning of each switching cycle and then fed into the V-I converter at the V BR of the triangular generator.As a consequence, the converter operates in the chaotic mode.The inset figure of inductor current shows that it varies chaotically; therefore, the EMI performance will be improved.The chaotic operation of the buck converter can also be easily confirmed from the phase portrait of two internal chaotic states (inductor current and output voltage) shown in Figure 9b.Compared to the standard mode shown in Figure 9a, in which the operation is stable between two equilibrium points and can thus be presented by only one trajectory, the chaotic operation shows a complex pattern, including multiple un-repeated trajectories that represent chaos.EMI performance will be improved.The chaotic operation of the buck converter can also be easily confirmed from the phase portrait of two internal chaotic states (inductor current and output voltage) shown in Figure 9b.Compared to the standard mode shown in Figure 9a, in which the operation is stable between two equilibrium points and can thus be presented by only one trajectory, the chaotic operation shows a complex pattern, including multiple un-repeated trajectories that represent chaos.The simulated switching frequency distribution of the chaotic triangular ramp generator using slope modulation is shown in Figure 10.To achieve the most flattened power spectrum, a uniformly distributed switching frequency is most desirable [18].As seen in Figure 10, the distribution of the chaotic switching frequency is not uniformly distributed over the desired frequency range.However, the frequency spreads out continuously in the pre-defined range; therefore, harmonic peaks in the power spectrum in chaotic mode are expected to disappear.confirmed from the phase portrait of two internal chaotic states (inductor current and output voltage) shown in Figure 9b.Compared to the standard mode shown in Figure 9a, in which the operation is stable between two equilibrium points and can thus be presented by only one trajectory, the chaotic operation shows a complex pattern, including multiple un-repeated trajectories that represent chaos.The simulated switching frequency distribution of the chaotic triangular ramp generator using slope modulation is shown in Figure 10.To achieve the most flattened power spectrum, a uniformly distributed switching frequency is most desirable [18].As seen in Figure 10, the distribution of the chaotic switching frequency is not uniformly distributed over the desired frequency range.However, the frequency spreads out continuously in the pre-defined range; therefore, harmonic peaks in the power spectrum in chaotic mode are expected to disappear.The simulated switching frequency distribution of the chaotic triangular ramp generator using slope modulation is shown in Figure 10.To achieve the most flattened power spectrum, a uniformly distributed switching frequency is most desirable [18].As seen in Figure 10, the distribution of the chaotic switching frequency is not uniformly distributed over the desired frequency range.However, the frequency spreads out continuously in the pre-defined range; therefore, harmonic peaks in the power spectrum in chaotic mode are expected to disappear.Generally, the EMI reduction of the switched-mode dc-dc converters using spread spectrum technique can be verified by analyzing the power spectrum [16][17][18].The power spectrum of the switching node and the output node were calculated using the available spectrum analyzer tool in Cadence software.Because of the intended target is to show the power spectrum up to 30 MHz, the resolution bandwidth (RBW) for the calculation of power spectrum was 6.67 kHz.The selected bandwidth for the spectrum analyzer in Cadence was also setup at 5 GHz for capturing all the harmonics for the analysis.Figures 11 and 12 show the simulated power spectra of the output node and switching node under different conditions of frequency deviation under ILOAD = 250 mA.The spectrum of the converter in the standard mode with a fixed switching frequency of FSW = 1.2 MHz is included as a benchmark for comparison with the chaotic mode.Clearly, the power is densely concentrated at the fundamental frequency of 1.2 MHz and its harmonics when the converter operates in standard mode, whereas the spectrum is continuous and the amplitudes of the spectral peaks are reduced in chaotic operations.This is because the total emitted energy does not change; instead, the energy gets spread over a wider frequency range, thereby reducing peak emissions [30].To determine the optimal frequency deviation in the chaotic mode in terms of EMI reduction performance and minimize the negative side-effects, the proposed design was simulated for 2 cases.For the first case, the switching frequency was chaotically varied within +/−10% of FSW, which reduced the fundamental harmonic peak from −13.34 dBm to −28.4 dBm at the output node and improved the peak at the switching node from 10.12 dBm to −4.87 dBm.The improvement of the power spectrum of the output node is similar to that of the switching node, and the EMI reduction for this case is approximately 15 dBm.For the second case, when the frequency deviation is increased to +/−20% of FSW, the EMI reduction is approximately 19 dBm.Generally, the EMI reduction of the switched-mode dc-dc converters using spread spectrum technique can be verified by analyzing the power spectrum [16][17][18].The power spectrum of the switching node and the output node were calculated using the available spectrum analyzer tool in Cadence software.Because of the intended target is to show the power spectrum up to 30 MHz, the resolution bandwidth (RBW) for the calculation of power spectrum was 6.67 kHz.The selected bandwidth for the spectrum analyzer in Cadence was also setup at 5 GHz for capturing all the harmonics for the analysis.Figures 11 and 12 show the simulated power spectra of the output node and switching node under different conditions of frequency deviation under I LOAD = 250 mA.The spectrum of the converter in the standard mode with a fixed switching frequency of F SW = 1.2 MHz is included as a benchmark for comparison with the chaotic mode.Clearly, the power is densely concentrated at the fundamental frequency of 1.2 MHz and its harmonics when the converter operates in standard mode, whereas the spectrum is continuous and the amplitudes of the spectral peaks are reduced in chaotic operations.This is because the total emitted energy does not change; instead, the energy gets spread over a wider frequency range, thereby reducing peak emissions [30].To determine the optimal frequency deviation in the chaotic mode in terms of EMI reduction performance and minimize the negative side-effects, the proposed design was simulated for 2 cases.For the first case, the switching frequency was chaotically varied within +/−10% of F SW , which reduced the fundamental harmonic peak from −13.34 dBm to −28.4 dBm at the output node and improved the peak at the switching node from 10.12 dBm to −4.87 dBm.The improvement of the power spectrum of the output node is similar to that of the switching node, and the EMI reduction for this case is approximately 15 dBm.For the second case, when the frequency deviation is increased to +/−20% of F SW , the EMI reduction is approximately 19 dBm.As shown in the power spectra in Figures 11 and 12, as the frequency deviation increases, the power spectra can be effectively spread over a wider frequency range, thereby reducing the peaks at the harmonic frequencies to much lower levels.In previous works using the randomized modulation technique [17,18], the power at the harmonic frequencies was spread out around discrete fixed-frequency levels.In particular, using the theory reported in [18], and assuming that randomness was assured, the theoretical reduction (ideal case) in the power spectrum using 2, 4, and 8 switching frequencies was 6 dB, 12 dB, and 18 dB, respectively.Using the spread-spectrum chaotic modulation proposed here, the reduction in the power spectrum can easily be more than 18 dB without the requirement of randomness because the power spectrum is spread continuously out rather than clustered around discrete frequency harmonics.Also, the hardware implementation of this proposed system is much simpler than that in the previous work.Therefore, the proposed design outperforms those earlier works.
Theoretically, the inductor current imbalance effect caused by the time-varying switching frequency in chaotic mode can be eliminated by using the triangular ramp generator.In fact, the non-idealities, such as the non-ideal triangular ramp and the delay in the drivers and controller, will As shown in the power spectra in Figures 11 and 12, as the frequency deviation increases, the power spectra can be effectively spread over a wider frequency range, thereby reducing the peaks at the harmonic frequencies to much lower levels.In previous works using the randomized modulation technique [17,18], the power at the harmonic frequencies was spread out around discrete fixed-frequency levels.In particular, using the theory reported in [18], and assuming that randomness was assured, the theoretical reduction (ideal case) in the power spectrum using 2, 4, and 8 switching frequencies was 6 dB, 12 dB, and 18 dB, respectively.Using the spread-spectrum chaotic modulation proposed here, the reduction in the power spectrum can easily be more than 18 dB without the requirement of randomness because the power spectrum is spread continuously out rather than clustered around discrete frequency harmonics.Also, the hardware implementation of this proposed system is much simpler than that in the previous work.Therefore, the proposed design outperforms those earlier works.
Theoretically, the inductor current imbalance effect caused by the time-varying switching frequency in chaotic mode can be eliminated by using the triangular ramp generator.In fact, the non-idealities, such as the non-ideal triangular ramp and the delay in the drivers and controller, will As shown in the power spectra in Figures 11 and 12, as the frequency deviation increases, the power spectra can be effectively spread over a wider frequency range, thereby reducing the peaks at the harmonic frequencies to much lower levels.In previous works using the randomized modulation technique [17,18], the power at the harmonic frequencies was spread out around discrete fixed-frequency levels.In particular, using the theory reported in [18], and assuming that randomness was assured, the theoretical reduction (ideal case) in the power spectrum using 2, 4, and 8 switching frequencies was 6 dB, 12 dB, and 18 dB, respectively.Using the spread-spectrum chaotic modulation proposed here, the reduction in the power spectrum can easily be more than 18 dB without the requirement of randomness because the power spectrum is spread continuously out rather than clustered around discrete frequency harmonics.Also, the hardware implementation of this proposed system is much simpler than that in the previous work.Therefore, the proposed design outperforms those earlier works.
Theoretically, the inductor current imbalance effect caused by the time-varying switching frequency in chaotic mode can be eliminated by using the triangular ramp generator.In fact, the non-idealities, such as the non-ideal triangular ramp and the delay in the drivers and controller, will cause a small imbalance in the inductor current; therefore, in fact, the low-frequency ripple caused by the chaotic switching frequency still exists [4,28].This perturbation will be injected into the output voltage at the switching frequency.A feedback network in response to perturbation at such a high rate of change cannot occur in a voltage-mode converter with limited bandwidth (0.2-0.3 switching frequency (F SW )), so the perturbation from the inductor current imbalance is injected into the output node.THis increases the output voltage ripple compared to the fixed-frequency PWM operation mode.After a few cycles, the amount of output voltage ripple accumulates, and the feedback network will start to respond and remove the redundant voltage.Figure 13 shows the simulation results for the inductor current ripple and the output voltage ripple when the converter operates in chaotic mode.As seen in this figure, the converter output ripple increases compared to the standard fixed-frequency mode (and the mean value of the output voltage is considered to be unchanged).In particular, the output ripple is more than two-fold (28 mV vs. 13.36 mV of standard mode) with F WS +/− 10%, while the output ripple is more than three-fold that of standard mode when the switching frequency deviation ∆F SW is increased to +/− 20% (36 mV vs. 13.36 mV of standard mode).Clearly, the output voltage ripple in the chaotic PWM mode is much higher than in the standard fixed-frequency PWM mode.
Electronics 2018, 7, x FOR PEER REVIEW 16 of 25 cause a small imbalance in the inductor current; therefore, in fact, the low-frequency ripple caused by the chaotic switching frequency still exists [4,28].This perturbation will be injected into the output voltage at the switching frequency.A feedback network in response to perturbation at such a high rate of change cannot occur in a voltage-mode converter with limited bandwidth (0.2-0.3 switching frequency (FSW)), so the perturbation from the inductor current imbalance is injected into the output node.THis increases the output voltage ripple compared to the fixed-frequency PWM operation mode.After a few cycles, the amount of output voltage ripple accumulates, and the feedback network will start to respond and remove the redundant voltage.Figure 13 shows the simulation results for the inductor current ripple and the output voltage ripple when the converter operates in chaotic mode.As seen in this figure, the converter output ripple increases compared to the standard fixed-frequency mode (and the mean value of the output voltage is considered to be unchanged).In particular, the output ripple is more than two-fold (28 mV vs. 13.36 mV of standard mode) with FWS +/− 10%, while the output ripple is more than three-fold that of standard mode when the switching frequency deviation ΔFSW is increased to +/− 20% (36 mV vs. 13.36 mV of standard mode).Clearly, the output voltage ripple in the chaotic PWM mode is much higher than in the standard fixed-frequency PWM mode.
(a) (b) As presented previously, there are two schemes for chaotic modulation in the triangular ramp generator: peak modulation and slope modulation.All of the simulated results above are based on the triangular ramp generator using slope modulation.To re-confirm the advantages of slope modulation, we also checked the performance of the converter with the ramp generator using peak modulation.Under the same frequency deviation condition with peak modulation, the output ripple rose to 213 mV and 549 mV, and the inductor current ripple rose to 549 mA and 984 mA, respectively, for 10% and 20% of switching frequency deviation.This confirms that peak modulation should not be used in the chaotic ramp generator even if the EMI performance could be improved significantly because of the large trade-offs in the output voltage ripple and inductor current ripple.
The results from the simulation showed that the frequency deviation (ΔFSW) should be small to limit the effects on the output ripple and the inductor current ripple, but it should also be large to achieve a significant EMI reduction.Therefore, the value of ΔFSW should be determined by balancing the trade-off between the ripple performance and the EMI of the converter.The switching frequency deviation should not usually be more than 20% because of the large trade-offs on the primary As presented previously, there are two schemes for chaotic modulation in the triangular ramp generator: peak modulation and slope modulation.All of the simulated results above are based on the triangular ramp generator using slope modulation.To re-confirm the advantages of slope modulation, we also checked the performance of the converter with the ramp generator using peak modulation.Under the same frequency deviation condition with peak modulation, the output ripple rose to 213 mV and 549 mV, and the inductor current ripple rose to 549 mA and 984 mA, respectively, for 10% and 20% of switching frequency deviation.This confirms that peak modulation should not be used in the chaotic ramp generator even if the EMI performance could be improved significantly because of the large trade-offs in the output voltage ripple and inductor current ripple.
The results from the simulation showed that the frequency deviation (∆F SW ) should be small to limit the effects on the output ripple and the inductor current ripple, but it should also be large to achieve a significant EMI reduction.Therefore, the value of ∆F SW should be determined by balancing the trade-off between the ripple performance and the EMI of the converter.The switching frequency deviation should not usually be more than 20% because of the large trade-offs on the primary performance, such as output voltage ripple, inductor current ripple, and power efficiency.For example, when ∆F SW was higher than 20%, the output voltage ripple was increased by orders of up to 10 mV, which is unacceptable for practical use.Additionally, the high inductor current ripple with the triangular ramp using peak modulation adds difficulty in designing the PWM/PFM controller, because the load current is indirectly sensed through the inductor current when switching between the PWM/PFM modes.Because the inductor current ripple changes from cycle-to-cycle, unexpected ring switching will happen between PWM and PFM.Therefore, the triangular ramp generator using slope modulation is more appropriate because of it much lower ripple.Finally, it is important to understand that the effect of a fixed frequency of the clock (CK) in the chaotic circuit does not affect the EMI reduction performance of the proposed scheme, as was found in [18], because the operation of the converter is asynchronous with the clocking signal (CK) of the chaos generator.As shown by the power spectrum when the converter is in chaotic mode (Figures 11 and 12), it does not peak at CK = 1.2 MHz.

EMI Reduction Performance of the Proposed Scheme
To verify the proposed chaotic PWM scheme and compare it with a fixed-frequency PWM, a buck converter with the proposed chaotic ramp signal generator and slope modulation was designed and fabricated using a 3.3 V, 0.18 µm, CMOS one-poly six-metal-layers process.The active chip area was 0.626 mm 2 (0.602 µm × 1.04 mm), excluding bonding pads, where the power transistors occupy 520 × 365 µm 2 .The chip photograph and the chip mounted on PCB for testing are shown in Figure 14.The experimental setup is shown in Figure 15 and the list of component values for the prototype is shown in Table 2.The terminal MODE (MODE = 0:Fixed-frequency PWM, MODE = 1:Chaotic PWM) can switch between the standard fixed-frequency PWM mode and the proposed chaotic PWM mode.Unless otherwise stated, all of the following results were measured using an input voltage of 3.3 V.
Electronics 2018, 7, x FOR PEER REVIEW 17 of 25 performance, such as output voltage ripple, inductor current ripple, and power efficiency.For example, when ΔFSW was higher than 20%, the output voltage ripple was increased by orders of up to 10 mV, which is unacceptable for practical use.Additionally, the high inductor current ripple with the triangular ramp using peak modulation adds difficulty in designing the PWM/PFM controller, because the load current is indirectly sensed through the inductor current when switching between the PWM/PFM modes.Because the inductor current ripple changes from cycle-to-cycle, unexpected ring switching will happen between PWM and PFM.Therefore, the triangular ramp generator using slope modulation is more appropriate because of it much lower ripple.Finally, it is important to understand that the effect of a fixed frequency of the clock (CK) in the chaotic circuit does not affect the EMI reduction performance of the proposed scheme, as was found in [18], because the operation of the converter is asynchronous with the clocking signal (CK) of the chaos generator.As shown by the power spectrum when the converter is in chaotic mode (Figures 11 and 12), it does not peak at CK = 1.2 MHz.

EMI Reduction Performance of the Proposed Scheme
To verify the proposed chaotic PWM scheme and compare it with a fixed-frequency PWM, a buck converter with the proposed chaotic ramp signal generator and slope modulation was designed and fabricated using a 3.3 V, 0.18 µm, CMOS one-poly six-metal-layers process.The active chip area was 0.626 mm 2 (0.602 µm × 1.04 mm), excluding bonding pads, where the power transistors occupy 520 × 365 µm 2 .The chip photograph and the chip mounted on PCB for testing are shown in Figure 14.The experimental setup is shown in Figure 15 and the list of component values for the prototype is shown in Table 2.The terminal MODE (MODE = 0:Fixed-frequency PWM, MODE = 1:Chaotic PWM) can switch between the standard fixed-frequency PWM mode and the proposed chaotic PWM mode.Unless otherwise stated, all of the following results were measured using an input voltage of 3.3 V.    First, we constructed an experiment to examine the operation of the ramp generator to verify its functional operation before checking the EMI performance of the proposed scheme.Figure 16 shows the measurement results for the ramp generator in two modes (controlled by the MODE terminal).Because the parasitic capacitor on the voltage probe terminal of the measurement equipment is quite high (up to 10 pF) compared to the internal capacitor of the ramp and clock generator (2 pF in this study), the ramp signal should not be measured directly.Instead, an on-chip reading buffer was embedded to measure the clock signal inside the chip.The biasing current resistor (R) of the V-I converter for the triangular ramp generator is off-chip in order to tune the biasing current of the ramp generator in the prototype.When the MODE terminal is connected to the GND, the triangular ramp generator works in standard mode, whereas it works in chaotic mode when the MODE terminal is connected to the VDD. Figure 16a,b shows the measurement results from the triangular ramp generator for the standard mode and the chaotic mode (FSW +/− 20%), respectively.Clearly, the switching frequency is a constant for the standard mode when a fixed VBR is used and chaotic when chaotic VBR generated from the N-shaped chaos generator is used.The measured constant FSW is approximately 1.2 MHz (MODE = 0 V, VBR = 0.61 V), and the measured chaotic switching frequency is in the range from 1.06 MHz to 1.37 MHz (MODE = VDD; VBR is chaotic when internally connected to the N-shaped chaos generator; VHC = 0.73 V, VLC = 0.41 V (tuned values)).The experimental result for the triangular ramp generator matches well with the simulation result, with only a small mismatch caused by chip fabrication.First, we constructed an experiment to examine the operation of the ramp generator to verify its functional operation before checking the EMI performance of the proposed scheme.Figure 16 shows the measurement results for the ramp generator in two modes (controlled by the MODE terminal).Because the parasitic capacitor on the voltage probe terminal of the measurement equipment is quite high (up to 10 pF) compared to the internal capacitor of the ramp and clock generator (2 pF in this study), the ramp signal should not be measured directly.Instead, an on-chip reading buffer was embedded to measure the clock signal inside the chip.The biasing current resistor (R) of the V-I converter for the triangular ramp generator is off-chip in order to tune the biasing current of the ramp generator in the prototype.When the MODE terminal is connected to the GND, the triangular ramp generator works in standard mode, whereas it works in chaotic mode when the MODE terminal is connected to the V DD .Figure 16a,b shows the measurement results from the triangular ramp generator for the standard mode and the chaotic mode (F SW +/− 20%), respectively.Clearly, the switching frequency is a constant for the standard mode when a fixed V BR is used and chaotic when chaotic V BR generated from the N-shaped chaos generator is used.The measured constant F SW is approximately 1.2 MHz (MODE = 0 V, V BR = 0.61 V), and the measured chaotic switching frequency is in the range from 1.06 MHz to 1.37 MHz (MODE = V DD ; V BR is chaotic when internally connected to the N-shaped chaos generator; V HC = 0.73 V, V LC = 0.41 V (tuned values)).The experimental result for the triangular ramp generator matches well with the simulation result, with only a small mismatch caused by chip fabrication.To test the EMI reduction in chaotic mode, the operation of the designed PWM/PFM buck converter in standard mode with a fixed switching frequency was also confirmed.Figure 17 shows the experimental results of the converter in standard mode under different load conditions (250 mA-PWM and 150 mA-PFM).The measured output ripples were 17 mV and 28 mA for the PWM and PFM modes, respectively.Because the switching node (rather than the output) is the dominant source of EMI [18], we evaluated the EMI performance by looking at the peaks in the power density spectrum of the inductor current (IL), aiming to reduce it compared with its fixed-frequency counterpart.To evaluate the effectiveness of the proposed scheme, the inductor current of the buck converter in both the standard and chaotic mode was measured and analyzed using the discrete Fourier transform in MATLAB to estimate the EMI reduction.Figure 18a shows the measured inductor current in standard mode (top) and chaotic mode (bottom) with 10% switching frequency deviation, and Figure 18b shows their associated power spectrum analyses.The peaks that appear at the multiples of the fundamental frequency, FSW, are dramatically suppressed compared to the standard mode, To test the EMI reduction in chaotic mode, the operation of the designed PWM/PFM buck converter in standard mode with a fixed switching frequency was also confirmed.Figure 17 shows the experimental results of the converter in standard mode under different load conditions (250 mA-PWM and 150 mA-PFM).The measured output ripples were 17 mV and 28 mA for the PWM and PFM modes, respectively.To test the EMI reduction in chaotic mode, the operation of the designed PWM/PFM buck converter in standard mode with a fixed switching frequency was also confirmed.Figure 17 shows the experimental results of the converter in standard mode under different load conditions (250 mA-PWM and 150 mA-PFM).The measured output ripples were 17 mV and 28 mA for the PWM and PFM modes, respectively.Because the switching node (rather than the output) is the dominant source of EMI [18], we evaluated the EMI performance by looking at the peaks in the power density spectrum of the inductor current (IL), aiming to reduce it compared with its fixed-frequency counterpart.To evaluate the effectiveness of the proposed scheme, the inductor current of the buck converter in both the standard and chaotic mode was measured and analyzed using the discrete Fourier transform in MATLAB to estimate the EMI reduction.Figure 18a shows the measured inductor current in standard mode (top) and chaotic mode (bottom) with 10% switching frequency deviation, and Figure 18b shows their associated power spectrum analyses.The peaks that appear at the multiples of the fundamental frequency, FSW, are dramatically suppressed compared to the standard mode, Because the switching node (rather than the output) is the dominant source of EMI [18], we evaluated the EMI performance by looking at the peaks in the power density spectrum of the inductor current (I L ), aiming to reduce it compared with its fixed-frequency counterpart.To evaluate the effectiveness of the proposed scheme, the inductor current of the buck converter in both the standard and chaotic mode was measured and analyzed using the discrete Fourier transform in MATLAB to estimate the EMI reduction.Figure 18a shows the measured inductor current in standard mode (top) and chaotic mode (bottom) with 10% switching frequency deviation, and Figure 18b shows their associated power spectrum analyses.The peaks that appear at the multiples of the fundamental frequency, F SW , are dramatically suppressed compared to the standard mode, similar to the simulation results in the previous section.The observed peak reduction at the first harmonic is about 14.53 dB, which agrees closely with the simulation result (15 dB).In fact, these differences come from the statistical properties of the chaotic output trajectory (in other words, the statistics of the chaotic frequency distribution).Also, the peak of the first harmonic of the power spectrum is at approximately 1.214 MHz for the standard mode, whereas the highest peak harmonic in the chaotic mode is at 1.2 MHz.Thus, the chaotic frequency distribution is focused at 1.2 MHz in chaotic mode, which slightly lowers the power spectrum reduction level of the proposed scheme.Additionally, the low spectrum peaks in the low-frequency range (lower than the minimum chaotic switching frequency) come from the low-frequency disturbance of the inductor current when the chaotic PWM is applied.However, it is still much lower than the other peaks, so it is not a concern related to EMI.
Electronics 2018, 7, x FOR PEER REVIEW 20 of 25 similar to the simulation results in the previous section.The observed peak reduction at the first harmonic is about 14.53 dB, which agrees closely with the simulation result (15 dB).In fact, these differences come from the statistical properties of the chaotic output trajectory (in other words, the statistics of the chaotic frequency distribution).Also, the peak of the first harmonic of the power spectrum is at approximately 1.214 MHz for the standard mode, whereas the highest peak harmonic in the chaotic mode is at 1.2 MHz.Thus, the chaotic frequency distribution is focused at 1.2 MHz in chaotic mode, which slightly lowers the power spectrum reduction level of the proposed scheme.Additionally, the low spectrum peaks in the low-frequency range (lower than the minimum chaotic switching frequency) come from the low-frequency disturbance of the inductor current when the chaotic PWM is applied.However, it is still much lower than the other peaks, so it is not a concern related to EMI.Comparisons with the standard are necessary to demonstrate the effectiveness of the proposed method.The EMI measurements of the buck converter in standard and chaotic modes are shown in Figure 19 along with the CISPR22 A-B limit.The EMI reduction obtained from the measurement is 14.36 dB at the fundamental switching frequency.The results show that operating the converter in chaotic mode reduces the EMI in the low-frequency range, which is consistent with the power spectrum analysis.The proposed method reduces the EMI of the DC-DC converter and satisfies the EMI standard is indicated in CISPR 22.In the test setup, the LISN (impedance stabilizer network) is located between the input power supply and the DC-DC converter under test [17].Power spectrum analyzer is set at RBW = 3 kHz, and the frequency range of the measurements is 0.5-30 MHz.Comparisons with the standard are necessary to demonstrate the effectiveness of the proposed method.The EMI measurements of the buck converter in standard and chaotic modes are shown in Figure 19 along with the CISPR22 A-B limit.The EMI reduction obtained from the measurement is 14.36 dB at the fundamental switching frequency.The results show that operating the converter in chaotic mode reduces the EMI in the low-frequency range, which is consistent with the power spectrum analysis.The proposed method reduces the EMI of the DC-DC converter and satisfies the EMI standard is indicated in CISPR 22.In the test setup, the LISN (impedance stabilizer network) is located between the input power supply and the DC-DC converter under test [17].Power spectrum analyzer is set at RBW = 3 kHz, and the frequency range of the measurements is 0.5-30 MHz.The EMI performance of the proposed chaotic PWM scheme and other state-of-the-art works using the spread-spectrum technique are compared in Table 3.The proposed scheme achieved better EMI performance than the other alternatives compared.The performance of the proposed scheme can be explained by the fact that the chaotic switching frequency in the proposed scheme is continuously spread out within a certain frequency range rather than swept at several random fixed-frequency levels, as presented in [17,18].In addition, the randomized PWM methods in [17,18] are usually costly because of their complex designs and the difficulty of confirming randomness.The most appealing advantage of the proposed scheme is that it can be easily embedded into any PWM buck converter using a standard ramp generator without modifying the overall structure.Therefore, the proposed scheme offers a cheap and effective solution for practical usage.

Reducing the Side Effects of the Proposed EMI-Improvement Scheme
The main purpose of a DC-DC converter is power conversion; therefore, the power efficiency of a converter must be maintained in a reasonable range whatever EMI reduction technique is used.Figure 20 shows the measured power efficiency at different load currents.The maximum power efficiencies of the converters are 84% and 83.1% for the fixed-frequency PWM mode and chaotic PWM mode, respectively.There is no difference in the power efficiency between the two PFM modes because they are common and are not included in EMI reduction.When the converter operates in PWM at moderate and heavy loads (200 mA to 450 mA), the power efficiency of the The EMI performance of the proposed chaotic PWM scheme and other state-of-the-art works using the spread-spectrum technique are compared in Table 3.The proposed scheme achieved better EMI performance than the other alternatives compared.The performance of the proposed scheme can be explained by the fact that the chaotic switching frequency in the proposed scheme is continuously spread out within a certain frequency range rather than swept at several random fixed-frequency levels, as presented in [17,18].In addition, the randomized PWM methods in [17,18] are usually costly because of their complex designs and the difficulty of confirming randomness.The most appealing advantage of the proposed scheme is that it can be easily embedded into any PWM buck converter using a standard ramp generator without modifying the overall structure.Therefore, the proposed scheme offers a cheap and effective solution for practical usage.

Reducing the Side Effects of the Proposed EMI-Improvement Scheme
The main purpose of a DC-DC converter is power conversion; therefore, the power efficiency of a converter must be maintained in a reasonable range whatever EMI reduction technique is used.Figure 20 shows the measured power efficiency at different load currents.The maximum power efficiencies of the converters are 84% and 83.1% for the fixed-frequency PWM mode and chaotic PWM mode, respectively.There is no difference in the power efficiency between the two PFM modes because they are common and are not included in EMI reduction.When the converter operates in PWM at moderate and heavy loads (200 mA to 450 mA), the power efficiency of the chaotic mode is less than that of the standard mode.The maximum power efficiency degradation is at the maximum load condition of 450 mA, with a reduction of 2% in power efficiency, mainly from the conduction loss, because the average switching frequency of the converter in chaotic mode and fixed-frequency in standard mode is approximately equal.When the converter operates in the chaotic mode, the ripple range of the inductor current increases, which results in an increase in the RMS inductor current.As a consequence, the power loss on the inductor and the on-resistance of the power switches also increases.
Electronics 2018, 7, x FOR PEER REVIEW 22 of 25 chaotic mode is less than that of the standard mode.The maximum power efficiency degradation is at the maximum load condition of 450 mA, with a reduction of 2% in power efficiency, mainly from the conduction loss, because the average switching frequency of the converter in chaotic mode and fixed-frequency in standard mode is approximately equal.When the converter operates in the chaotic mode, the ripple range of the inductor current increases, which results in an increase in the RMS inductor current.As a consequence, the power loss on the inductor and the on-resistance of the power switches also increases.Figure 21 shows the measured output voltage ripple in two modes.In this experiment, additional capacitors were added (as shown in Figure 3) to eliminate the high-frequency noises caused by the switching operation of the power switches.The measurements show an output voltage ripple of 38 mV and 16 mV for chaotic mode and standard mode operations, respectively.Compared to the output voltage ripple when the converter operates in PFM mode (Figure 17b), the ripple of the converter in PWM chaotic mode is approximately the same.This can be solved by increasing the capacitor value at the output but that increases the power module and adds additional costs.However, compared to the active EMI reduction with an input filter, this scheme is still much better, and therefore, it can be used for many applications.For a further demonstration, we conducted an experiment in which we increased COUT to 4.7 uF.The output voltage ripple decreased from 38 mV to 27 mV (approximately equal to the output voltage ripple when the converter enters PFM mode at a light load).It should be noted that this might result in instability.As a consequence, the compensation network should be redesigned to balance EMI performance with other factors, depending on the specific application.Figure 21 shows the measured output voltage ripple in two modes.In this experiment, additional capacitors were added (as shown in Figure 3) to eliminate the high-frequency noises caused by the switching operation of the power switches.The measurements show an output voltage ripple of 38 mV and 16 mV for chaotic mode and standard mode operations, respectively.Compared to the output voltage ripple when the converter operates in PFM mode (Figure 17b), the ripple of the converter in PWM chaotic mode is approximately the same.This can be solved by increasing the capacitor value at the output but that increases the power module and adds additional costs.However, compared to the active EMI reduction with an input filter, this scheme is still much better, and therefore, it can be used for many applications.For a further demonstration, we conducted an experiment in which we increased C OUT to 4.7 uF.The output voltage ripple decreased from 38 mV to 27 mV (approximately equal to the output voltage ripple when the converter enters PFM mode at a light load).It should be noted that this might result in instability.As a consequence, the compensation network should be redesigned to balance EMI performance with other factors, depending on the specific application.
Electronics 2018, 7, x FOR PEER REVIEW 22 of 25 chaotic mode is less than that of the standard mode.The maximum power efficiency degradation is at the maximum load condition of 450 mA, with a reduction of 2% in power efficiency, mainly from the conduction loss, because the average switching frequency of the converter in chaotic mode and fixed-frequency in standard mode is approximately equal.When the converter operates in the chaotic mode, the ripple range of the inductor current increases, which results in an increase in the RMS inductor current.As a consequence, the power loss on the inductor and the on-resistance of the power switches also increases.Figure 21 shows the measured output voltage ripple in two modes.In this experiment, additional capacitors were added (as shown in Figure 3) to eliminate the high-frequency noises caused by the switching operation of the power switches.The measurements show an output voltage ripple of 38 mV and 16 mV for chaotic mode and standard mode operations, respectively.Compared to the output voltage ripple when the converter operates in PFM mode (Figure 17b), the ripple of the converter in PWM chaotic mode is approximately the same.This can be solved by increasing the capacitor value at the output but that increases the power module and adds additional costs.However, compared to the active EMI reduction with an input filter, this scheme is still much better, and therefore, it can be used for many applications.For a further demonstration, we conducted an experiment in which we increased COUT to 4.7 uF.The output voltage ripple decreased from 38 mV to 27 mV (approximately equal to the output voltage ripple when the converter enters PFM mode at a light load).It should be noted that this might result in instability.As a consequence, the compensation network should be redesigned to balance EMI performance with other factors, depending on the specific application.

Conclusions
In this paper, we have proposed and implemented a SiP buck converter with a fully on-chip chaotic triangular ramp generator for EMI reduction.The on-chip chaotic triangular ramp generator is constructed from an N-shaped chaos generator linked with a symmetrical triangular ramp generator.The on-chip chaos generator generates a controllable chaotic signal and applies it to modulate the slope of the triangular signal.The proposed modulated triangular signal based on the N-shaped chaotic circuit is then applied to the spread-spectrum control of a dual-mode PFM/PWM SiP buck converter with EMI reduction.To verify the effectiveness of the proposed scheme, the proposed EMI-improved buck converter was fabricated in a standard 0.18 µm CMOS process, and the experimental results verified the effectiveness of the proposed technique.The proposed scheme experimentally achieved up to 14.53 dB EMI reduction.In the simulation, extending the spread-spectrum bandwidth increased the EMI reduction amount to 19.13 dB with a 20% deviation in the switching frequency.The modulated triangle signal reduces the inductor current imbalance when the converter operates in chaotic mode.Therefore, the magnitude of the output voltage ripple and inductor current ripple of our design is lower than that in other works.This relaxes the required LC value for the output filter of the DC-DC converter.Due to its simplicity of implementation, high EMI improvement, and LC size relaxation, the proposed scheme can effectively solve EMI issues in many applications, especially on-chip and in-package solutions.

Figure 1 .
Figure 1.System-in-package (SiP) buck converter with chaos-based electromagnetic interference (EMI) reduction.The highlighted chaotic ramp and clock generator forces the converter to operate in chaotic mode for EMI reduction.

Figure 1 .
Figure 1.System-in-package (SiP) buck converter with chaos-based electromagnetic interference (EMI) reduction.The highlighted chaotic ramp and clock generator forces the converter to operate in chaotic mode for EMI reduction.

Figure 2 .
Figure 2. Proposed scheme for synthesizing a chaotic pulse-width modulation (PWM) signal with an N-shaped chaotic generator for a buck converter using a type-III compensator network.

Figure 2 .
Figure 2. Proposed scheme for synthesizing a chaotic pulse-width modulation (PWM) signal with an N-shaped chaotic generator for a buck converter using a type-III compensator network.

Figure 3 .
Figure 3. Simplified block diagram of the proposed N-shaped chaos generator.

Figure 3 .
Figure 3. Simplified block diagram of the proposed N-shaped chaos generator.

Figure 4 .
Figure 4. Operation of the N-shaped-based chaos generator: (a) Finite state machine.(b-d) Capacitor voltage waveform.

Figure 4 .
Figure 4. Operation of the N-shaped-based chaos generator: (a) Finite state machine.(b-d) Capacitor voltage waveform.

Figure 5 .
Figure 5. Bifurcation diagram versus T2 of the mathematical model of the proposed N-shaped chaos generator.The range of T2 associated with the dense area of the diagram shows chaotic behavior and can be used later to design Complementary Metal Oxide Semiconductor (CMOS) chaotic circuit.

Figure 5 .
Figure 5. Bifurcation diagram versus T 2 of the mathematical model of the proposed N-shaped chaos generator.The range of T 2 associated with the dense area of the diagram shows chaotic behavior and can be used later to design Complementary Metal Oxide Semiconductor (CMOS) chaotic circuit.

Figure 8 .Figure 9 .
Figure 8. Steady-state time-domain simulation results of the converter in chaotic mode using chaotic triangular ramp generator with slope modulation.

Figure 8 .
Figure 8. Steady-state time-domain simulation results of the converter in chaotic mode using chaotic triangular ramp generator with slope modulation.

Figure 8 .Figure 9 .
Figure 8. Steady-state time-domain simulation results of the converter in chaotic mode using chaotic triangular ramp generator with slope modulation.

Figure 9 .
Figure 9. Operation mode of buck converter under phase-portrait view between two internal states (output voltage and inductor current): (a) Standard mode.(b) Chaotic mode.

Figure 15 .
Figure 15.Experimental setup of the monolithic EMI-improved SiP buck converter.R is the current biasing current resistor of the V-I converter for the triangular ramp generator, and the VBR, VHC, and VLC of the triangular ramp generator are easy to tune.

Figure 15 .
Figure 15.Experimental setup of the monolithic EMI-improved SiP buck converter.R is the current biasing current resistor of the V-I converter for the triangular ramp generator, and the V BR , V HC , and V LC of the triangular ramp generator are easy to tune.

Figure 18 .
Figure 18.Measurement result of the fabricated chip: (a) Inductor current of the standard mode (top) and chaotic mode (bottom) (measurement mode: AC coupling @DC level: 0 V); (b) Power spectrum calculation results.

Figure 18 .
Figure 18.Measurement result of the fabricated chip: (a) Inductor current of the standard mode (top) and chaotic mode (bottom) (measurement mode: AC coupling @DC level: 0 V); (b) Power spectrum calculation results.

Figure 19 .
Figure 19.Conducted emission measurement of the buck converter.

Figure 19 .
Figure 19.Conducted emission measurement of the buck converter.

Figure 20 .
Figure 20.Measured power conversion efficiency at standard fixed-frequency mode and chaotic frequency mode with FSW +/− 10%.The maximum power efficiency reduction of 2% is at 450 mA of load current.

Figure 20 .
Figure 20.Measured power conversion efficiency at standard fixed-frequency mode and chaotic frequency mode with F SW +/− 10%.The maximum power efficiency reduction of 2% is at 450 mA of load current.

Figure 20 .
Figure 20.Measured power conversion efficiency at standard fixed-frequency mode and chaotic frequency mode with FSW +/− 10%.The maximum power efficiency reduction of 2% is at 450 mA of load current.

Table 1 .
Designed buck converter specifications.

Table 1 .
Designed buck converter specifications.

Table 2 .
List of component values used in test setup.

Table 2 .
List of component values used in test setup.

Table 3 .
EMI reduction performance of the proposed scheme and stage-of-the-art alternatives.

. Implementation Method Modulation Technique EMI Reduction Switching Frequency Compatibility for On-Chip Integration
1Extracted from figure; 2 Δf is not determined.

Table 3 .
EMI reduction performance of the proposed scheme and stage-of-the-art alternatives.
1Extracted from figure; 2 ∆f is not determined.