PVT-Robust CMOS Programmable Chaotic Oscillator : Synchronization of Two 7-Scroll Attractors

Victor Hugo Carbajal-Gomez 1,2,† , Esteban Tlelo-Cuautle 3,†,* , Carlos Sanchez-Lopez 1,† and Francisco Vidal Fernandez-Fernandez 4,† 1 Department of Electronics, Universidad Autónoma de Tlaxcala, Apizaco Tlaxcala 90300, Mexico; victhug26@gmail.com (V.H.C.-G.); carlsanmx@yahoo.com.mx (C.S.-L.) 2 Faculty of Electronic Sciences, Benemérita Universidad Autónoma de Puebla, Puebla 72570, Mexico 3 Department of Electronics, INAOE, Puebla 72840, Mexico 4 Instituto de Microelectrónica de Sevilla, CSIC and Universidad de Sevilla, 41092 Sevilla, Spain; pacov@imse-cnm.csic.es * Correspondence: etlelo@inaoep.mx; Tel.: +52-222-2663100 † These authors contributed equally to this work.


Introduction
Chaotic systems have been studied for a long time and nowadays many examples of electronic implementations using discrete devices can be found in the literature.However, the big challenge remains the generation of multi-scroll attractors and their design using CMOS integrated circuit (IC) technology to develop real life applications.For instance, the control and synchronization of chaotic systems were first proposed no more than three decades ago [1][2][3][4][5][6][7], from which some practical developments have impacted areas such as high-performance circuit design (e.g., delta-sigma modulators and power converters), liquid mixing, chemical reactions, biological systems (e.g., sensing signals produced in the human brain, heart or other organs), power electronics, secure communication systems, etc. [8][9][10][11][12][13].That way, this new and challenging line for research and development is becoming highly inter-disciplinary, involving systems and control engineers, theoretical and experimental physicist, applied mathematicians, physiologists and, above all, IC design specialists.
From the electronic design point of view, the majority of chaotic oscillators are based on the traditional voltage operational amplifier [26].However, there are many drawbacks related to this approach, such as requiring a high number of amplifiers and passive elements for its design, they have low frequency response, and require high voltage biases up to ±18 V. On the other hand, as already shown in [15,16], the good option to design CMOS chaotic oscillators is by using operational transconductance amplifiers (OTAs), which are biased using low voltages of around ±1.65 V or lower, and they provide higher frequency response than voltage amplifiers.However, the challenge in IC design is the generation of multi-scroll attractors, for which up to now the highest number of scrolls that have been generated is five [27,28].In this manner, we introduce a CMOS design of a seven-scroll attractor that is based on a new current-mode PWL function that can be programmed to generate 2-7-scroll attractors.We performed post-layout simulations using 0.35 µm CMOS technology from AMS to guarantee robustness to process-voltage-temperature (PVT) variations.We also show the synchronization of two seven-scroll attractors to highlight that the proposed CMOS design can be suitable to develop applications in security and Internet of Things (IoT).
The rest of this article shows the CMOS design of a chaotic oscillator using OTAs and a new programmable current-mode PWL function to generate up to seven scrolls.The chaotic oscillator has four coefficients that have been optimized in [29][30][31][32] to provide a high maximum Lyapunov exponent (MLE).Section 2 lists feasible solutions providing different values of MLE.It is worth mentioning that the seminal work in [33] introduced the first algorithm to compute Lyapunov exponents from experimental chaotic time series.Afterwards, other authors introduced different approaches to compute MLE [34][35][36][37][38]. Section 3 details the design of the OTA that allows programmability of the transconductance, and introduces our proposed current-mode PWL function.The whole CMOS chaotic oscillator is introduced in Section 4, where we detail the programmability of the current-mode PWL function.Section 5 shows the master-slave synchronization of two CMOS chaotic oscillators.The layout of the chaotic oscillator has been performed using 0.35 µm CMOS technology, as shown in Section 6, where we highlight post-layout simulations including PVT variations for the synchronization of two seven-scroll chaotic attractors using generalized Hamiltonian forms and observer approach.Finally, the conclusions are listed in Section 7.

OTA-Based Chaotic Oscillator Using a CMOS Programmable Current-Mode PWL Function
Chaotic oscillators have a complex dynamical behavior that is associated to their high sensitivity to small variations in the initial conditions.They also have bounded trajectories in the phase space.They possess at least one MLE and have a continuous power spectrum [39][40][41][42][43][44][45][46].Chaotic oscillators can be described by the state-space approach given by where the dot denotes differentiation with respect to time and the functions f() and h() are in general nonlinear.In Equation (1), the variety of possible nonlinear functions is infinite, but, in some cases, they can be approached by PWL functions leading to the state-space representation given by where A, B, C and D are matrices (possibly time-dependent) of appropriate dimensions.If the input vector u is fixed or equals zero, the model describes an autonomous dynamical system.Lets us consider the multi-scroll chaotic oscillator modeled by [26]: where a, b, c, and d 1 are real and positive constants, and f (x 1 ) models a saturated nonlinear function (SNLF) series that can be approached by a PWL function, as already shown in [23,26,47,48].
In Equation ( 3), the coefficients a, b, c, and d 1 must have appropriate values to estimate the quality of chaotic behavior [49,50].For example, one can evaluate Lyapunov exponents, Kaplan-York dimension and entropy.In this work.we focus on evaluating Lyapunov exponents, which are asymptotic measures characterizing the average rate of growth (or shrinkage) of small perturbations to the solutions of a dynamical system [38], and provide quantitative measures of sensitivity of the system response to small changes in initial conditions [35].
The Lyapunov exponents λ i can be computed by applying numerical methods [35,36,41].Furthermore, the optimization of Equation ( 3) requires varying the coefficients to obtain high values of MLE, as already demonstrated in [31].For instance, in [51], three meta-heuristics (genetic algorithms (GA), differential evolution (DE), and particle swarm optimization (PSO)) have been applied to optimize MLE.When the coefficient values are fixed to 0.7, as already done in [26,52], the MLE value is 0.105422 to generate two-scroll, 0.138087 to generate three scrolls, 0.142087 to four scrolls, 0.134534 to five scrolls, 0.147785 to six scrolls, and 0.148159 to generate seven scrolls.However, after applying GA, DE and PSO, the optimized MLE values increase according to Table 1, where we list the mean value, standard deviation and coefficient values to generate two to seven scrolls.
The goal of this article is the introduction of a current-mode PWL function to design the chaotic oscillator in Equation (3), using CMOS technology to program the generation of 2-7-scroll attractors.That way, Table 1 is the reference to design the CMOS OTAs to accomplish the values of the coefficients a, b, c, and d 1 .According to Trejo-Guerra et al. [14], there are very few integrated designs presented in the literature with this purpose, and they only generate up to five-scroll attractors.In this article, we highlight the design of a CMOS programmable current-mode PWL function to generate up to seven-scroll.The main idea is sketched in Figure 1, where the PWL function is generated from an input voltage (V + in − V − in ) to provides an output current I q .This PWL function can be generated in either voltage-mode h v () or current-mode h i ().This article details the CMOS design of the current-mode PWL function labeled as saturated nonlinear function (SNLF) in Figure 2, which shows the OTA-capacitor (g m − C) implementation of Equation (3), where the state variables are x 1 , x 2 and x 3 .By applying Kirchhoff's current law to Figure 2, one gets Equation ( 4), where SNLF is described by f (x 1 ), and the equations resemble the original ones defined by Equation (3).The operating frequency is evaluated by

CMOS Design of the OTA Enabling the Proposed Current-Mode PWL Function
Figure 3 shows the CMOS topology of the OTA that is designed herein and allows programmability of its transconductance g m .Its CMOS design combines a differential pair with source degeneration to linearize g m , which is tuned by the feedback resistors R that are designed as active loads using MOSFETs controlled by voltage V c , as shown in Figure 4.
. CMOS design of resistors R in Figure 3, allowing programmability of g m through V c .
Looking at Table 1, the values of the optimized coefficients a, b and d 1 are in the range [0.5, 1], and coefficient c in the range [0.19, 0.5].Therefore, to implement all those combinations of coefficients, the OTA for the former case is designed herein with a central transconductance of g m = 200 µA/V, and with a tunable range of ±50 µA/V.Considering the ranges of coefficient c, the OTA is designed with a central transconductance of g m = 50 µA/V, and with a tunable range of ±50 µA/V.Another OTA is designed to accomplish the slope k ≥ 10 required by the PWL function, with a central transconductance of g m = 2 mA/V, and with a tunable range of ±500 µA/V.According to Equation (4), to implement the coefficients to generate seven scrolls (see Table 1, where [a, b, c, d 1 ] = [0.93,0.52,0.21,0.96]),we select gm x = gm y = gm z = 200 µA/V, gm a = 186 µA/V, gm b = 104 µA/V, gm c = 41 µA/V and gm d = 1.92 mA/V.
The sizes of the OTA having a central value of g m = 200 µA/V are listed in Table 2. Table 3 lists its electrical characteristics.The g m is tuned by the feedback resistors R controlled by V c in the range [−5 V, −3 V].The sizes of the MOSFETs for the active loads R are: M p1 -M p4 , L = 2.1 µm, W = 3.8 µm, and the multiplication factor M = 4.
The sizes for the OTA designed with a central transconductance of g m = 50 µA/V, are also listed in Table 2, and Table 3 lists its performance characteristics.These OTAs with centered transconductances at g m = 200 µA/V and g m = 50 µA/V are used to tune the coefficient values a, b, c, and d 1 listed in Table 1.The integrators and PWL function also require OTAs with transconductance centered at g m = 2 mA/V.In this case, the transistor sizes are listed in Table 2, and Table 3 lists its performance characteristics.PWL techniques have been used extensively in circuits and systems theory to model nonlinear characteristics of electronic devices [53,54], and to study a large class of nonlinear resistive networks [55,56].A SNLF series can be generated using the CMOS topology shown in Figure 5 to generate the PWL function that allows programmability of the break-points by tuning the currents Ioff in , Ioff out and I sat to implement the required plateaus and slopes.This approach has the following advantages: (1) the current mode circuits are in open loop configuration, being unconditionally stable; (2) the current mode blocks have high frequency performance; (3) the simplicity and modularity of the current-mode blocks make them very appropriate to approach a PWL function; (4) a small number of transistors is required for each block; and (5) the current mode blocks allow programmability of the breakpoints for each segment of the PWL function.It should be noted that, to generate a slope k = 10, it is necessary to inject an input signal I in = 10 × I in .All transistors have sizes L = 0.7 µm and W = 3.5 µm, but the multiplicity is 4 for M 1 , M 3 − M 4 and 12 for M 2 .

Integrated Multi-Scroll Chaotic Oscillator Using the Proposed Current Mode PWL Function
The majority of CMOS chaotic oscillators are based on OTAs.For example, the authors in [57] highlighted the benefits of low-voltage implementation, integrability and electronic tunability.Following this direction, in this work, we highlight the programmability of the PWL function enabled through current mode cells and the transconductances of the OTAs to tune the fractional values of the coefficients a, b, c, and d 1 listed in Table 1.By using the current mode cell shown in Figure 5, we propose the CMOS design sketched in Figure 6 to generate 2-7 scrolls by programming the parallel connection of all the saturated blocks.The current mode blocks are modified by the shift currents Ioff in and Ioff out .The saturated regions are limited by the bias current Isat.That way, to connect n − 1 current mode blocks to generate n-scroll, a 3-8-bit decoder is designed.As one sees, the input currents to each current mode block are copies of the input current I in , generated from the class AB current mirror shown in Figure 7.To generate seven scrolls, six copies of the input current are required.The transistor sizes of the multi-output current mirror using 0.35 µm CMOS process from AMS are listed in Table 4.The electrical characteristics are: current gain of 1.005, dynamic range of ±2 mA, R in = 1.168KΩ, R out = 748.4KΩ, and I o f f set = 1.28 µA.PVT variation simulations are performed to verify the robustness of our proposed current mode block using the BSIM3v3 model.The tested corners are: (NMOS-PMOS) typical-typical, fast-fast, fast-slow, slow-fast, and slow-slow (TT, FF, FS, SF, and SS, respectively) of the 0.35µm CMOS technology.The temperature is swept from −20 • C to 100 • C in steps of 40 • C. Figures 8 and 9 show the PVT simulation results.Figure 10 shows the proposed circuit used to tune I o f f in shown in Figure 6.Its sizes are listed in Table 5. Figure 11 shows the proposed circuit to tune I sat and I o f f out , and the transistor sizes are listed in Table 6.Table 7 shows the digital control word and the activation outputs of the 3-to-7-bit digital decoder, which is designed to select the number of current mode building blocks in Figure 6 for the generation of 2-7 scrolls.The output functions are shown in Figure 12, where   Table 5. Sizes of the circuit in Figure 10.
A PWL function to generate two scrolls is implemented by setting the decoder inputs to logic A, B, C = [0, 0, 1], i.e., 1 = 1.65v and 0 = −1.65v.For this last case, we show the simulation results in Figures 13-15, respectively, to conclude that, with adjustment of the current shifts, our proposed current mode PWL function is robust to PVT variations and allows for programmability to choose any value between two-and seven-scroll attractors.

Master-Slave Synchronization of Two Chaotic Oscillators
Chaos synchronization is an important problem in nonlinear science.During the last three decades, synchronization has received a great interest among various scientists [1][2][3][4][5][6][7].The synchronization can be seen as the property shared by some objects to express a uniform rate of coexistence.For example, two harmonic oscillators can be synchronized if their periods are equal.However, for the case of chaotic oscillators, the concepts of frequency and phase are not well defined and, therefore, two chaotic oscillators can be synchronized if eventually, after a transitional time (a long or short time span), the oscillations coincide exactly at all times despite both oscillators started at different initial conditions.
The idea of synchronizing two identical chaotic systems from different initial conditions was introduced in the seminal work in [1].After that, several synchronization schemes were introduced in [50,[58][59][60][61][62][63][64][65][66].Besides, the practical applications of chaotic synchronization has some limitations to accomplish identical synchronization.For example, parameter mismatch will probably destroy the manifold of a synchronization.To deal with this issue, generalized synchronization approaches were introduced [3,67].In this manner, we perform the synchronization of two chaotic oscillators following the approach given in [3].Therefore, the chaos generator model from Equation (3) in Generalized Hamiltonian form, is given by The Hamiltonian energy function can be described by and the gradient vector can be described by The destabilizing vector field calls for x 1 and x 2 signals to be used as the outputs of the master model (Equation ( 5)).The matrices C, S, and I are given by The pair (C, S) is observable.Therefore, the nonlinear state observer for Equation ( 5) to be used as the slave model is designed as The gains k i , i = 1, 2, 3 must be selected to guarantee asymptotic exponential stability to zero of the state reconstruction error trajectories (i.e., synchronization error e(t)).From Equations ( 5) and ( 7), the synchronization error dynamics is governed [21] by By setting K = (k 1 , k 2 , k 3 ) T with k 1 = 2, k 2 = 5, k 3 = 7, and considering the initial condition X(0) = [0, 0, 0.1], ξ(0) = [1, −0.5, 3], we performed numerical simulations by using ode45 in MATLAB, with a time integration of T = 2000 to generate four scrolls.Figure 16 shows the state trajectories of the master and slave models described by Equations ( 5) and (7), respectively, and their synchronization.The coincidence of the states is represented by a straight line with a unity-slope in the phase plane of each state.The synchronization error is also shown in their transient evolution.
The proposed scheme for the synchronization of multi-scroll chaotic oscillators of the form shown in Equation (3) using OTAs is shown in Figure 17.The vector K in Equation ( 7) is the observer gain and it is adjusted by selecting the value of the OTA gm sync according to the sufficient conditions for synchronization given in [3].In all our simulations, the values of the transconductances were evaluated as: gm f = gm x = gm y = gm z = 200 µA/V, and we used the values for a, b, c, d 1 from the cases listed in Table 1 for the PSO algorithm.Those values are tuned from the OTAs with these equations: g ma = ag m f , g mb = bg m f , g mc = cg m f , and g md = d 1 g m f .

Layout and Post-Layout Simulations of the Synchronization of Two Multi-Scroll Chaotic Oscillators
The layout of our proposed CMOS programmable current-mode PWL function in Figure 6 is shown in Figure 18.It is used in the complete layout of the OTA-based CMOS multi-scroll chaotic oscillator shown in Figure 19.The dimension of the silicon area is 900 µm × 350 µm.A total of 2005 elements and 175 nodes were required, and a total of 21 inputs/outputs were considered to design the pad frame that contains a protection diode, Vdd, Vss and open contacts to connect the manufactured designs.A 20 pF parasitic capacitance associated to an oscilloscope was included at the outputs of the state variables, and an external integrator capacitance of C = 30pF was used, calculated to correspond to a 636.62 kHz dominant frequency.Higher frequencies of chaotic oscillation can be reached using bipolar technology [68] to compete with digital implementations [69].In Figure 20, it can be seen the good synchronization for all the cases when plotting the state variables of the master oscillator x vs. the slave oscillator ξ.This leads us to conclude that these multi-scroll chaotic attractors are robust to PVT variations, they allow programmability to generate 2-7 scrolls, and therefore are quite suitable for the development of applications like chaotic secure communication systems.

Conclusions
We have introduced a new CMOS current-mode programmable PWL function using 0.35 µm CMOS technology of AMS.It is used to design a CMOS chaotic oscillator that can be programmed to generate 2-7-scroll attractors.The coefficients a, b, c, d 1 of this chaotic oscillator were tuned by designing programmable OTAs.Using two chaotic oscillators, we showed the implementation of a synchronized master-slave topology, performed by generalized Hamiltonian forms and observer approach.
It was highlighted that the required PWL function, considered as a saturated nonlinear function (SNLF) series, can be implemented in current-mode, and one can take control of the break-points and slopes of the linear segments.The simulation results showed that our CMOS multi-scroll chaotic oscillator is robust to PVT variations.Finally, the simulations performed after the layout parasitic extraction, and the five PVT corner analysis and four temperatures (−20 • C, 20 • C, 60 • C and 100 • C), demonstrate the suitability of our proposed CMOS chaotic oscillator to be in engineering applications, such as chaotic secure communication systems, healthcare informatics, security, Internet of Things, and so on.These practical applications require low-power consuming circuits, such as our proposed CMOS chaotic oscillator that is also quite suitable to enhance wireless systems.

Figure 1 .Figure 2 .
Figure 1.Voltage-to-current implementations of the PWL function in: voltage-mode h v (); and current-mode h i ().

Figure 3 .
Figure 3. CMOS OTA that allows programmability of g m .

Figure 5 .
Figure 5. CMOS design of the PWL function by cascading simple current mirrors.

Figure 10 .
Figure 10.Proposed circuit to tune Io f f in in Figure 6.

Figure 11 .
Figure 11.Proposed circuit to tune Isat and Io f f out in Figure 6.

Figure 12 .
Figure 12.Logic gates to implement the decoder.

Figure 13 .
Figure 13.PVT simulation of the proposed PWL function to generate seven-scroll: (a,b) without adjustment of the current offsets; and (c,d) with adjustment of the current offsets.

Figure 15 .
Figure 15.Temperature variations of the proposed PWL function in time simulation to generate seven-scroll: (a) TT; (b) SF; (c) FS; (d) SS; and (e) FF corner.

Figure 16 .
Figure 16.Master-slave synchronization of two four-scroll chaotic attractors with a = b = c = d 1 = 0.7: (a) master oscillator; (b) slave oscillator; (c) error synchronization; and (d) error phase diagram for the states of the master x and the slave ξ.

Figure 17 .
Figure 17.Synchronization of two multi-scroll chaotic attractors implemented with OTAs and with our proposed current mode PWL function described by the block SNLF.

Figure 19 .
Figure 19.Multi-scroll chaotic oscillator layoutThe layout of the CMOS multi-scroll chaotic oscillator was designed by using Tanner suite version 16.2, and the post-layout simulations demonstrate that effectively we can program the proposed CMOS current-mode PWL function to generate 2-7 scrolls, as shown in Figure20.External integration capacitances are used to control the spectra scaling of the system.A 0.5 pF parasitic capacitance and an inductor L = 2nH have been introduced in the simulation at the outputs of the state variables, which resemble the internal IC parasitic elements of the circuit and the pad frame.A 20 pF parasitic capacitance associated to an oscilloscope was included at the outputs of the state variables, and an external integrator capacitance of C = 30pF was used, calculated to correspond to a 636.62 kHz dominant frequency.Higher frequencies of chaotic oscillation can be reached using bipolar technology[68] to compete with digital implementations[69].In Figure20, it can be seen the good synchronization for all the cases when plotting the state variables of the master oscillator x vs. the slave oscillator ξ.This leads us to conclude that these multi-scroll chaotic attractors are robust to PVT variations, they allow programmability to generate 2-7 scrolls, and therefore are quite suitable for the development of applications like chaotic secure communication systems.

Table 2 .
Sizes of the OTA with different multiplicity (M) for the g m centered at 200 µA/V, 50 µA/V and 2 mA/V.

Table 3 .
Performance ranges of the programmable OTAs with g m centered at 200 µA/V, 50 µA/V and 2 mA/V.

Table 4 .
Proposed programmable CMOS current mode PWL function to generate from two to seven scrolls.Replication of the input current I in .Sizes of the current mirror shown in Figure7.

Table 6 .
Sizes of the circuit in Figure11.
A B C O