Effects of Gate-Length Scaling on Microwave MOSFET Performance

This paper focuses on the extraction of an accurate small-signal equivalent circuit for metal-oxide-semiconductor field-effect transistors (MOSFETs). An analytical modeling approach was developed and successfully validated through the comparison between measured and simulated scattering parameters. The extraction of the equivalent circuit elements allowed for the estimation of the intrinsic unity current-gain cutoff frequency, which is a crucial figure of merit for assessing the high-frequency performance. The experimental data show that the cutoff frequency of the tested devices exhibits a nearly ideal scaling behavior with decreasing gate length.


Introduction
The extraction of an accurate small-signal equivalent circuit is of great importance for evaluating microwave field-effect transistor (FET) performance.This is because the equivalent circuit provides a physically meaningful description of the physical device structure.Furthermore, the extraction of the circuit elements allows for the estimation of relevant figures of merit, such as the intrinsic unity current-gain cutoff frequency (f T ).The determination of this figure of merit is essential to assess the potential of the device for high-frequency operation.Driven by the ever-growing demand for high-frequency applications, continuous efforts are being made to develop innovative materials and architectures (e.g., high-mobility III-V and Ge channels, high-k dielectrics, and multiple-gates) [1][2][3][4][5].The intrinsic f T is expected to remarkably increase with decreasing gate length and to be roughly independent of the gate width.Hence, a significant improvement of the high-frequency performance can be achieved with gate-length downscaling.Typically, the equivalent circuit is extracted from scattering (S-) parameters, which can be straightforwardly and accurately measured with a vector network analyzer.To accomplish this goal, several numerical optimization [6][7][8][9] and analytical [10][11][12][13][14][15][16] procedures have been proposed in the last four decades.The numerical optimization approach can yield non-physical values of the circuit elements, by which the results can critically depend on the initial element values, local minima, and the optimization technique itself.These drawbacks can be overcome by adopting the analytical approach that is based on first extracting the extrinsic bias-independent elements, then de-embedding their contributions with simple matrix manipulations, and finally calculating the intrinsic bias-dependent elements from the intrinsic admittance (Y-) parameters.The determination and subsequent de-embedding of the extrinsic elements is essential to access the performance of the intrinsic FET that is not directly measurable, since the intrinsic section of the FET is experimentally inaccessible.The extrinsic elements are usually determined using "cold" S-parameter measurements (V DS = 0 V, i.e., passive device) [10][11][12][13][14][15][16], passive test structures [13][14][15][16][17], and full-wave electromagnetic simulations [18][19][20][21].In practice, the "cold" approach is the most used, since it does not require additional dummy structures or detailed information about the FET layout.
The present study aims to develop an analytical modeling technique to determine a small-signal equivalent circuit for three metal-oxide-semiconductor field-effect transistors (MOSFETs) with different gate lengths.In particular, the extrinsic capacitances are obtained from S-parameters measured on an open structure, whereas the extrinsic resistances and inductances are determined from "cold" S-parameter measurements.The open structure is used to extract the extrinsic capacitances, since the standard "cold" approach does not allow distinguishing clearly between extrinsic and intrinsic output capacitances [10,22].The de-embedding of the extrinsic elements enables the calculation of the intrinsic elements, thereby allowing the estimation of f T and the analysis of the impact of the gate-length scaling on this figure of merit.It is noteworthy that a lossy substrate resistance is included in the intrinsic model in order to obtain good agreement between the measured and simulated output reflection coefficient.
The remainder of this paper is structured as follows: the next section contains a description of the tested devices and of the proposed modeling technique, the subsequent section discusses the experimental results, and the last section summaries the main conclusions of this study.

Model Extraction
The tested devices are three multi-cell, multi-finger MOSFETs with a gate width of 192 µm (W = 16 × 4 × 3, 8 × 4 × 6, and 8 × 4 × 6 µm) and different gate lengths (L g = 0.25, 0.5, and 1 µm).The measured DC output characteristics are reported in Figure 1.As can be observed, a quite good scaling of the drain current is achieved.This is highlighted in Figure 2, showing that the drain current and transconductance increase roughly linearly with inverse gate length.Although the extrinsic contributions imply a reduction of the transconductance, both extrinsic and intrinsic transconductances (g mExtrDC and g mDC ) exhibit good scaling.It should be underlined that the scaling of DC and RF properties are strongly correlated with each other, since RF performance strongly depends on the associated DC bias point.
The present study aims to develop an analytical modeling technique to determine a small-signal equivalent circuit for three metal-oxide-semiconductor field-effect transistors (MOSFETs) with different gate lengths.In particular, the extrinsic capacitances are obtained from S-parameters measured on an open structure, whereas the extrinsic resistances and inductances are determined from "cold" S-parameter measurements.The open structure is used to extract the extrinsic capacitances, since the standard "cold" approach does not allow distinguishing clearly between extrinsic and intrinsic output capacitances [10,22].The de-embedding of the extrinsic elements enables the calculation of the intrinsic elements, thereby allowing the estimation of fT and the analysis of the impact of the gate-length scaling on this figure of merit.It is noteworthy that a lossy substrate resistance is included in the intrinsic model in order to obtain good agreement between the measured and simulated output reflection coefficient.
The remainder of this paper is structured as follows: the next section contains a description of the tested devices and of the proposed modeling technique, the subsequent section discusses the experimental results, and the last section summaries the main conclusions of this study.

Model Extraction
The tested devices are three multi-cell, multi-finger MOSFETs with a gate width of 192 μm (W = 16 × 4 × 3, 8 × 4 × 6, and 8 × 4 × 6 μm) and different gate lengths (Lg = 0.25, 0.5, and 1 μm).The measured DC output characteristics are reported in Figure 1.As can be observed, a quite good scaling of the drain current is achieved.This is highlighted in Figure 2, showing that the drain current and transconductance increase roughly linearly with inverse gate length.Although the extrinsic contributions imply a reduction of the transconductance, both extrinsic and intrinsic transconductances (gmExtrDC and gmDC) exhibit good scaling.It should be underlined that the scaling of DC and RF properties are strongly correlated with each other, since RF performance strongly depends on the associated DC bias point.Figure 3 illustrates the small-signal equivalent circuit that is used to reproduce the measured Sparameters of the tested MOSFETs.This circuit can be divided into two main sections: the extrinsic and intrinsic parts.The extrinsic section is composed by eight bias-independent elements (Cpg, Cpd, Lg, Ls, Ld, Rg, Rs, and Rd), while the intrinsic section consists of eight bias-dependent elements (Cgs, Cgd, Cds, Rgs, Rds, Rsub, gm, and τ).In order to take into account the distributed effects, the extrinsic capacitances are split into two equal parts, placed outermost and innermost of the three extrinsic inductances.The extrinsic capacitances Cpg and Cpd are straightforwardly extracted from the imaginary parts of the Yparameters of an open structure that has been fabricated on the same die of the same wafer of the tested MOSFETs.In general, the open structure can be represented with a pi network composed of three capacitances modeling the capacitive coupling between the pads.In most cases, as in the present one, the feedback capacitance can be disregarded, thereby allowing the determination of the input and output capacitances from the imaginary parts of Y11 and Y22, respectively.As illustrated in Figure 4, the extrinsic capacitances are extracted by using the frequency range from 0.3 to 10 GHz.After removing the effects of Cpg and Cpd, the extrinsic resistances and inductances are, respectively, obtained from the real and imaginary parts of Z-parameters with VDS = 0 V and VGS >> VTH by using the frequency range from 10 to 40 GHz.Under this bias condition, the intrinsic section of the MOSFET can be modeled through a distributed channel resistance and a distributed gate capacitance, leading to the following expressions of the Z-parameters [13]: (2) where Cg and Rch are the gate capacitance and the channel resistance, respectively.
By assuming Rch to be proportional to 1/(VGS-VTH) at "cold" condition [13], the extrinsic resistances can be straightforwardly determined from the intercept coefficients of the three linear regressions of Re(Zij) versus 1/(VGS-VTH) (see Figure 5).In order to minimize the frequency dependence of Re(Zij) associated with an incomplete capacitance de-embedding and/or intrinsic capacitive effects, Re(Zij) is obtained at each gate voltage from the slope of the straight line approximating ω 2 Re(Zij) Figure 3 illustrates the small-signal equivalent circuit that is used to reproduce the measured S-parameters of the tested MOSFETs.This circuit can be divided into two main sections: the extrinsic and intrinsic parts.The extrinsic section is composed by eight bias-independent elements (C pg , C pd , L g , L s , L d , R g , R s , and R d ), while the intrinsic section consists of eight bias-dependent elements (C gs , C gd , C ds , R gs , R ds , R sub , g m , and τ).In order to take into account the distributed effects, the extrinsic capacitances are split into two equal parts, placed outermost and innermost of the three extrinsic inductances.The extrinsic capacitances C pg and C pd are straightforwardly extracted from the imaginary parts of the Y-parameters of an open structure that has been fabricated on the same die of the same wafer of the tested MOSFETs.In general, the open structure can be represented with a pi network composed of three capacitances modeling the capacitive coupling between the pads.In most cases, as in the present one, the feedback capacitance can be disregarded, thereby allowing the determination of the input and output capacitances from the imaginary parts of Y 11 and Y 22 , respectively.As illustrated in Figure 4, the extrinsic capacitances are extracted by using the frequency range from 0.3 to 10 GHz.After removing the effects of C pg and C pd , the extrinsic resistances and inductances are, respectively, obtained from the real and imaginary parts of Z-parameters with V DS = 0 V and V GS >> V TH by using the frequency range from 10 to 40 GHz.Under this bias condition, the intrinsic section of the MOSFET can be modeled through a distributed channel resistance and a distributed gate capacitance, leading to the following expressions of the Z-parameters [13]: where C g and R ch are the gate capacitance and the channel resistance, respectively.By assuming R ch to be proportional to 1/(V GS − V TH ) at "cold" condition [13], the extrinsic resistances can be straightforwardly determined from the intercept coefficients of the three linear regressions of Re(Z ij ) versus 1/(V GS − V TH ) (see Figure 5).In order to minimize the frequency dependence of Re(Z ij ) associated with an incomplete capacitance de-embedding and/or intrinsic capacitive effects, Re(Z ij ) is obtained at each gate voltage from the slope of the straight line approximating ω 2 Re(Z ij ) versus ω 2 .The extrinsic inductances are extracted from the slopes of the straight lines approximating ωIm(Z ij ) versus ω 2 (see Figure 6).versus ω 2 .The extrinsic inductances are extracted from the slopes of the straight lines approximating ωIm(Zij) versus ω 2 (see Figure 6).After de-embedding all of the parasitic effects' elements by means of simple matrix operations, the intrinsic elements can be obtained from the intrinsic Y-parameters at each bias condition.It is versus ω 2 .The extrinsic inductances are extracted from the slopes of the straight lines approximating ωIm(Zij) versus ω 2 (see Figure 6).After de-embedding all of the parasitic effects' elements by means of simple matrix operations, the intrinsic elements can be obtained from the intrinsic Y-parameters at each bias condition.It is versus ω 2 .The extrinsic inductances are extracted from the slopes of the straight lines approximating ωIm(Zij) versus ω 2 (see Figure 6).After de-embedding all of the parasitic effects' elements by means of simple matrix operations, the intrinsic elements can be obtained from the intrinsic Y-parameters at each bias condition.It is versus ω 2 .The extrinsic inductances are extracted from the slopes of the straight lines approximating ωIm(Zij) versus ω 2 (see Figure 6).After de-embedding all of the parasitic effects' elements by means of simple matrix operations, the intrinsic elements can be obtained from the intrinsic Y-parameters at each bias condition.It is After de-embedding all of the parasitic effects' elements by means of simple matrix operations, the intrinsic elements can be obtained from the intrinsic Y-parameters at each bias condition.It is worth noting that, analogously to what has been done for fin field-effect transistors (FinFETs) [14], R ds , C ds , and R sub are determined from the real and imaginary part of the intrinsic Y 22 + Y 12 .In particular, R ds is calculated at low frequencies by treating the R sub C ds series network as an open circuit, and then its contribution is removed to enable the extraction of C ds and R sub : The introduction of R sub does not affect the calculation of the intrinsic f T , which is determined with the output short-circuited.The intrinsic unity current-gain cutoff frequency can be straightforwardly estimated from the intrinsic elements of the equivalent circuit as follows: This equation shows that f T is directly proportional to g m and inversely proportional to the total gate capacitance C gg , given by the sum of C gs and C gd .The capacitance C gg should be directly proportional to both gate width and gate length, while the conductance m should be directly proportional to the gate width and inversely proportional to the gate length.As a result, f T is expected to be inversely proportional to the square of the gate length and to be roughly independent of the gate width.However, deviations from this ideal behavior can be observed, due to non-ideal effects such as thermal phenomena and short channel effects.For example, f T can be found to inversely scale with the gate length, due to saturation velocity in short channel devices.In such a case, the cutoff frequency can be used to estimate the saturation velocity as 2πL g f T .Furthermore, under-and/or over-de-embedding of the extrinsic contributions may critically affect the results of the scaling analysis for the intrinsic section.

Model Validation and Discussion
The validity of the proposed technique is confirmed by the good agreement between the measured and simulated S-parameters.As an illustrative example, Figure 7 shows the comparison between the measured and simulated S-parameters from 0.3 to 40 GHz for the three tested devices at V GS = 1 V and V DS = 1 V.It should be highlighted that, by decreasing the gate length, the magnitude of the low-frequency forward transmission coefficient S 21 increases, due to the improvement of the transconductance, and the starting point of output reflection coefficient S 22 moves farther from the open circuit condition, due to the reduction of the drain-source resistance.This result can be easily explained by considering that, as the frequency tends to zero, the transconductance delay can be neglected and all inductors and capacitors can be, respectively, replaced with short and open circuits, and thereby S 21 and S 22 can be defined as follows [23]: where R 0 is the characteristic resistance (i.e., 50 Ω), while g mExtr and R dsExtr represent the extrinsic transconductance and drain-source resistance: To illustrate the necessity of including R sub in the model, Figure 8 shows that the measured S 22 is not accurately reproduced by disregarding R sub .As a matter of fact, R sub is required to add a resistive contribution in order to enhance the accuracy of the simulated S 22 .
Electronics 2017, 6, 62 6 of 10 To illustrate the necessity of including Rsub in the model, Figure 8 shows that the measured S22 is not accurately reproduced by disregarding Rsub.As a matter of fact, Rsub is required to add a resistive contribution in order to enhance the accuracy of the simulated S22.By focusing the analysis on the scaling of fT, Figure 9 shows that a significant improvement of fT is achieved with decreasing gate length.In particular, fT scales inversely with the square of the gate length, as in the ideal case.In agreement with the expectation, this result is due to the achieved good scaling of gm and Cgg with the gate length.Although Cgg is usually mostly determined by Cgs, Cgd has been considered to estimate fT, since its contribution becomes relevant by decreasing VDS and/or VGS.Furthermore, it is noteworthy that, although some slight discrepancy is observed with decreasing gate length, the achieved values of gm are very close to those of the intrinsic transconductance calculated from DC measurements, indicating that the low-frequency dispersion plays a negligible role (see Figure 10).For the sake of completeness, the scaling of fT, gm, and Cgg versus the gate length is analyzed under a wide range of bias conditions (see Figures 11 and 12).By fixing the input or the output voltage, a good scaling of fT with decreasing gate length is always obtained, due to the increase of gm and the reduction of Cgg.By focusing the analysis on the scaling of f T , Figure 9 shows that a significant improvement of f T is achieved with decreasing gate length.In particular, f T scales inversely with the square of the gate length, as in the ideal case.In agreement with the expectation, this result is due to the achieved good scaling of g m and C gg with the gate length.Although C gg is usually mostly determined by C gs , C gd has been considered to estimate f T , since its contribution becomes relevant by decreasing V DS and/or V GS .Furthermore, it is noteworthy that, although some slight discrepancy is observed with decreasing gate length, the achieved values of g m are very close to those of the intrinsic transconductance calculated from DC measurements, indicating that the low-frequency dispersion plays a negligible role (see Figure 10).For the sake of completeness, the scaling of f T , g m , and C gg versus the gate length is analyzed under a wide range of bias conditions (see Figures 11 and 12).By fixing the input or the output voltage, a good scaling of f T with decreasing gate length is always obtained, due to the increase of g m and the reduction of C gg .By focusing the analysis on the scaling of fT, Figure 9 shows that a significant improvement of fT is achieved with decreasing gate length.In particular, fT scales inversely with the square of the gate length, as in the ideal case.In agreement with the expectation, this result is due to the achieved good scaling of gm and Cgg with the gate length.Although Cgg is usually mostly determined by Cgs, Cgd has been considered to estimate fT, since its contribution becomes relevant by decreasing VDS and/or VGS.Furthermore, it is noteworthy that, although some slight discrepancy is observed with decreasing gate length, the achieved values of gm are very close to those of the intrinsic transconductance calculated from DC measurements, indicating that the low-frequency dispersion plays a negligible role (see Figure 10).For the sake of completeness, the scaling of fT, gm, and Cgg versus the gate length is analyzed under a wide range of bias conditions (see Figures 11 and 12).By fixing the input or the output voltage, a good scaling of fT with decreasing gate length is always obtained, due to the increase of gm and the reduction of Cgg.Finally, it should be pointed out that the achieved good scaling of the intrinsic performance of the tested devices implies that the extraction of the model for a few gate lengths allows for the prediction of the intrinsic performance, as well as for other lengths that fall into the studied range.

Conclusions
An analytical technique has been proposed to extract the small-signal equivalent circuits for MOSFFETs.The extrinsic elements have been determined using an open structure and "cold" FET measurements.The validity of the obtained models has been confirmed by the achieved good agreement between the measured and simulated S-parameters.The experimental data have shown that the presence of the substrate resistance in the intrinsic model is necessary to accurately reproduce the behavior of the measured output reflection coefficient.Furthermore, it has been found that the intrinsic unity current-gain cutoff frequency of the tested devices scales inversely with the square of the gate length, exhibiting a nearly ideal scaling.

Figure 2 .
Figure 2. Behavior of (a) I D ; (b) g mExtrDC ; and (c) g mDC versus gate length for three MOSFETs at V DS = 1 V and V GS = 1 V.

Figure 3 .
Figure 3. Small-signal equivalent circuit for the tested MOSFETs.

Figure 3 .
Figure 3. Small-signal equivalent circuit for the tested MOSFETs.

Figure 3 .
Figure 3. Small-signal equivalent circuit for the tested MOSFETs.

Figure 4 .
Figure 4. Behavior of Im(Y ij ) versus ω for the open structure.The extracted extrinsic capacitances are: C pg = 338 fF and C pd = 335 fF.

Figure 3 .
Figure 3. Small-signal equivalent circuit for the tested MOSFETs.

Figure 5 .
Figure 5. Behavior of Re(Z ij ) versus 1/(V GS − V TH ) for a MOSFET with a gate length of 0.25 µm at V DS = 0 V.The extracted extrinsic resistances are: R g = 1.9 Ω, R s = 1.7 Ω, and R d = 2 Ω.

Figure 3 .
Figure 3. Small-signal equivalent circuit for the tested MOSFETs.

Figure 6 .
Figure 6.Behavior of ωIm(Z ij ) versus ω 2 for a MOSFET with a gate length of 0.25 µm at V DS = 0 V and V GS = 1.4 V.The extracted extrinsic inductances are: L g = 26.6 pH, L s = 4.3 pH, and L d = 19.5 pH.

Figure 8 .
Figure 8. Measured (solid colored lines) and simulated (dashed black lines) S22 from 0.3 to 40 GHz at VDS = 1 V and VGS = 1 V for three MOSFETs with different gate lengths: 0.25 μm, 0.5 μm, and 1 μm.The simulations are performed by omitting Rsub in the model.

Figure 9 .
Figure 9. Behavior of (a) gm; (b) Cgg; and (c) fT versus gate length for three MOSFETs at VDS = 1 V and VGS = 1 V.

Figure 8 .
Figure 8. Measured (solid colored lines) and simulated (dashed black lines) S 22 from 0.3 to 40 GHz at V DS = 1 V and V GS = 1 V for three MOSFETs with different gate lengths: 0.25 µm, 0.5 µm, and 1 µm.The simulations are performed by omitting R sub in the model.

Figure 8 .
Figure 8. Measured (solid colored lines) and simulated (dashed black lines) S22 from 0.3 to 40 GHz at VDS = 1 V and VGS = 1 V for three MOSFETs with different gate lengths: 0.25 μm, 0.5 μm, and 1 μm.The simulations are performed by omitting Rsub in the model.

Figure 9 .
Figure 9. Behavior of (a) gm; (b) Cgg; and (c) fT versus gate length for three MOSFETs at VDS = 1 V and VGS = 1 V. Figure 9. Behavior of (a) g m ; (b) C gg ; and (c) f T versus gate length for three MOSFETs at V DS = 1 V and V GS = 1 V.

Figure 10 . 10 Figure 10 .Figure 11 .
Figure 10.Behavior of g m (colored symbols) and g mDC (white symbols) versus gate length for three MOSFETs at V DS = 1 V and V GS = 1 V.

Figure 11 . 10 Figure 10 .Figure 11 .Figure 12 .
Figure 11.Behavior of (a) g m ; (b) C gg ; and (c) f T versus V GS for three MOSFETs with different gate lengths at V DS = 1 V.