Intermodulation Linearity in High-k / Metal Gate 28 nm RF CMOS Transistors

This paper presents experimental characterization, simulation, and Volterra series based analysis of intermodulation linearity on a high-k/metal gate 28 nm RF CMOS technology. A figure-of-merit is proposed to account for both VGS and VDS nonlinearity, and extracted from frequency dependence of measured IIP3. Implications to biasing current and voltage optimization for linearity are discussed.


Introduction
Modern CMOS technology scaling is no longer just a matter of shrinking physical dimensions.A key to down scale the equivalent oxide thickness (EOT) in recent technologies is the replacement of classic poly-Si gate/SiO 2 gate stack with a high-k dielectric/metal gate stack.Given the tremendous interest in scaled RF CMOS and RF system-on-chip that integrates digital and RF functions, it is necessary to examine the RF performance of the core transistors in these scaled technologies.
In this work, we investigate two-tone intermodulation linearity in a 28 nm high-k/metal gate RF CMOS technology [1], characterized by the intermodulation intercept.Both second and third order intermodulation intercept IP 2 and IP 3 are measured.We focus on IP 3 as it is more relevant.Third order intermodulation products are close to the fundamental frequencies of interest and cannot be filtered out [2].Mixing of adjacent channel interferers produces undesired output in the frequency band of interest.Third order nonlinearities are also responsible for desensitization and cross-modulation.
From a gate capacitance perspective, poly depletion effect is no longer present with the use of metal gate, the change of gate-to-source capacitance C gs with gate voltage is less in strong inversion, and linearity should improve compared to poly-gate transistors according to [3].That analysis, however, assumed velocity saturation at the source, which is not the case in today's advanced CMOS.Scaling, and the associated changes in doping, effective oxide thickness, strain are all expected to change device I −V characteristics as well as the various transconductance nonlinearities, output conductance nonlinearities, and cross nonlinearities.
Harmonic gate voltage IP 3 of 28 nm RF CMOS devices has been recently examined using third-order derivative of I DS − V GS data [4].However, no experimental RF measurement of IP 3 has been reported.Previous investigations using Volterra series analysis [5] showed that such estimation using third-order transconductance nonlinearity alone is not sufficient in characterizing transistor IP 3. Drain conductance nonlinearity as well as cross terms involving partial derivatives of I DS with respect to both V GS and V DS are also important [6].Typical compact model parameters are extracted by fitting DC I-V curves and sometimes first order derivatives.A good fitting does not necessarily guarantee good accuracy of higher order derivatives, which are difficult to evaluate experimentally due to the increase of numerical and experimental error in differentiation.Direct RF intermodulation measurements are therefore necessary, which we present below, together with simulations using a compact model with DC I-V and Y-parameter calibration.As IP 3 in RF measurements is determined using RF power of the source voltage, the result in general depends on frequency, and cannot be directly compared with traditional gate voltage IP 3 that is defined using the gate voltage.
We propose below a new figure-of-merit that can be extracted from RF measurements so that meaningful comparison with traditional intermodulation gate voltage IP 3 can be made with ease.The new figure-of-merit accounts for both V GS and V DS related nonlinearities, and reduces to traditional intermodulation gate voltage IP 3 when all of the V DS related intermodulation products are neglected.

Tested Technology and Measurement System
Figure 1a shows typical I DS − V GS characteristics of a 30 nm device from the examined 28 nm technology.Figure 1b shows measured cut-off frequency f T as a function of I DS .A 304 GHz peak f T is reached at 0.45 mA/ µm at V DS = 1.05 V. Figure 1c shows typical I DS − V DS characteristics.
Figure 2a shows the experimental setup used, which is similar to the setup in [7].Broadband 50 Ω terminations are used so that they do not filter out the second order harmonics which may remix with the fundamental output to produce third order intermodulation (IM 3).Devices are probed on-wafer using Cascade Infinity GSG probes.Two Agilent signal sources are synchronized and combined using a power combiner to produce a two tone input.Attenuators are used to reduce the intermodulation within the sources.Automatic level control in the sources is turned off to minimize intermodulation generated by the sources.An HP-6625 power supply is used to provide precision DC biases.A spectrum analyzer is used to measure the output spectrum.Power meters are used for calibration of power loss on cables and probes.Analyzer setting is optimized for each measurement to minimize analyzer IM 3 and maximize signal to noise ratio.For each bias point and frequency, the input power is swept and the third order intercept is obtained by extrapolation.The analyzer setting is optimized dynamically for each input power level.The measurement system intermodulation is verified to be well below the intermodulation from the device under test.The upper and lower IM 3 are the same in our measurements.Figure 2b illustrates how IP 3 and IP 2 are determined for a 30 nm device biased at V GS = 0.44 V, V DS = 0.6 V. Device total width is 256 µm.Gate finger width W f is 1 µm, number of finger N f is 16, and multiplicity M = 16.At low P in , first order output P out,1st increases linearly with P in at a slope of 1:1, while the third and the second order intermodulation output (P out,3rd and P out,2nd ) increase at slopes of 3:1 and 2:1, respectively.IP 3 is obtained as the extrapolated intercept of P out,1st and P out,3rd in a region of P in where the ideal slopes are observed.The input and output powers at IP 3 are denoted as IIP 3 and OIP 3. Their difference is gain.Similarly, we can obtain IIP 2 and OIP 2 from the extrapolation intercept of P out,1st and P out,2nd .

Results and Analysis
As mentioned earlier, in RF measurement, the intercept point is defined using RF input power.The input third order intermodulation intercept point, IIP 3, is thus dependent on frequency, because of finite source impedance, which for our case, is a 50 Ω resistance.For a given RF input power, the RF gate voltage varies with frequency, as transistor input impedance varies with frequency.For analysis as well as estimation of IIP 3 at another design frequency from measurement at one frequency, it is desirable to find a figure-of-merit that does not depend on frequency.Such figure-of-merit is more useful if it can relate to the traditional figure-of-merit, gate voltage V IP 3, but also include effects of drain voltage related nonlinearities.We derive such a figure-of-merit below using Volterra series analysis.
A simplified equivalent circuit as shown in Figure 3 is used.Gate-drain capacitance (C gd ) is omitted, as the result is much simpler and sufficient for most purposes [5].R S = 50 Ω.C gs is gate-to-source capacitance.C d is drain capacitance.R L = 50 Ω is load resistance.i ds is nonlinear drain current: g m and g 0 are transconductance and output conductance.K 2g m , K 3g m , K 2g 0 , K 3g 0 , K 2g mg0 , K 3 2gmg 0 and K 3 gm2g 0 are nonlinearity coefficients that relate to higher order partial derivatives as defined in [8] using Taylor expansion.For instance, Using the nonlinear current source method, IIP 3 can be derived [5]: where ∆ = ∆ 1 + ∆ 2 + ∆ 3 + ∆ 4 .∆ 1 through ∆ 4 are functions of nonlinear output conductance, its high order terms and cross terms with transconductance nonlinearity as follows: Z 1 through Z 8 are given by: with Z L (ω) = and Y S (ω) = 1 R S + jωC gs .A close inspection of the Volterra series based derivation details shows that at the intermodulation IP 3 point, the first order v gs has an amplitude of: For typical transistor sizes of interest, the ∆ term is found to have a negligibly weak frequency dependence, making V GS,IP 3 nearly frequency independent in practice.We thus propose to use V GS,IP 3 as a figure-of-merit as it includes output conductance effect, and is more general than the traditional V IP 3 defined solely using K 3g m and g m .The designation GS in the subscript refers to the fact that this is the V GS amplitude at the intercept.The value of V GS,IP 3 , however, is clearly a function of the V DS dependence of I DS , through the ∆ term.
Using V GS,IP 3 , Equation (4) can then be rewritten as Equation ( 18) indicates that IIP 3 increases linearly with ω 2 and V GS,IP 3 can be obtained experimentally by plotting measured IIP 3 as a function of ω 2 , as shown in Figure 4a.A linear fitting is made.The intercept with the IIP 3 axis gives V 2 GS,IP 3 /8R S .Note that the unit used for IIP 3 is watt instead of dBm.As measured IIP 3 in dBm is shown in Figure 4b.The device has a drawn gate length of 30 nm.W f = 4 µm.N f = 16.Multiplicity M = 4.The total width W total = 256 µm.V GS = 0.7 V and V DS = 1.0 V. Measurement frequency ranges from 100 MHz to 10 GHz.Within measurement uncertainty, the data shows an expected linear dependence on the square of fundamental angular frequency.This linear dependence of IIP 3 on ω 2 is found to be valid for other bias points as well.The slope is given by from which C gs can be extracted.The C gs calculated is fairly close to that extracted from S-parameter measurements, thus supporting the validity of the proposed technique.
If we ignore the ∆ term that originates from the v ds dependence of i ds , V GS,IP 3 reduces to This is essentially the V GS,IP 3 one would get if transistor drain current depends on V GS only.This V IP 3 for intermodulation distortion differs from the third order harmonic distortion V IP 3 in [4,9] by a constant.
The transistor model used to evaluate the derivatives needed in Equation ( 4) is a PSP model, with initial parameter values for base line digital CMOS transistors of the same technology.In this work, device model parameters are tuned to better fit the I-V characteristics and S-parameters.Figure 5a,b compare simulated I DS versus V GS with measurement using linear and log I DS scales, respectively.Good agreement is achieved.To simulate IP 3, quasi periodic steady state (QPSS) analysis is used in Cadence SpectreRF to calculate two-tone large signal behavior [10].For each bias point, a series of input power level is swept.The output is plotted using ipnVRI function to ensure the extrapolation point for IP 3 is within the linear range, in the same manner IP 3 is determined in measurement illustrated earlier in Figure 2b.
Figure 6a shows both measured and simulated IIP 3 at 5 GHz as a function of V GS at V DS = 0.6 V for the same device in Figure 5. Measurements and simulations are also made at 2 and 10 GHz.At each V GS , from frequency dependence of IIP 3, a V GS,IP 3 is extracted.From 0.5 to 0.7 V, simulated IIP 3 is higher than measured IIP 3 by as much as 3.8 dB.This indicates that simulated IIP 3 for such technologies may be optimistic.In future work, model parameters can be further optimized to see if IIP 3 can be better fitted.To our knowledge, there are no direct knobs to turn to tune higher order derivatives in compact models.Improvement of IIP 3 simulation may require new improvements of the model formulation itself in addition to better parameter extraction and optimization.Figure 6b shows the V IP 3 calculated from K 3g m and g m using Equation (19).Fitting of V IP 3, which is determined by the first and third order derivatives of I DS -V GS , is clearly worse than the fitting of I DS -V GS itself shown earlier in Figure 5. Figure 6c,d show V GS,IP 3 and K 3g m as a function of V GS .The K 3g m = 0 point is clearly different from the measured IIP 3 and V GS,IP 3 peak positions.The peak IIP 3 V GS is 55 mV lower than the peak V IP 3 V GS .As was observed in 90 nm technology [5], V IP 3 does not correctly predict the linearity sweet spot, due to omission of the ∆ term.Around V GS = 0.6 V, V GS,IP 3 and the traditional V IP 3 are close to each other, as the ∆ term is small.Beyond its peak, IIP 3 drops to a valley and starts rising slowly.However, when V GS > 0.65 V, as the device gets closer to linear operation region, IIP 3 shows a slight decrease.Figure 7a-d show measured IIP 3, IIP 2, V GS,IP 3 , and V IP 3 as a function of V GS at V DS = 0.6 and 1.0 V.The same device as in Figure 6 is used.As can be seen from Figure 7a, IIP 3 curves at high V DS are shifted towards low V GS direction due to decreased threshold voltage, a consequence of drain induced barrier lowering.In strong inversion region, at the same V GS , a higher V DS results in a higher IIP 3.For instance, at V GS = 0.8 V, IIP 3 increases by 7.7 dB when V DS increases from 0.6 to 1.0 V.As shown in Figure 7b, IIP 2 has a clear peak, though not as sharp as IIP 3, around V GS = 0.6 V, in strong inversion.If both high IIP 3 and high IIP 2 are desired, the transistor should be biased around V GS = 0.6 V, which is approximately 200 mV above threshold voltage.A comparison of Figure 7c,d shows that the V DS dependence of V GS,IP 3 and hence IIP 3 is insufficiently captured by V IP 3, due to lack of v ds related terms, as expected.
Figure 8a shows measured IIP 3 at 5 GHz for devices with W total = 153.6 and 256 µm.Note that the device finger widths are 0.3 and 1 µm respectively.At both very low and high I DS , a large device gives a large IIP 3.Both peak IIP 3 value and peak IIP 3 I DS decrease with device width.Narrow width effect clearly plays a role in affecting the position of the linearity peak.Figure 8b shows measured IIP 3 as a function of V GS for two 30 nm MOSFETs with the same total width of 256 µm.As the device finger widths are both large, 2 and 4 µm respectively, no narrow width effect is observed, and IIP 3 is largely the same for the two devices as expected.

Conclusions
We have presented experimental measurements and simulation of RF intermodulation linearity as a function of biases and frequencies on a 28 nm high-k/metal gate RF CMOS technology.Using Volterra series analysis, a new figure-of-merit, V GS,IP 3 , is proposed.V GS,IP 3 can be experimentally determined from RF IP 3 measurements, circuit simulations, or calculated from DC I-V characteristics, and reduces to traditional V IP 3 when V DS dependence of I DS is neglected.Due to stronger impact of V DS on I DS , a stronger impact of V DS on IIP 3 is observed compared to 90 nm technologies.The strong output conductance and related nonlinearities also cause a large separation between the V GS,IP 3 /IIP 3 peak and V IP 3 peak.V GS dependence of IIP 2 is independent on that of IIP 3. A higher V DS is found to improve IIP 3 as well as IIP 2.

Figure 1 .Figure 2 .
Figure 1.Measured (a) I DS versus V GS ; (b) f T versus I DS and (c) I DS versus V DS .

Figure 3 .
Figure 3. Simplified equivalent circuit used for IP 3 derivation using Volterra series.

Figure 5 .Figure 6 .
Figure 5.Comparison of simulated I DS versus V GS with measurement on (a) linear and (b) log I DS scales at V DS = 0.6 and 1.0 V.

Figure 7 .Figure 8 .
Figure 7. Measured (a) IIP 3; (b) IIP 2 and (c) V GS,IP 3 and (d) V IP 3 as a function of V GS for different V DS .