A Fully Integrated Gate-Pole-Dominant Low-Dropout Regulator with Loop-Gain Booster for Maintaining High Power-Supply Rejection over a Wide Load Current Range

Abstract

This paper introduces a fully integrated gate-pole-dominant low-dropout regulator (LDO) that eliminates the need for external capacitors while sustaining high power-supply rejection (PSR) over a broad load current range. A loop-gain booster (LGB) is proposed to maintain the DC operating point of the error amplifier output at its optimal value, thereby preserving a high unity-gain frequency (UGF) even as the load current varies from zero to 200 mA. The parallel signal paths within the LGB inherently produce a left-half-plane (LHP) zero, which cancels one of the poles within the UGF of the feedback loop and guarantees robust stability under diverse operating conditions. Fabricated in a 40 nm CMOS technology, the prototype occupies only 0.008 mm² with a 4 pF on-chip compensation capacitor. The proposed LDO achieves a PSR of −72 dB at 1 MHz and −40 dB at 10 MHz when I_L = 200 mA and V_DO = 0.1 V, and maintains a PSR better than −78 dB at 1 MHz and −42 dB at 10 MHz when I_L = 1 mA and V_DO = 0.1 V. The LGB-enhanced regulator achieves excellent load and line regulation figures of 29 μV/mA and 0.75 mV/V, while the LGB itself consumes merely 7 μA out of a total quiescent current of 108 μA.

1. Introduction

In modern system-on-chip (SoC) implementations, the increasing degree of functional integration means that noise-sensitive analog and radio-frequency (RF) circuits coexist on the same silicon substrate with aggressive digital circuitry. The spurious switching activity and supply fluctuation generated by the digital blocks can severely degrade the performance of adjacent analog circuits [1]. Under these circumstances, on-chip low-dropout regulators (LDOs) capable of providing high power-supply rejection (PSR) have become essential building blocks in modern power management architectures [2].

Figure 1 illustrates the typical operating environment of an LDO in deep sub-micron integrated circuits, where the regulator must supply a clean output voltage V_OUT to multiple load blocks (i.e., L1, L2, …, Ln) under a shrinking dropout voltage V_DO and increasing load current I_L demands.

The demand for high-PSR LDOs has intensified as both the supply voltage headroom and the required I_L range have expanded concurrently. A shrinking supply voltage translates into a diminished V_DO, which places stringent constraints on the error amplifier’s output swing and gain. Meanwhile, applications such as wideband RF transceivers targeting 5G systems [3] require clean power delivery across bandwidths exceeding 100 MHz [3,4]. These dual requirements—low dropout and high PSR bandwidth—constitute one of the principal design tensions in contemporary LDO research.

From an architectural standpoint, LDO regulators are broadly divided into two families according to the location of their dominant loop pole [5]. In the first family, the dominant pole resides at the output node (i.e., ω_D = ω_OUT). While such output-pole-dominant LDOs naturally achieve high PSR at high frequencies—owing to the large output capacitor C_L shunting supply ripples to ground beyond the unity-gain frequency (UGF)—they face a fundamental stability challenge. As the load current I_L increases, the output pole moves toward the gate pole of the pass transistor, necessitating larger capacitors (often several microfarads) to preserve adequate phase margin [6,7,8,9]. The resulting dependence on bulky external capacitors conflicts with the ongoing drive toward full integration and reduced printed-circuit-board (PCB) footprints.

The second family positions the dominant pole at the gate node of the pass transistor M_P (i.e., ω_D = ω_G) [10,11,12,13,14,15,16,17,18]. In these gate-pole-dominant architectures, increasing I_L pushes ω_OUT away from the dominant pole, thereby relaxing the capacitive loading requirement and enabling capacitor-less operation. Nevertheless, a well-known drawback emerges: a PSR hump near the UGF. At frequencies above ω_G, the gate of M_P is effectively shorted to ac ground; so the regulating loop loses its ability to suppress supply perturbations until C_L takes over at higher frequencies [19]. The severity of this hump is directly linked to the UGF; a higher UGF pushes the hump to a higher frequency, improving broadband PSR.

Figure 2a depicts a conventional gate-pole-dominant LDO employing a simple error amplifier A_E that directly drives the gate of M_P, with the dominant pole located at the gate node V_E. The feedback is taken from the output node V_OUT. Figure 2b shows the corresponding PSR characteristics, where a notable PSR hump appears near the UGF (ω_UGF). When the loop gain is reduced—for example, by a shift in the operating point of the error amplifier—the PSR hump worsens, whereas boosting the loop gain pushes the hump to higher frequencies and improves the overall PSR performance.

However, maintaining a high UGF across a wide I_L range is challenging in practice. When I_L changes across several decades, the overdrive voltage of M_P varies substantially, which in turn forces the DC output level of the error amplifier V_E to undergo a large variation. If V_E deviates from the amplifier’s optimal output common-mode range (OCMR), the gain of the error amplifier A_E degrades, the loop gain drops, and the UGF decreases—all of which translate into deteriorated PSR. This problem is exacerbated as V_DO decreases, since the required swing in V_E grows proportionally. Recently published high-PSR LDOs can be broadly grouped into three categories according to their PSR-enhancement strategies. The first category includes LDOs employing feed-forward ripple-cancelation or ripple-neutralization paths to suppress supply ripple over frequency [20,21]. The second category consists of gate-pole-dominant capacitor-less LDOs that utilize adaptive biasing or active frequency-compensation techniques to preserve loop bandwidth and stability [22,23]. A third category combines multiple loops or control domains in hybrid topologies to balance PSR, bandwidth, and transient behavior [24,25]. Nevertheless, these prior works still face trade-offs among high-frequency PSR, wide load-current range, low dropout, stability, and implementation overhead. These limitations directly motivate the proposed loop-gain booster (LGB) approach.

In this work, we present a fully integrated gate-pole-dominant LDO that achieves sustained high PSR over a wide I_L range through a technique termed the loop-gain booster (LGB). Rather than adding intermediate gain stages or feed-forward cancelation paths, the LGB fixes V_E at its optimal DC operating point via a secondary feedback mechanism. This stabilization preserves the maximum attainable A_E—and hence the highest UGF—regardless of I_L and V_DO variations. Moreover, the auxiliary signal path of the LGB naturally produces an LHP zero that cancels a pole within the loop bandwidth, ensuring robust phase margin despite the multi-pole nature of the regulating loop. The remaining part of this paper is structured as follows. Section 2 examines the fundamental limitations of conventional gate-pole-dominant LDOs. Section 3 details the proposed LGB concept and overall architecture. Section 4 describes the transistor-level design of each building block. Section 5 presents the loop-gain analysis, stability assessment, and PSR characterization. Section 6 reports measurement results from the 40 nm CMOS prototype, and Section 7 concludes the paper.

2. Limitations of Conventional Gate-Pole-Dominant Architectures

To appreciate the contribution of the proposed technique, it is instructive to quantify the variation in V_E as I_L sweeps across its full range. In a gate-pole-dominant LDO where the error amplifier output drives M_P either directly or through an intermediate stage characterized by an effective gain A_I, the change ΔV_E experienced when I_L transitions from its minimum to maximum value can be expressed using the alpha-power-law MOSFET model [26] as:

$$∆{\mathrm{V}}_{\mathrm{E}}\approx {\displaystyle \frac{1}{{\mathrm{A}}_{\mathrm{I}}}}({\displaystyle \frac{\sqrt{{\mathrm{I}}_{\mathrm{L}.\mathrm{M}\mathrm{A}\mathrm{X}}}-\sqrt{{\mathrm{I}}_{\mathrm{L}.\mathrm{M}\mathrm{I}\mathrm{N}}}}{\sqrt{{\mathrm{k}}_{\mathrm{p}}}}}\times {\displaystyle \frac{1}{\sqrt{\left(1+\mathsf{\lambda }{\mathrm{V}}_{\mathrm{D}\mathrm{O}}\right)}}})$$

(1)

where $k_p=0.5{\mu }_P\cdot C_{ox}\cdot {\displaystyle \frac{W}{L}}$ is a process transconductance parameter, ${\mu }_P$ is a mobility of PMOS, $C_{ox}$ is a Capacitance of oxide, W and L are the width and length of M_P, λ is a channel length modulation parameter, V_DO is a drop-out voltage, $I_L$ is a load current, and A_I represents the voltage gain of any intermediate stage preceding M_P. According to (1), when A_I is unity (i.e., no intermediate stage), ΔV_E can amount to several hundred millivolts for a wide load current swing, readily exceeding the OCMR of the error amplifier.

Figure 3 shows a conventional LDO architecture that cascades an intermediate voltage buffer stage with gain A_I between the error amplifier output V_E and the gate of M_P. Prior solutions that employ high-gain intermediate stages [10,11] can raise A_I and thereby reduce the voltage ΔV_E as quantified in (1). However, achieving a high voltage gain in such a stage requires a correspondingly high output impedance, which, when loaded by the large parasitic capacitance of M_P, pulls the gate pole ω_G to a low frequency and limits the attainable UGF [12,13]. Multi-stage buffer topologies with low output impedance [14,15] offer another pathway but inevitably introduce multiple poles, creating stability concerns, especially under light-load conditions. It is worth noting that placing the dominant pole at V_G, rather than at V_OUT, is a deliberate architectural choice: it eliminates the need for a large off-chip output capacitor and ensures that the loop remains stable across the full load-current range, since the output pole moves to higher frequencies as I_L increases. The dominant pole at V_G effectively defines the loop bandwidth of the LDO, which in turn determines both the PSR performance within the regulation band and the speed of the load-transient response. Specifically, at frequencies below the dominant pole, the high loop gain suppresses supply ripples on V_OUT, while the same bandwidth governs how quickly V_OUT recovers to its nominal value after a load transient. However, this gate-pole-dominant topology inherently introduces the PSR hump described in Section 1, whose severity is directly tied to the UGF—and hence to how well V_E is maintained at its optimal operating point. In essence, these conventional approaches face a three-way trade-off among loop gain, bandwidth, and stability. Raising the intermediate-stage gain improves ΔV_E suppression at the cost of bandwidth; expanding the number of gain stages provides design flexibility but multiplies the poles that must be compensated. The LGB technique proposed in the following section resolves this trade-off by decoupling the DC operating point control of V_E from the signal-path gain distribution.

3. Proposed LDO Architecture Employing the Loop-Gain Booster

Figure 4a presents the top-level architecture of the proposed LDO, which comprises five principal blocks: the error amplifier, the loop-gain booster (LGB), M_P (3 mm/40 nm thin-oxide), and a Miller compensation network (R_C and C_C). Because the dominant pole is located at the gate of M_P rather than at the output, no external decoupling capacitor is needed. Figure 4b details the internal structure of the LGB, which consists of a secondary amplifier with gain A_S whose inverting input is referenced to V_REF2 and whose output drives a source-follower transistor M_SF2, operating in parallel with a main-path source follower M_SF1. A second buffer stage comprising M_SF3 and M_SF4 is inserted between V_P and the gate of M_P to eliminate the net DC level shift in the feedback path. Without this stage, the V_GS offset of the source followers (i.e., M_SF1) would cause V_E to settle at an excessively high DC level. By passing the signal through a PMOS source follower (i.e., M_SF4), which shifts the voltage down by one V_GS, followed by an NMOS source follower (M_SF4), which shifts it back up by one V_GS, the two offsets cancel, and the DC relationship between V_G and V_E remains free of any accumulated level shift. Also, a digitally controllable switch array (SW<N:0>) is incorporated within this buffer stage to calibrate the DC operating point of V_P. When I_L changes or PVT variations become extreme, the number of active switches can be adjusted to compensate for the resulting shifts in V_P. This prevents such perturbations from propagating back through the LGB and disturbing V_E, thereby keeping V_E stable across all operating conditions. It should be noted that, although C_C is connected between the gate and drain of M_P in a Miller configuration, its primary purpose in this design is not conventional pole-splitting. Without C_C and the series resistor R_C, the parasitic C_gd of the large pass transistor M_P naturally produces a right-half-plane (RHP) zero that significantly degrades the phase margin. By inserting a small Miller capacitor C_C (only 2 pF in this design) in series with R_C between the gate and drain of M_P, an LHP zero is generated that cancels the detrimental effect of the RHP zero and improves stability. The capacitance of C_C was deliberately minimized to 2 pF to avoid any severe bandwidth reduction from the Miller effect at the dominant gate pole.

3.1. Operating Principle of the Loop-Gain Booster

The LGB is composed of two sub-blocks: a secondary amplifier with high DC gain A_S and a voltage subtractor realized as two source followers. The key concept is the creation of an auxiliary signal path that operates in parallel with the main path from V_E (the error amplifier output) to V_P. In the main path, V_E is level-shifted by a first source-follower transistor M_SF1. In the auxiliary path, V_E feeds the inverting input of the secondary amplifier (referenced to V_REF2), whose output drives a second source-follower transistor M_SF2. Because the secondary amplifier inverts the signal polarity, the two contributions arrive at V_P with the same sign, ensuring constructive addition.

Since the DC gain A_S of the secondary amplifier is large, the closed-loop action of the overall LDO forces V_E to settle at V_REF2. By choosing V_REF2 to coincide with the voltage at which the error amplifier achieves its peak gain, the design locks V_E at the optimal operating point, irrespective of load-current or dropout-voltage variations. Consequently, A_E remains at its maximum value at all times, and the UGF of the loop is preserved.

It is worth noting that this operating principle of the LGB can be conceptually understood as the single-ended counterpart of a common-mode feedback (CMFB) loop. In a conventional differential amplifier, a CMFB loop is necessary because the high-impedance output node is not self-biased and would otherwise drift toward the supply rails; the CMFB loop anchors this node at its optimal DC operating point so that the differential gain is maximized. The error amplifier of an LDO suffers from a similar—but arguably more severe—DC drift problem at V_E, where the bias point is pushed away from the optimum by load-current variations as well as PVT and dropout-voltage changes. However, a conventional CMFB cannot be directly applied here, because the error amplifier in an LDO is a single-ended structure rather than a differential one, and CMFB inherently relies on sensing the common mode of two complementary outputs. The proposed LGB resolves this incompatibility by acting as a single-ended CMFB equivalent: it continuously senses V_E and, through the secondary feedback path described above, forces it back to V_REF2 regardless of I_L and V_DO. Unlike a simple DC servo loop, which only corrects DC offset and is typically heavily low-pass filtered to avoid interfering with the main signal path, the LGB remains active over a wide frequency range, so that it not only stabilizes the DC operating point of V_E but also actively boosts the small-signal loop gain at the frequencies where PSR matters most.

3.2. Transfer Function of the LGB

Superposing the gains of the main and auxiliary paths, the small-signal transfer function from V_E to V_P can be written as:

$${\displaystyle \frac{V_P}{V_E}}\left(s\right)\approx A_{LGB}\cdot {\displaystyle \frac{\left(1+\frac{s}{{\omega }_S\cdot A_{LGB}}\right)}{\left(1+\frac{s}{{\omega }_S}\right)}}$$

(2)

where

$$A_{LGB}=1+A_S\cdot \left({\displaystyle \frac{g_{m,SF2}}{g_{m,SF1}}}\right)$$

(3)

and ω_S is the pole frequency at the secondary amplifier output. This expression reveals that the two parallel paths inherently generate an LHP zero at a frequency $A_{LGB}$ times higher than ω_S. This intrinsic zero plays a pivotal role in maintaining phase margin, as it can be positioned to cancel one of the poles falling within the UGF of the overall loop.

It should be emphasized that this LHP zero is not an incidental byproduct of the LGB but rather a deliberate design feature that distinguishes the proposed approach from prior gate-pole-dominant LDOs employing intermediate gain stages. In conventional approaches, inserting an additional gain stage in the feedback loop introduces an additional pole that severely degrades the phase margin, often requiring large compensation capacitors or complex pole-splitting techniques that ultimately limit the achievable bandwidth and PSR. In contrast, the parallel signal flow between the main path and the auxiliary path of the LGB intrinsically generates the LHP zero in (2), which is positioned to cancel the phase degradation caused by the additional pole introduced by the LGB itself. As a result, the proposed LGB attains the gain-boosting and DC-stabilization benefits of an auxiliary amplifier without paying the stability penalty that has historically limited intermediate-gain-stage approaches. This is the key reason the LGB can deliver high PSR over a wide load-current range without sacrificing loop stability.

3.3. Effective Intermediate-Stage Gain

Figure 5 compares the behavior of ΔV_E and the error amplifier gain A_E as the load current I_L varies from 0 to 200 mA, for two cases: (a) without the LGB, and (b) with the LGB. As shown in Figure 5a, in the absence of the LGB, V_E undergoes a large excursion of approximately 0.6 V across the load range, causing A_E to degrade by as much as 27 dB. In contrast, Figure 5b demonstrates that with the LGB enabled, V_E remains nearly constant because the secondary feedback loop clamps it to V_REF2. As a result, A_E stays at its peak value of approximately 40 dB throughout the entire load range, confirming the effectiveness of the proposed technique.

As implied by (2), the effective gain from V_E to V_G (the gate of M_P) is given by the product A_LGB, which can be made large through the high gain of the secondary amplifier (approximately 26 dB in this design), ensuring that ΔV_E is significantly attenuated.

Figure 6 compares the open-loop gain of the proposed LDO with and without the LGB as a function of frequency, at two extreme load conditions (I_L = 0 mA and 200 mA) with V_DO = 0.1 V and C_L = 100 pF. Without the LGB, the DC loop gain drops by 37 dB when I_L increases from 0 to 200 mA. Also, it shows the degradation of UGF due to the increase in I_L. In contrast, with the LGB enabled, the DC gain variation is reduced to only 17 dB. Also, the reduction of UGF is minimized compared than that of the LDO without the LGB. Furthermore, the LGB contributes an additional 26 dB of gain, and the UGF is maintained at a consistently high level across the entire load range.

Figure 7 presents the simulated PSR comparison between the LDO with and without the LGB under the same operating conditions. Without the LGB, the PSR at the hump frequency degrades by up to 29 dB as I_L increases from 0 to 200 mA, reflecting the collapse of the loop gain. With the LGB active, the LDO can achieve a 26 dB better PSR at 0 mA, compared with the LDO without the LGB. It can be observed that without LGB, the PSR-hump shifts to a lower frequency. Also, even when I_L increases from 0 to 200 mA, the degradation of the PSR is dramatically reduced to 13 dB, confirming that maintaining a high UGF directly translates into improved broadband PSR performance.

Figure 8 shows the simulated load-transient responses of the LDO with and without the LGB for a 0 to 200 mA current step (100 ns edge time) at V_DO = 0.1 V and C_L = 100 pF. With the LGB enabled, the steady-state output voltage is regulated at 0.999 V with undershoot and overshoot magnitudes of 90 mV and 89 mV, respectively. Without the LGB, the steady-state output shifts to 0.958 V—a 42 mV offset reflecting the degraded DC loop gain—while the transient excursions are comparable (93 mV undershoot and overshoot). The similar transient peak amplitudes indicate that the slew rate, limited by the stage driving M_P, governs the dynamic behavior in both cases, whereas the improved DC accuracy with the LGB reflects its superior static regulation.

Figure 9 presents the results of a Monte Carlo simulation of the output voltage error ΔV_OUT at I_L = 25 mA, V_DO = 0.1 V, and C_L = 100 pF, with a target output voltage of V_OUT = 1 V. The distribution yields an average offset of −1.06 mV and a standard deviation of 0.80 mV, indicating that the proposed LDO achieves acceptable output accuracy even in the presence of process and mismatch variations.

4. Transistor-Level Design of the Building Blocks

4.1. Error Amplifier

High inherent PSR of the error amplifier at low frequencies is a prerequisite for achieving excellent overall PSR. This design adopts a negative-g_m operational amplifier topology [27], in which the negative impedance generated by cross-coupled transistors cancels the low impedance of diode-connected loads. This technique dramatically boosts the output impedance—and hence the voltage gain—of the first stage without requiring larger bias currents. The input pair employs NMOS devices, and an NMOS-type current mirror at the second stage ensures high supply rejection at low frequencies [28].

Figure 10 shows the transistor-level schematic of the error amplifier. The first stage consists of cross-coupled PMOS load pairs (M_E3,M/M_E3,P and M_E4,M/M_E4,P) with NMOS input transistors (M_E2,M and M_E2,P), creating high-impedance nodes A and A′ through negative-g_m enhancement. The reference voltage V_REF1 and the feedback voltage V_FB are applied to the NMOS differential pair (M_E1,M and M_E1,P), and the second stage produces the output V_E at node B. Tail current sources M_E5,M and M_E5,P set the bias condition.

Particular attention was paid to minimizing the parasitic capacitances at the internal high-impedance nodes (designated A and A′ in the schematic) by keeping the transistor dimensions compact. This strategy pushes the associated parasitic poles well beyond the UGF, preventing them from eroding the phase margin. The overall voltage gain of the error amplifier, evaluated at its output node B, exceeds 40 dB at low frequencies.

4.2. Secondary Amplifier

The secondary amplifier within the LGB is a conventional single-stage differential pair using PMOS input transistors, which inherently provides superior supply rejection at low frequencies compared with an NMOS input pair [28]. The secondary amplifier of the LGB employs a PMOS-input differential pair with a top PMOS bias current source. This topology provides inherently superior supply-noise rejection compared to NMOS-input configurations, because supply perturbations are tracked by both the source nodes of the input pair and the bias reference, resulting in first-order cancelation of supply-induced $V_{GS}$ modulation at the input stage [28]. This property is particularly important for the LGB, since any supply noise that leaks through the secondary amplifier would directly degrade the overall PSR improvement provided by the loop-gain boosting mechanism. Because its primary function is to establish a high DC gain for clamping V_E rather than to extend signal bandwidth, the secondary amplifier operates with a modest current budget of only 2 μA and delivers approximately 26 dB of voltage gain. To further improve the common-mode rejection ratio (CMRR), the tail current source is implemented with a long channel length to increase its output resistance.

Figure 11 presents the transistor-level schematic of the secondary amplifier. The PMOS input pair (M_S3,P and M_S3,M), sized at 1 μ/1 μ, receives V_REF2 and V_E at its differential inputs. The input pair is sized sufficiently large to reduce random offset and threshold-voltage mismatch, thereby helping maintain CMRR robustness under PVT variations. The NMOS current-mirror load (M_S4,P and M_S4,M, sized at 1 μ/2 μ) provides the output at V_S. In layout, the input differential pair and active load are arranged symmetrically using common-centroid and interdigitated configurations to minimize gradient-induced mismatch. The compact transistor dimensions keep the parasitic pole at the output node well above the frequencies of interest.

5. Theoretical Analysis of Loop Gain, Stability, and PSR

5.1. Loop-Gain Transfer Function

Figure 12 illustrates the complete small-signal equivalent model of the proposed LDO. The error amplifier is represented by its transconductance g_m,E driving the output resistance R_E in parallel with the parasitic capacitance C_E. The LGB is modeled as two parallel paths: the main source-follower path with transconductance g_m,SF feeding into R_P and C_P, and the secondary amplifier path with gain −g_m,S driving R_S and C_S, where ω_S marks the secondary amplifier’s pole, and ω_Z2 denotes the LHP zero produced by the parallel-path structure. The low-gain buffer (g_m,B) connects to the gate node of M_P, modeled by R_G and C_G with the dominant pole ω_G. The Miller compensation network (R_C and C_C) introduces the compensating zero ω_Z1, and the output stage comprises the pass transistor transconductance g_m,P driving the parallel combination of the load resistance R_L and the load capacitor C_L, establishing the output pole ω_OUT.

The complete small-signal model of the proposed regulator includes multiple gain stages, each contributing poles and zeros. Within the UGF, three poles and two LHP zeros dominate the phase-margin budget. The first (dominant) pole ω_G arises at the gate of M_P, where the Miller-amplified compensation capacitor and the intrinsic gate capacitance create a large effective capacitance. The second pole ω_S lies at the output of the secondary amplifier, and the third pole ω_OUT is located at the LDO output. The first LHP zero ω_Z1 is generated by the series R_C–C_C Miller network, while the second LHP zero ω_Z2 originates from the parallel-path structure of the LGB, as derived in (2). The DC loop gain is given by:

$$A_{v,DC}=g_{m,E}\cdot R_E\cdot \left(1+g_{m,S}\cdot R_S\cdot {\displaystyle \frac{g_{m,SF2}}{g_{m,SF1}}}\right)\cdot g_{m,B}\cdot R_G\cdot g_{m,P}\cdot \left(R_L\parallel r_{o,p}\right)$$

(4)

5.2. Phase Margin and Maximum Load Capacitance

Figure 13a shows the Bode plots (magnitude and phase) of the proposed LDO obtained from post-layout simulations across three representative process–temperature corners: [TT, 30 °C], [FF, −30 °C], and [SS, 100 °C]. Figure 13a presents the results at I_L = 200 mA and C_L = 1.5 nF (it is not required C_L, but just the maximum allowable C_L at full load). The dominant gate pole ω_G, the secondary amplifier pole ω_S, and the output pole ω_OUT are clearly visible in the magnitude response, along with the two LHP zeros (ω_Z1 and ω_Z2) that provide phase recovery before the crossover. The UGF ranges from 80 to 180 MHz, and the worst-case phase margin is approximately 43° at the [FF, −30 °C] corner, with 51° at [TT, 30 °C] and 63° at [SS, 100 °C]. Figure 13b shows the corresponding plots at I_L = 0 mA and C_L = 100 pF. The UGF in this case spans 90–180 MHz, with worst-case phase margins of approximately 40°, 44°, and 50° at the [FF, −30 °C], [TT, 30 °C], and [SS, 100 °C] corners, respectively.

Post-layout simulations were carried out across five process–temperature corners: [TT, 70 °C], [FF, −30 °C], [SS, 100 °C], [FF, 100 °C], and [SS, −30 °C]. For I_L = 200 mA and C_L = 1.5 nF (the maximum allowable load capacitance at full load), the worst-case phase margin was 43° at the [FF, −30 °C] corner.

5.3. PSR Analysis

Figure 14 depicts the coupling paths through which supply noise V_IN reaches the LDO output V_OUT. Four principal paths are identified: P_A1 (PSR₁) propagates through the second source follower of the LGB; P_A2 (PSR₂) couples through the source-follower-based voltage subtractor A_SF into the buffer; P_A3 (PSR₃) passes through the secondary amplifier A_S; and P_A4 (PSR₄) enters via the error amplifier A_E. The output node also receives direct supply coupling through the pass transistor’s drain–source path, modeled by P_M1 and P_M2.

Supply noise reaches the LDO output through several coupling mechanisms: the transconductance and drain–source conductance of M_P, and parasitic supply-sensitivity paths in the error amplifier, the secondary amplifier, the voltage subtractor, and the second source follower of the LBG. A breakdown analysis at 1 kHz, 100 kHz, and 10 MHz reveals that the pass-transistor paths account for 88–98% of the total supply coupling, with the remaining contributions from the amplifier stages limited to less than 12%. The overall PSR within the UGF is well described by:

$${PSR}_{LDO}\left(s\right)\approx {\displaystyle \frac{\left(K_{M1,M2}+K_{A1}+K_{A2,A3,A4}\right)}{\left(1+LG\left(s\right)\right)\cdot \left(1+\frac{s}{{\omega }_{out}}\right)}}$$

(5)

where K_M1,M2 captures the pass-transistor coupling (6–14 dB), K_A1 represents the buffer path contribution (suppressed to below −8 dB by the NMOS active load), and K_A2,A3,A4 accounts for the remaining amplifier stages (collectively below −5 dB at low frequencies). The close agreement between the analytical model and full post-layout simulation validates the adequacy of this PSR decomposition.

Figure 15 compares the overall PSR obtained from post-layout simulation (solid lines, at three process–temperature corners: [TT, 30 °C], [FF, −30 °C], and [SS, 100 °C]) with the analytical prediction from Equation (5) evaluated in MATLAB (ver.R2026A) (dashed line). Figure 15a shows the case with V_DO = 0.1 V, I_L = 0 mA, and C_L = 100 pF, and Figure 15b shows the case with V_DO = 0.1 V, I_L = 200 mA, and C_L = 100 pF. In both cases, the analytical model closely tracks the simulation across the entire frequency range, confirming the validity of the PSR decomposition presented above.

6. Experimental Results

Figure 16 shows the die micrograph of the proposed LDO fabricated in a 40 nm CMOS process. The total chip area is 950 μm × 500 μm, and the layout identifies the major functional blocks: the pass transistor (Pass-Tr.), the LDO core containing the error amplifier and LGB, the output buffer, the input buffer, an SPI interface for digital control, and the on-chip load capacitor C_L used for testing. The total active area, including the 4 pF on-chip compensation capacitor, measures 0.008 mm², of which the LGB occupies a mere 240 μm² (approximately 3% of the core area).

The input supply voltage is 1.1 V, and the output voltage is adjustable between 0.7 and 1.0 V, corresponding to dropout voltages in the range of 0.1–0.4 V. Both reference voltages, V_REF1 and V_REF2, were provided externally during testing.

Figure 17 illustrates the measurement setups used to characterize the LDO. Figure 17a shows the PSR measurement configuration, in which a function generator provides an 80 mV peak-to-peak ac ripple that is combined with the DC supply through a bias tee to produce V_IN. The output voltage V_OUT is sensed through a common-mode measurement resistor R_CM and buffered by a THS 3120 amplifier before being analyzed by a spectrum analyzer (Keysight Technologies, Santa Rosa, CA, USA; N9020A). The input capacitor C_in = 10 pF and termination resistor R_in = 50 Ω ensure proper impedance matching. Multiple ground domains (GND1, GND2, GND3) are carefully managed on the PCB to minimize ground-loop interference. Figure 17b depicts the load-transient measurement setup, where a function generator drives the load current through the common-mode node with R_in = 1 MΩ and C_in = 10 pF, and the output transient is captured by an oscilloscope (Tektronix, Beaverton, OR, USA; MSO9254A). Figure 18 shows our actual measurement setup.

6.1. Power-Supply Rejection

PSR measurements were conducted by superimposing an 80 mV peak-to-peak ac ripple onto V_IN and sweeping the frequency from 10 kHz to 10 MHz. Figure 19a shows the measured PSR with the LGB enabled as V_DO decreases from 0.4 to 0.1 V at a fixed I_L of 200 mA. Even under the most stressed condition of V_DO = 0.1 V, the LDO sustains PSR values better than −78, −72, and −40 dB at 100 kHz, 1 MHz, and 10 MHz, respectively—demonstrating the technique’s efficacy in preserving high rejection under low-headroom operation. Figure 19b presents the measured PSR as I_L increases from 1 mA to 200 mA at V_DO = 0.1 V. The PSR remains largely invariant with load current when the LGB is active, confirming the robustness of the proposed approach across the entire load range. Even at a light load current of 1 mA, the proposed LDO sustains PSR values better than −84 dB, −78 dB, and −42 dB at l00 kHz, 1 MHz, and 10 MHz, respectively. This demonstrates that the supply rejection performance of the proposed design is well maintained across the full range of load current conditions.

6.2. Transient Response

Figure 20a shows the measured load-transient response when I_L steps between 0.2 and 200 mA with 100 ns edge time at V_IN = 1.1 V, V_OUT = 1.0 V (V_DO = 0.1 V), and C_L = 100 pF. The steady-state output voltage shifts from 1.0028 V at light load to 0.997 V at full load, yielding a load regulation of 19 μV/mA with the LGB enabled. The undershoot and overshoot magnitudes are 134 mV and 132 mV, respectively, with recovery times of 0.7 μs (undershoot) and 0.8 μs (overshoot). Figure 20b shows the measured line-transient response when V_IN steps between 1.1 and 1.3 V at I_L = 25 mA. The output voltage fluctuations are limited to 4 mV in both directions, with a settling time of approximately 0.6 μs for the rising edge and 0.5 μs for the falling edge, yielding a line regulation of 0.75 mV/V. These results confirm that the LGB successfully maintains a high loop gain under both load and supply perturbations.

6.3. Output Noise

Figure 21 compares the measured and simulated output noise spectral density of the proposed LDO at I_L = 200 mA and V_DO = 0.1 V. The measurement was performed using a spectrum analyzer, and the results are plotted alongside the post-layout simulation predictions. The measured spot noise density at a 400 kHz offset is 88.58 $nV/\sqrt{Hz}$, showing reasonable agreement with the simulated values. The noise spectrum exhibits the expected 1/f characteristic at lower frequencies, transitioning to a flat thermal noise floor at higher offsets. Importantly, toggling the LGB has no appreciable effect on the noise floor, indicating that the dominant noise contributor is the error amplifier rather than the LGB circuitry.

6.4. Performance Summary and Comparison

Table 1. Performance comparison with state-of-the-art external-capacitor-less LDOs.

		This Work	[29]	[30]	[31]	[32]	[33]	[34]	[35]
Year		2026	2021	2025	2025	2022	2024	2018	2025
Process (nm)		40	180	28	180	180	180	130	40
Dominant pole		ωG	ωG	ωG	ωG	ωG	ωG	ωG	ωG
Technique		LGB	Adaptive Biasing	Dual-Loop	Bulk-Driven	Multi-loops	Load-Tracking	Multi-miller path	DLRA
VIN (V)		1.1	1.8	0.5–1	2.5–3.3	1.2–2.4	1.2–1.8	1–1.4	0.8–1.0
VDO (V)		0.1	0.2	0.1	0.2	0.2	0.2	0.2	0.1
IL,MAX (mA)		200	100	120	100	100	10	25	500
IL,MIN (mA)		0.2	0.1	0.1	0.1	1	0.1	0.12	5
CL (pF)		100	100	20	100	1000	NA	25	165
UGF (MHz)		80–200	3.88	8.5–150	4.45	<1	38.5	100.2–130.5	NA
PSR (dB)	100 kHz	−78	−29.4	−66	−10	−32	<−40	NA	<−40
	1 MHz	−72	−22.5	−44	NA	−12	−39	−57	<−30
	10 MHz	−40	NA	−22	NA	−1	−24.5	−22	<0
Cap. for compensation (pF)		4	12	NA	NA	NA	0.4	0.115	NA
Load reg. (μV/mA)		29	0.48	324	8.38	0.025	NA	173	NA
Line reg. (mV/V)		0.75	0.75	6.53	2.94	0.5	11.7	2.25	NA
IQ (μA)		108	10–50.25	26–224	37	14	0.054	112	300–350
Undershoot (mV)		134	174	158	NA	252	390	284	96
TTR (ns)/K *		100/333	500/1667	10/33	NA	1000/3333	15/50	0.3/1	10/
ΔIL for transient test(mA)		199.8	99.9	99.9	99.9	99	9.9	24.88	300
FOMTR ** (mV)		24.1	145.8	9.7	NA	117.6	0.1	1.27	NA
TSETTLE (μs)		0.8	NA	0.023	1.2	7.3	0.0175	<0.19	0.052
$\mathrm{Output} \mathrm{noise} (\mathrm{nV}/\sqrt{\mathrm{H}\mathrm{z}}$)		276 @100kHz	NA	NA	NA	NA	NA	NA	NA
Active area (mm2)		0.008	0.104	0.0016	0.0417	0.109	0.0074	0.008	0.17

* K: T_TR used in the measurement/the smallest T_TR among the designs for comparison. ** FOM_TR: K× Undershoot × I_Q/I_L,MAX [18].

benchmarks the proposed LDO against recently reported state-of-the-art external-capacitor-less LDOs in terms of PSR, load capability, regulation performance, transient response, quiescent current, and silicon area. Among the compared designs, the proposed LDO exhibits the strongest PSR at all reported frequency points, achieving –78 dB at 100 kHz, –72 dB at 1 MHz, and –40 dB at 10 MHz. In addition, it supports the highest maximum load current of 200 mA while operating with the lowest dropout voltage of 0.1 V. Its UGF also extends up to 200 MHz, indicating a very wide loop bandwidth. In contrast, prior works generally either support lower maximum load currents or exhibit weaker PSR in the MHz range [29,30,31,32,33,34]. These results suggest that the proposed LGB-based architecture is highly effective in simultaneously achieving strong supply-noise suppression, wide loop bandwidth, and high load-driving capability.

From the implementation viewpoint, the proposed LDO also provides a competitive overall design point. Its line regulation is 0.75 mV/V, which is comparable to [29] and better than [30,31,33,34]. The active area is only 0.008 mm², which is among the smallest in Table 1 and is smaller than those of [29,31,32]. In addition, as described in the circuit implementation, the LGB itself introduces only 7 μA of additional quiescent current and 240 μm² of area overhead. On the other hand, the load regulation of 29 μV/mA is not the lowest among the compared works, indicating that the design emphasis is placed not on minimizing a single DC metric, but on achieving a balanced optimization across PSR, bandwidth, dropout, load capability, and area.

In terms of transient behavior, the proposed LDO achieves the smallest undershoot of 134 mV among the compared designs. Its ${\mathrm{F}\mathrm{O}\mathrm{M}}_{\mathrm{T}\mathrm{R}}$ is 24.1 mV, which is significantly better than those of [29,32], although some prior works, such as [30,33,34], report smaller ${\mathrm{F}\mathrm{O}\mathrm{M}}_{\mathrm{T}\mathrm{R}}$ values or shorter settling times. However, those designs generally show trade-offs in maximum load current, PSR, or both. The measured settling time of 0.8 μs is also faster than those of [31,32], while remaining competitive considering the 200 mA load-driving capability. Therefore, the key advantage of the proposed LDO is not merely the best result in a single metric, but the well-balanced combination of strong PSR from 100 kHz to 10 MHz, low-dropout operation, high maximum load current, compact area, and competitive transient performance without requiring an external capacitor.

7. Conclusions

This paper has presented a fully integrated gate-pole-dominant LDO regulator that leverages a loop-gain booster to maintain high PSR performance over a wide load current range without relying on external capacitors. By clamping the error amplifier’s output DC level at its gain-maximizing operating point, the LGB ensures that the UGF of the feedback loop remains high regardless of variations in the load current and dropout voltage. Implemented in a 40 nm CMOS process, the prototype achieves PSR values of −72 dB and −40 dB at 1 MHz and 10 MHz, respectively, under the most challenging conditions of 200 mA load current and 0.1 V dropout.

An intrinsic LHP zero generated by the dual-path topology of the LGB compensates for one of the in-band poles, ensuring robust stability with phase margins exceeding 40° across all corners. The technique incurs only 7 μA of additional quiescent current and 240 μm² of extra silicon area—negligible overheads relative to the total LDO budget. These attributes, combined with excellent load regulation (29 μV/mA) and line regulation (0.75 mV/V), make the proposed LGB technique a compelling candidate for powering noise-sensitive analog and RF circuits in advanced SoC platforms.

While the current implementation targets a 40 nm node, the LGB concept is process-agnostic and can be applied to LDOs designed in longer-channel technologies with proportional benefits to the UGF. Future work may explore combining the LGB with adaptive supply-ripple cancelation techniques to push PSR performance beyond 1 GHz, which would be particularly valuable for next-generation wideband wireless transceivers.