Exploiting Static Conductance and Dynamic Switching of Memristors for Artificial Intelligence Applications

Abstract

Memristors, as programmable resistive switching devices, offer two fundamental computational modalities for artificial intelligence: static conductance for parallel data processing and dynamic switching for temporal, logical, and stochastic operations. This Review systematically distinguishes these two modalities and evaluates their respective hardware implementations. In terms of our review scope, we first examine how static conductance modality is exploited in analog matrix computing, which encompasses matrix–vector multiplication and matrix equation solving, and discuss how these primitives enable efficient neural network inference and training. Second, we survey dynamic switching modality and its algorithmic applications, including stateful logic for digital in-memory acceleration, attractor networks for associative memory, reservoir computing and spatiotemporal signal processing using transient device dynamics, biologically inspired spike-timing-dependent plasticity, and stochastic computation. In addition, we discuss key challenges such as device variability, stochastic switching, interconnect parasitics, peripheral circuit overhead, and endurance limitations. We also highlight opportunities for future development, emphasizing algorithm–hardware co-design to leverage application-specific error tolerance and mitigate device non-idealities. Finally, we outline promising research directions aimed at realizing robust, scalable, and energy-efficient memristor-based AI systems.

1. Introduction

The scale and computational demands of artificial intelligence (AI) models have grown explosively in recent years. In this work, AI is broadly defined to encompass a wide spectrum of computational paradigms, including traditional machine learning (ML), neural networks (NNs), and transformer-based foundation models, as well as neuromorphic and bio-inspired learning approaches. From large pre-trained foundation models to real-time inference on resource-constrained edge devices, modern AI workloads impose increasingly stringent requirements on computing power, memory bandwidth, and energy efficiency. However, conventional digital computing architectures struggle to meet these demands efficiently [1]. This challenge is further exacerbated by the slowdown of Moore’s Law, which has limited the performance gains achievable through transistor scaling [2]. Meanwhile, traditional von Neumann architectures suffer from significant energy and latency overheads due to the frequent transfer of large volumes of data between physically separated processing and memory units [3,4,5]. Consequently, developing novel computing architectures that enhance parallelism and reduce data movement has become a critical necessity for next-generation AI systems.

Memristors—two-terminal electronic elements with programmable conductance—have emerged as promising building blocks for in-memory computing (IMC) and brain-inspired hardware [6,7,8]. While several recent reviews have examined memristor-based computing, most address static conductance or dynamic switching in isolation, or discuss both without an explicit structural division (

Table 1. Comparison of recent reviews on memristor-based neuromorphic computing.

Attribute	Prior Paper	Application
Static Conductance	Memory devices and applications for in-memory computing [5]	NN, scientific computing, combinatorial optimization
	In-Memory Vector-Matrix Multiplication in Monolithic Complementary Metal–Oxide–Semiconductor-Memristor Integrated Circuits: Design Choices, Challenges, and Perspectives. [10]	NN, machine learning
Dynamic Switching	Emerging Materials and Computing Paradigms for Temporal Signal Analysis [11]	Reservoir computing, spatiotemporal signal detection, STDP
Covering both but unstructured	Neuromorphic computing using non-volatile memory [12]	NN, STDP, stateful logic
	In-memory computing with resistive switching devices [3]	Stateful Logic, NN, stochastic computation
Both as structured	In-memory computing with emerging memory devices: Status and outlook [9]	NN, Closed-loop AMC circuits, STDP, reservoir computing, spatiotemporal signal detection
	This Review	NN, Closed-loop AMC circuits, stateful logic, attractor networks, reservoir computing, spatiotemporal signal detection, STDP, stochastic computation

). Notably, Mannocci et al. (2023) introduced a pioneering static/dynamic framework [9]. This review systematically organizes memristor-based AI hardware around these two intrinsic physical modalities. Beyond consolidating recent breakthroughs, we substantially expand the coverage to include previously underrepresented paradigms, such as closed-loop analog matrix computing (AMC) for second-order NN training, practical implementations of stateful logic and stochastic computing. Integrated with updated co-design strategies for modern architectures like Transformers, this article provides a timely, application-centric roadmap that explicitly leverages the dual physical modalities of memristors for next-generation AI systems. As illustrated in Figure 1, their functionality is fundamentally characterized by two key modalities: (i) static conductance—the ability to set and retain a multi-level conductance that can represent matrix elements; and (ii) dynamic switching—the nonvolatile or volatile time-dependent resistive transitions intrinsic to the devices.

When exploiting the static conductance of memristors arranged in crossbar arrays, a primary application is AMC, which enables massively parallel, low-energy operations. The first major pathway of AMC is matrix-vector multiplication (MVM), the fundamental operation in fully connected, convolutional, and attention-based layers of NNs [13]. The second pathway extends AMC to the direct, one-step solution of matrix equations [14]. This is achieved through closed-loop circuits that integrate crossbars with feedback amplifiers to perform matrix inversion, generalized inverse and related linear solving tasks in the analog domain.

Dynamic switching behavior refers to time-dependent resistive changes and switching events in memristors. To systematically exploit these dynamics for AI, their applications can be methodically classified into four primary physical paradigms [12,15,16,17]: (1) deterministic nonvolatile switching: leveraging abrupt, nonvolatile state transitions to implement stateful logic and associative attractor networks; (2) volatile relaxation switching: utilizing the spontaneous decay and fading memory of volatile memristors to construct reservoir computing substrates and spatiotemporal sensors; (3) cumulative nonvolatile switching: exploiting the pulse-driven, incremental conductance modulation in nonvolatile memristors to emulate biological spike-timing-dependent plasticity (STDP); and (4) stochastic switching: harnessing intrinsic switching randomness and thermal noise as physical entropy sources for stochastic computing.

This Review frames memristor-based AI hardware around these two complementary modalities—static conductance and dynamic switching. After an overview of device physics and performance metrics (Section 2), we examine static conductance approaches for analog matrix computations (Section 3) and dynamic-switching approaches for temporal, logical, and stochastic paradigms (Section 4). Finally, we synthesize open challenges and highlight algorithm-hardware co-design strategies to guide future efforts in developing robust, energy-efficient memristor-based AI systems (Section 5).

2. Memristor Background

The memristor concept was first proposed by Leon Chua (1971) and later experimentally demonstrated in nanoscale two-terminal devices [18,19]. In practice, most hardware implementations adopt a metal–insulator–metal (MIM) structure, where a thin active layer is positioned between the two electrodes. The active material and electrode interfaces determine the dominant switching behavior and thus the device’s electrical characteristics.

The switching behavior of modern memristors is commonly grouped into two broad categories. Nonvolatile resistive switching includes valence-change mechanism (VCM), electrochemical metallization (ECM), and phase-change memory (PCM). In VCM and ECM devices, resistance modulation is governed by field-driven ion migration and filament formation or rupture [20,21,22,23,24,25], whereas PCM relies on reversible amorphous–crystalline phase transitions in chalcogenide materials [26,27,28]. Volatile memristors, by contrast, relax back to a high-resistance state after the stimulus is removed and are therefore better suited to temporal processing and transient dynamics [29,30,31]. Representative examples include diffusion-mediated memristors, Ovonic threshold switching elements, and VO₂-based Mott devices. Importantly, the same memristor-based platform can often be tuned toward persistent weight storage or transient switching behavior through material engineering, interface design, current compliance, and pulse protocols [6]. Notably, the distinction between static conductance and dynamic switching is application-driven rather than material-driven. In this review, static conductance refers to conductance states intended for long-term weight storage and computation, whereas dynamic switching refers to resistive state transitions exploited for stateful logic, attractor networks, temporal processing, and plasticity.

Key device performance metrics that determine suitability for AI workloads include settling and retention times, programming linearity and symmetry, multilevel resolution, cycle-to-cycle and device-to-device variability, endurance, on/off contrast, switching energy, and the probability of stochastic switching under a given input pulse. Nonvolatile memristors (e.g., VCM, ECM, and PCM) typically exhibit on/off ratios ranging from ${10}^2$ to ${10}^5$ and endurance spans from ${10}^4$ to over ${10}^{10}$ cycles [20,21,22,23,24,25,26]. Their switching energies generally fall within the femtojoule (fJ) to picojoule (pJ) regime, with PCM typically operating at the higher pJ end due to its thermally driven phase transition [5,26]. Crucially, due to the stochastic nature of filament formation and phase changes, these devices often suffer from noticeable cycle-to-cycle and device-to-device variability, posing a primary challenge for high-precision weight mapping [6]. In contrast, volatile memristors are characterized by spontaneous relaxation times (nanoseconds to milliseconds) and extremely high endurance (${10}^{10}$ to >${10}^{12}$ cycles) as they avoid permanent structural rupture [17,31]. They feature ultra-fast switching (<30 ns) and inherently provide stochastic switching probabilities that are highly beneficial for temporal and probabilistic AI workloads [32]. Subsequent sections discuss how these physical characteristics are leveraged in specific circuit implementations and algorithmic frameworks.

3. Static Conductance of Memristors and Their Applications in AI

3.1. Matrix-Vector Multiplication Primitive on Crossbar Arrays

A memristor crossbar array serves as a fundamental building block for IMC, efficiently performing MVM [33,34,35,36,37,38]. To aid readability, the principal symbols used in the mathematical derivations are listed in Appendix A (

Table A1. Symbol notation.

Symbol	Meaning	Symbol	Meaning
$\mathit{A}$	Weight matrix	$\mathit{C}$	Covariance matrix
G	Conductance matrix	$\mathit{D}$	Graph degree matrix
$\mathit{x}$	MVM input/AMC output vector	$\mathit{I}$	Identity matrix
$\mathit{y}$	MVM output/AMC input vector	${\mathit{g}}_{\mathit{x}}$	Input conductance vector
$\mathit{v}$	Output voltage vector	k	Constant of dual IMC
$\mathit{i}$	Input current vector	$g_c$	Compensation conductance
$\mathit{z}$	Intermediate vector	$\mu$	Auxiliary node voltage
W	Weight matrix of NN	$\lambda$	Eigenvalue parameter
b	Bias vector of the NN	$\tau$	Relaxation time
$\mathit{H}$	Node-feature matrix of GNN	$\Delta t$	Relative spike timing
$\mathit{Q}$	Query matrices	$m,n$	Matrix dimensions
$\mathit{K}$	Key matrix	V	Node voltage
$\mathit{V}$	Value matrix	I	Current
$\mathit{L}$	Graph Laplacian matrix	$g$	Memristor conductance
$\mathit{h}$	hidden state of RNN	$\beta$	Sparsity penalty

), which also clarifies notations that may vary across sections. As shown in Figure 2a, the array stores programmable conductances $A_{ij}$ at each crosspoint, representing the weight matrix A. When a voltage vector $\mathit{x}$ is applied to the word lines (WLs), the current flowing through each device is $I_{ij}=G_{ij}\cdot x_j$. According to Kirchhoff’s current law (KCL), the total current in each bit line (BL) is the sum of the currents from all connected devices: $I_i={\mathsf{\Sigma }}_j{G}_{ij}{x}_j$. This current represents exactly the dot product between the i-th WL of the conductance matrix and the input vector. The resulting currents are then converted into a digital MVM result by peripheral circuits, including transimpedance amplifiers (TIAs) and analog-to-digital converters (ADCs).

MVM executes n-dimensional dot products in a single physical step across a crossbar array, providing massive parallelism that can outperform serial digital implementations. IMC leverages this property to perform computation where the weights are stored, avoiding repeated data transfer between memory and processor. However, this crossbar-based implementation of MVM only partially alleviates the von Neumann bottleneck: the array typically stores only the weight matrix, while input values must still be supplied from external sources. To address this limitation, Wang et al. propose a dual IMC method where the input vector is also represented as conductance states within the array, as shown in Figure 2b [39]. In this approach, a voltage pulse is applied to the word-line corresponding to the row that stores the input vector ${\mathit{g}}_{\mathit{x}}$. As a result, the bit-line (BL) voltages are modulated according to KCL. By introducing conductance compensation ($g_c$) to equalize the total conductance connected to each BL, a linear mapping between BL voltage and input value can be achieved: ${\mathit{V}}_{BLj}=k{\mathit{g}}_{\mathit{x}}$, where k is a constant. This approach enables both weights and inputs to be processed within the array, eliminating the need for digital-to-analog converters (DACs) for input encoding, thereby significantly reducing external data movement and improving array utilization.

This parallel MVM primitive, implemented at the physical device level, is a cornerstone for accelerating linear operators in a wide range of NN architectures. However, its practical implementation is constrained by limited computational accuracy due to device non-idealities, as well as by significant overhead introduced by peripheral circuits, including DACs and ADCs. These combined bottlenecks restrict the effective numerical resolution of practical implementations to approximately 5–8 bits for target workloads [40].

3.2. Applications of MVM in Neural Networks

Memristor crossbars offer a versatile MVM primitive capable of accelerating a wide range of NN architectures, and extensive research has demonstrated their practical integration.

Fully Connected Network (FCN). A fully connected layer computes $\mathit{y}=\mathit{W}\cdot \mathit{x}+\mathit{b}$, as illustrated in Figure 3a. Mapping this operation onto a crossbar is straightforward: each weight $W_{ij}$ is programmed as a conductance $G_{ij}$, and the input vector $\mathit{x}$ is applied as WL voltages; the resulting BL currents represent the output activations [41,42,43,44,45]. Because dense MVMs dominate many AI workloads, crossbars deliver high throughput by performing numerous dot products in parallel. Representative works span device-to-system considerations: integration studies combine arrays with CMOS peripherals to form programmable systems on a chip (SoC) that tolerate variability via calibration [41]; Dot-Product Engine-type architectures explore weight encoding, negative-value mapping, and precision decomposition [46]; and mixed-precision approaches perform most dot products in low-precision analog and correct residuals digitally, achieving efficient energy–accuracy tradeoffs [34]. FCNs represent a well-established and promising target for crossbar-based acceleration, with substantial progress already demonstrated in practice.

Convolutional Neural Network (CNN). A convolution operation can be formulated as multiple local dot products between flattened kernels and input patches, as illustrated in Figure 3b [47]. Consequently, convolutions map naturally to memristor crossbars by storing flattened kernels as column-wise conductance vectors and applying input patches as row voltages [40,48,49,50,51]. The primary challenges lie in limited array sizes and efficient input reuse. Key studies have addressed these issues through weight encoding and precision-splitting schemes to reduce column replication, as well as optimized tiling and reuse strategies to improve array utilization. Moreover, several fully hardware-implemented CNN prototypes have demonstrated the feasibility of end-to-end on-chip inference [9,46,52]. Together, these results confirm that with proper mapping and peripheral co-design, memristor crossbars can effectively accelerate convolutional layers.

Recurrent Neural Network (RNN). Recurrent models reuse the same weight matrices across time steps, so the principal operations remain MVMs of the form $\mathit{W}\cdot {\mathit{x}}_{\mathit{t}}$ and $\mathit{W}\cdot {\mathit{h}}_{\mathit{t}-1}$ for the gates and candidate updates in an LSTM cell, as illustrated in Figure 3c [53]. Memristor crossbars can store the weight matrices for input and recurrent connections and be invoked at each time step to perform the required MVMs in parallel [54,55,56,57,58]. In practice, however, the time-recursive nature of RNNs raises two additional requirements: maintaining stable programmed conductances over repeated reads and writes, and controlling accumulated numerical errors across multiple time steps. Experimental and system-level studies have addressed these challenges: early demonstrations verified low-power LSTM inference, followed by in situ training approaches that adapt to device nonidealities and system prototypes that incorporate calibration and mixed-precision correction [54,56]. Achieving high-precision conductance programming is particularly crucial to prevent long-term error accumulation.

Graph Neural Network (GNN). A prototypical graph convolutional layer (GCN) implements $\mathit{H}(l+1)=\sigma (\widehat{\mathit{A}}\cdot \mathit{H}\left(l\right)\cdot \mathit{W}(l))$, where $\widehat{\mathit{A}}$ is an adjacency matrix and $\mathit{H}\left(\mathit{l}\right)$ is the node-feature matrix of the l-th layer, as illustrated in Figure 3d [59]. Because adjacency matrices are sparse and access patterns irregular, directly mapping GNN operations onto dense crossbars results in low utilization and significant energy inefficiency [60,61]. Recent studies have proposed sparse-friendly mappings, communication support, and heterogeneous architectures that decouple the aggregation and dense transformation stages. For example, IMA-GNN organizes dataflow around graph aggregation, while ReGNN partitions dense and sparse computations for improved efficiency [62,63]. These works demonstrate that with sparsity-aware scheduling and heterogeneous compute support, crossbar-based GNN accelerators can achieve competitive performance [64,65,66].

Transformer. The computational bottleneck of Transformers lies in repeated dense matrix multiplications, prominently including the generation of query ($\mathit{Q}$), key ($\mathit{K}$), and value ($\mathit{V}$) matrices through matrix multiplications of input embeddings. Subsequently, the scaled dot-product attention computes attention scores through another matrix multiplication ($\mathit{Q}{\mathit{K}}^{\mathrm{T}}$), followed by a weighted sum with $\mathit{V}$, expressed as $\mathrm{S}\mathrm{o}\mathrm{f}\mathrm{t}\mathrm{m}\mathrm{a}\mathrm{x}\left(\mathit{Q}\cdot {\displaystyle \frac{{\mathit{K}}^T}{\sqrt{d_k}}}\right)\cdot \mathit{V}$, as illustrated in Figure 3e [67]. Unlike many CNN kernels, the operands in attention layers vary dynamically at runtime. For modern large language models (LLMs), particularly in long-context generative tasks, the primary bottleneck has shifted from initial projections to the management and reuse of the key-value (KV) cache. This shift introduces severe memory-wall pressure, including frequent writes of intermediate matrices and substantial ADC/DAC overhead. To address these issues, recent memristor-based CIM architectures emphasize hardware–algorithm co-design. Sequence blocking and tiling strategies partition long contexts to align with crossbar dimensions, while matrix decomposition and pipelined dataflows optimize attention computation efficiency [68,69]. In addition, KV cache compression methods reduce the memory footprint of long-context inference [70]. Several memristor-based attention accelerators such as Attar execute attention in-memory, reducing write-backs and memory-transfer overhead [71,72,73,74,75]. Collectively, these co-optimized strategies demonstrate that memristor crossbars can efficiently accelerate Transformer.

Spiking Neural Network (SNN). Spiking networks compute weighted sums of sparse, temporally coded spike trains, meaning their synaptic operations can be expressed as dot products between spike-based inputs and conductance-encoded weights, as illustrated in Figure 3f. In addition, some volatile memristors inherently exhibit thresholding and short-term dynamic behaviors, enabling compact hardware neuron implementations that integrate seamlessly with synaptic crossbars [76]. Architectures combining sensing, event encoding, spike generation, and crossbar-based synapses minimize I/O overhead and enable highly event-driven computation pipelines. Several studies have also explored on-chip learning rules, such as STDP and its variants, implemented through local updates [77]. Overall, memristor hardware has demonstrated the ability to support both the synaptic MVMs and the compact neuronal primitives necessary for building dense, low-power SNN accelerators.

3.3. Closed-Loop Matrix Equation Solving in AMC

Memristor crossbars can also be employed to implement efficient closed-loop matrix equation solvers [11,78]. By constructing closed-loop feedback topologies in which crossbars are embedded within the feedback paths of amplifiers—such as operational amplifiers (op-amps) or transimpedance amplifiers (TIAs)—these AMC circuits can perform more advanced linear algebra operations relevant to AI applications. Figure 4 summarizes several representative closed-loop AMC circuits, including those for matrix inversion, generalized inverse (GINV), eigenvector extraction, and sparse approximation. Throughout this section, we consistently map the mathematical variables to their circuit counterparts: the coefficient matrix $\mathit{A}$ is encoded as the conductance matrix $\mathit{G}$, the known vector $\mathit{y}$ is applied as the input current $\mathit{i}$, and the solution vector $\mathit{x}$ is read out as the output voltage $\mathit{v}$.

Matrix Inversion (Figure 4a). The inversion circuit (INV) solves the linear system $\mathit{A}\cdot \mathit{x} =\mathit{y}$ for an n × n matrix $\mathit{A}$. The crossbar that encodes $\mathit{G}$ to conductance values and is connected in a global feedback loop through op-amps. Thanks to the op-amp virtual-ground property, the input nodes are maintained at approximately 0 V during operation. When an input current vector is applied to the op-amp inputs, the closed-loop feedback enforces the corresponding steady-state solution

$$\mathit{x}={\mathit{A}}^{-1}\cdot \mathit{y}.$$

(1)

These closed-loop feedback dynamics are depicted in the block diagram of Figure 4a (bottom). The convergence time of this topology depends on the spectral properties of $\mathit{A}$ (in particular its smallest eigenvalue), rather than directly on matrix size [79]. Specifically, a larger minimum eigenvalue (or equivalently, a smaller condition number) leads to faster convergence. This spectral dependence explains why closed-loop AMC can achieve very fast solutions for well-conditioned matrices.

Generalized Inverse (Figure 4b,c). Non-square or rank-deficient problems require a GINV. AMC can realize both left and right GINVs with paired crossbars and amplifier networks.

Figure 4b shows the left GINV circuit for the overdetermined case m > n. Two crossbar arrays store copies of $\mathit{A}$ and two sets of amplifiers form the feedback network. When the input current vector $\mathit{y}$ is applied, the steady-state solution is

$$\mathit{x}={\left({\mathit{A}}^T\cdot \mathit{A}\right)}^{-1}\cdot {\mathit{A}}^T\cdot \mathit{y}={\mathit{A}}^{+}\cdot \mathit{y}.$$

(2)

Figure 4c implements the right GINV for the underdetermined case m < n. Here, the crossbars are programmed with ${\mathit{A}}^T$ and the topology is modified so that KCL yields

$$\mathit{x}={\mathit{A}}^T\cdot {\left(\mathit{A}\cdot {\mathit{A}}^T\right)}^{-1}\cdot \mathit{y}={\mathit{A}}^{+}\cdot \mathit{y}.$$

(3)

Both GINV circuits compute minimum-norm solutions through fully analog feedback dynamics, which is useful for least-squares regression tasks in AI.

Eigenvector Circuit (Figure 4d). The eigenvector circuit directly enforces

$$\mathit{A}\cdot \mathit{x}=\lambda \mathit{x}$$

(4)

via a positive feedback configuration, with the TIA conductance encoding the eigenvalue λ of matrix $\mathit{A}$ [80]. The steady-state outputs are the eigenvectors associated with $\lambda$. This analog approach enables direct extraction of principal directions, which can accelerate principal component analysis (PCA) and spectral methods used in AI pipelines [81].

Modified-GINV Circuit (Figure 4e). Figure 4e illustrates an AMC circuit designed to solve for all eigenpairs (eigenvalues and eigenvectors) of a matrix [82]. The topology maps the target matrix $\mathit{A}$ and the diagonal matrix $\lambda \mathit{I}$ onto two memristor arrays, leading to the matrix relation:

$${\left(\mathit{A}-\lambda \mathit{I}\right)}_{2:n}^T {\left(\mathit{A}-\lambda \mathit{I}\right)}_{2:n} {\mathit{x}}_{2:n} = -{\left(\mathit{A}-\lambda \mathit{I}\right)}_{2:n}^T {\left(\mathit{A}-\lambda \mathit{I}\right)}_1 x_1.$$

(5)

The vector ${\left(x_1,x_2 ,\cdots ,x_n\right)}^T$ corresponds to the eigenvector associated with the current eigenvalue parameter $\lambda$. By sweeping the conductance values of the diagonal array and monitoring the output voltage of the op-amp in the disconnected branch for a characteristic peak, the circuit identifies the eigenvalue of G. This approach enables the extraction of the complete set of eigenpairs for a given matrix, which can accelerate PCA, spectral clustering and graph learning.

Sparse Approximation (Figure 4f). Figure 4f shows an AMC circuit that solves a sparse approximation (LASSO-like) problem:

$$\underset{x}{\min }L\left(\mathit{x}\right) =\underset{x}{\min }[1/2{\left|\left|\mathit{y}-\mathit{A}·\mathit{x}\right|\right|}_2^2+\beta {\left|\left|x\right|\right|}_1]$$

(6)

where $\beta$ controls the sparsity penalty [83]. In this design, the compensation conductance ${\mathit{g}}_c$ ensures conductance sum of each column equal to a constant, thus the crossbar output current proportional to ${\mathit{G}}^{\mathit{T}}(\mathit{G}\cdot \mathit{v}-\mathit{i})$. That current is converted by TIAs to node voltages μ, and the sparsity output x is obtained through soft-thresholding nonlinearity (Figure 4g). The analog inverters are applied for cancelling the diagonal contribution of the Gram product ${\mathit{G}}^{\mathit{T}}\cdot \mathit{G}$. The circuit performs the locally competitive algorithm (LCA):

$${\displaystyle \frac{\mathrm{d}\mathit{\mu }}{\mathrm{d}t}} = {\displaystyle \frac{1}{\tau }} \left[-\mathit{\mu }+{\mathit{A}}^T\cdot \mathit{y}-\left({\mathit{A}}^T\cdot \mathit{A}-I\right)\cdot \mathit{x}\right].$$

(7)

This direct analog implementation of the differential equation can accelerate sparse coding, compressed sensing, and other AI primitives relying on L1 regularization.

By constructing a closed-loop architecture between the memristor crossbar array and op-amps, AMC circuits can achieve rapid solutions to complex linear-algebra problems fast, typically converging within nanoseconds to microseconds [79,80,81]. Thereby, they provide efficient hardware primitives for AI tasks such as regression, optimization, and NN training.

3.4. Applications of Closed-Loop AMC Circuits

3.4.1. Linear/Logistic Regression

As a fundamental ML model, linear regression is widely used for regression and predictive analysis across diverse fields, including biology, statistics and finance [84]. The GINV circuit described above can be directly applied to perform linear regression in a single step and has been demonstrated on standard benchmark datasets such as the Boston Housing dataset [85]. This approach enables one-step regression with comparable accuracy to digital baselines and offers a dramatic speedup and energy reduction owing to its fully parallel analog implementation [85]. In contrast to linear regression, which is a fully linear model, logistic regression introduces a nonlinear sigmoid function into the feature-to-output mapping to produce binary outcomes. As a widely used model for object classification and pattern recognition, logistic regression can be regarded as a single-layer FCN. It is also commonly employed as the final output layer in multilayer NNs, with its training process equivalent to that of a single-layer network. Through the logit transformation, the logistic regression problem can be reduced to a linear regression problem. Based on this simplification, as shown in Figure 5a, the aforementioned linear regression (or GINV) circuit has been shown to implement logistic regression in one step—for example, in the training of a two-layer NN for modified national institute of standards and technology (MNIST) digit recognition—and can effectively accelerate reservoir computing training [85,86,87]. Previous studies have also demonstrated that such circuits exhibit significant performance advantages across multiple benchmark metrics [88,89,90,91,92]. Their computational speed can further be enhanced through parameter co-optimization [93].

Building on the basic GINV circuit structure, a generalized regression circuit has also been designed by replacing scalar conductances with a conductance array. The introduced matrix enables encoding additional information on data covariance for generalized linear regression or circuit preconditioning when solving linear systems [95]. Meanwhile, a ridge regression circuit has been developed to implement the regularization term by adding an additional negative feedback branch [96]. Although applications of generalized and ridge regression circuits in NN training have not yet been reported, these designs have significantly broadened the functional scope of regression circuits and are expected to enable fully on-hardware NN training [97].

3.4.2. Second-Order Neural Network Training

In NN training, second-order optimization methods converge much faster than first-order ones because they leverage the inversion of the second-order information (SOI) matrix to determine more accurate descent directions and step sizes [98]. However, on conventional computing platforms such as graphics processing unit (GPU) and central processing unit (CPU), handling the massive SOI matrix incurs substantial computational and memory overhead. As illustrated in Figure 5b, the matrix inversion circuit described earlier can efficiently accelerate SOI matrix inversion, offering O(1) computational complexity and high parallelism. Analysis has shown that second-order training accelerators-based on matrix inversion circuits achieve significant speed and energy efficiency improvements over conventional GPU and PipeLayer baselines [99,100] (see Discussion for quantitative comparisons). In parallel, inspired by the intrinsic mechanisms of AMC, the thermodynamic approach to computation has emerged as a promising paradigm for solving mathematical problems [101]. Its core principle lies in exploiting the stochastic dynamic behavior of physical systems governed by the interplay of conservative, dissipative, and fluctuating forces. Thermodynamic computing has been shown to accelerate tasks such as matrix determinant evaluation and solving matrix equations [102,103]. Furthermore, it has been applied to Bayesian inference and to accelerating various second-order NN training algorithms, including natural gradient descent and Kronecker-factored approximate curvature (KFAC) [104,105,106]. Notably, these thermodynamic approaches have also demonstrated superior speed and energy efficiency compared with first-order methods such as stochastic gradient descent (SGD) and Adam.

3.4.3. Linear Programming and Quadratic Programming

The parallelism of closed-loop AMC circuits enables their widespread application in optimization tasks, including linear programming (LP) and quadratic programming (QP). LP and QP are extensively used in numerous scientific and engineering fields, such as ML, robot kinematics and drone control [107]. LP and QP problems can be formulated as minimizing an objective function ${\mathit{x}}^T\mathit{A}\mathit{x}+{\mathit{c}}^T\mathit{x}$ subject to equality and inequality constraints, where a QP problem reduces to an LP problem when the Hessian matrix $\mathit{A}$ is zero. Both the interior-point and simplex methods are iterative, with each iteration requiring multiple complex matrix computations, which imposes a lower bound on computational complexity for digital solvers [108,109]. AMC circuits provide an alternative approach by directly accelerating these matrix operations. For example, using AMC circuits to implement iterative methods such as the alternating direction method of multipliers can reduce the effective computational complexity of QP problems to approximately O(k), where k is the iteration time that is typically small. Furthermore, optimized circuit structures can extend AMC solvers to tackle more complex problems, including mixed-integer programming [110,111].

By fully exploiting the inherent differential characteristics of feedback loops, several studies have proposed LP solvers-based on RNN architectures and closed-loop AMC solvers [112,113,114,115]. As shown in Figure 5c,d, the ultra-fast hybrid computing system integrates tuning, control, optimization, readout circuits, and memristor arrays [94]. By directly mapping the problem constraints and objective function to the memristor array conductances and input voltage values, the solution can be obtained rapidly at the output port, reducing the computational complexity of LP and QP optimization. In application scenarios such as miniature aerial vehicle control and edge computing for clinical image analysis, the closed-loop AMC solver demonstrates ultra-fast response speeds and massive energy efficiency improvements compared to standard microcontrollers units (MCU), substantially alleviating computational pressure in these domains.

3.4.4. PCA and Spectral Clustering

PCA is a classical linear dimensionality reduction technique in ML. It relies on the eigendecomposition of data covariance matrices to extract eigenvectors (principal components) representing directions of maximum variance, with corresponding eigenvalues quantifying the information content. The closed-loop AMC circuit in Figure 4e provides a hardware acceleration solution by mapping the covariance matrix $\mathit{C}$ onto array conductances and sweeping the $\lambda$ value in the diagonal array [82,116]. When $\lambda$ coincides with an eigenvalue, the op-amp output exhibits a characteristic peak, while the voltage vector encodes the corresponding eigenvector. This analog domain direct solution eliminates the need for iterative convergence and data movement, enabling PCA with ultra-low latency and energy consumption. The circuits have been validated on the Iris dataset and Wine dataset, with extracted principal components closely matching theoretical values.

Spectral clustering is a graph-based clustering algorithm that relies on eigendecomposition of the graph Laplacian matrix $\mathit{L}=\mathit{D}-\mathit{A}$ [117]. Its core step extracts eigenvectors corresponding to the smallest nonzero eigenvalues as node spectral embeddings, followed by k-means clustering in the embedding space to partition graph nodes. For large-scale graphs with tens of thousands of nodes (e.g., social networks, knowledge graphs), Laplacian eigendecomposition imposes enormous computational demands that conventional digital processors struggle to meet for real-time applications. The AMC circuit in Figure 4e provides efficient hardware acceleration: by mapping the Laplacian matrix onto memristor arrays, the circuit completes eigendecomposition with ultra-low latency, directly outputting all required eigenvectors. Because the circuit solves the complete set of eigenpairs, it is particularly suited for spectral clustering, which requires multiple non-dominant eigenvectors. The parallelism and low-latency characteristics of AMC, combined with memristor IMC, significantly alleviate the memory wall bottleneck in large-scale graph analytics, offering viable acceleration for real-time graph clustering, community detection in social networks, and graph learning applications [118,119,120].

4. Dynamic Switching of Memristors and Their Applications in AI

Driven by an applied voltage, memristors change their conductance, exhibiting distinct conductance states. The high-conductance state (HCS) functions like a closed switch (logic 1), while the low-conductance state (LCS) acts as an open switch (logic 0). To systematically harness these behaviors for AI, we first establish a unifying framework that maps intrinsic switching dynamics to their corresponding computational paradigms (

Table 2. Taxonomy of Dynamic Switching Applications in AI.

Required Physical Dynamics	Application Paradigm	Typical Device Type	Core AI Function
Deterministic nonvolatile switching (abrupt SET/RESET)	Stateful logic & attractor networks	Nonvolatile	In-memory Boolean logic, associative memory
Volatile relaxation switching (fading memory)	Reservoir computing & spatiotemporal signal detection	Volatile	Temporal feature extraction, short-term memory
Cumulative nonvolatile switching (incremental modulation)	STDP	Nonvolatile	Unsupervised local learning, synaptic weight update
Stochastic switching (intrinsic noise)	Stochastic computing	Volatile/nonvolatile	Bayesian inference, random number generation

). Specifically, deterministic nonvolatile switching characterizes abrupt state transitions harnessed for stateful logic (Section 4.1) and attractor network (Section 4.2). Conversely, volatile relaxation switching utilizes the spontaneous decay to provide a natural fading memory essential for reservoir computing (Section 4.3). Regarding synaptic learning, cumulative nonvolatile switching relies on cumulative, history-dependent conductance modulation to implement local plasticity rules like STDP (Section 4.4). Finally, stochastic switching exploits the probabilistic nature of ion migration or phase transition to offer a physical substrate for stochastic computing (Section 4.5). This unifying framework explicitly contrasts the required physical dynamics, corresponding device types, and system-level applications.

4.1. Stateful Logic and In-Memory Logic Acceleration

Stateful logic executes Boolean operations directly within a memory array, by exploiting the abrupt switching process of memristor to indicate logic output [121,122,123,124,125,126]. It uses only the two conductance levels, HCS and LCS, to encode logic 1 and 0, respectively. Under proper voltage stimuli, SET and RESET transitions change a device to HCS or LCS, respectively. In this way, a memristor both stores a bit and participates in logic operation, reducing data movement between separate memory and compute units.

Stateful logic gates operate by exploiting differences in conductance among input memristors to control intermediate node voltages. Those intermediate voltages, in turn, determine whether an output memristor receives a voltage that exceeds its switching threshold and therefore switches state. Different input patterns produce different node voltages and thus different outputs for the same physical connection pattern.

Material implication (IMP) was the earliest demonstrated stateful primitive for memristors [121]. As shown in Figure 6a, in the IMP circuit, two memristors, A and Y, together with a load resistor, are driven by two voltages: a conditioning voltage $V_{\mathrm{c}\mathrm{o}\mathrm{n}}$ applied to A and a SET voltage $V_{\mathrm{s}\mathrm{e}\mathrm{t}}$ applied to Y. The intermediate node voltage $V_{\mathrm{P}}$ is determined by KCL:

$$V_{\mathrm{P}}={\displaystyle \frac{V_{\mathrm{c}\mathrm{o}\mathrm{n}}{g}_{\mathrm{A}}+V_{\mathrm{s}\mathrm{e}\mathrm{t}}{g}_{\mathrm{Y}}}{g_{\mathrm{X}}+g_{\mathrm{Y}}+g_{\mathrm{L}}}}.$$

(8)

Here, $g_{\mathrm{A}}$ and $g_{\mathrm{Y}}$ are the conductances of A and Y, and $g_L$ denotes the load conductance. The logic design ensures that Y is SET (written to 1) only when A = 0 and Y = 0 initially; when A = 1 and Y = 0, the voltage across Y remains below the SET threshold, preventing switching. If Y is already 1, the output stays unchanged. The final state of Y implements the IMP result. IMP, together with FALSE logic gate, can be composed to realize universal logic.

Memristor-Aided LoGIC (MAGIC) is a memristor-only logic family that mainly uses RESET transitions to implement gates such as NOR [122]. As shown in Figure 6b, input memristors A and B are preprogrammed to input values, and the output memristor Y is initially set to HCS. During evaluation, input lines are driven with voltages such that the intermediate node voltage $V_{\mathrm{P}}$ becomes

$$V_{\mathrm{P}}={\displaystyle \frac{V_{\mathrm{A}}{g}_{\mathrm{A}}+V_{\mathrm{A}}{g}_{\mathrm{B}}}{g_{\mathrm{A}}+g_{\mathrm{B}}+g_{\mathrm{Y}}}}.$$

(9)

If either input is logic 1, $V_{\mathrm{P}}$ shifts and the voltage across Y exceeds its RESET threshold, forcing Y to LCS (logic 0). Only if both inputs are 0, Y remains in HCS (logic 1). With NOR as a primitive, arbitrary Boolean logic can be synthesized in place within the array.

Stateful logic can be extended to the so-called stateful neural network framework [123]. As shown in Figure 6c, memristors A and B encode the logic inputs, and the output memristor Y stores the computation result. Applying KCL at the intermediate node, the voltage across the output memristor can be expressed as a weighted sum of input contributions:

$$V_{\mathrm{Y}}-V_{\mathrm{P}} = w_{\mathrm{A}}{x}_{\mathrm{A}}+w_{\mathrm{B}}{x}_{\mathrm{B}}+b.$$

(10)

Here, $x_{\mathrm{A}}$ and $x_{\mathrm{B}}$ denote input bits stored in memristor states, and $w_{\mathrm{A}}$, $w_{\mathrm{B}}$, $b$ are effective weight terms derived from conductances and voltage biases. Because the output memristor has a switching threshold, the architecture naturally implements a nonlinear activation: if the weighted sum exceeds threshold, the output switches to 1; otherwise, it remains 0. In this way, linear accumulation and a threshold activation are realized in situ, enabling implementation of single-layer perceptron for linearly separable logic functions, and, by cascading, multi-layer networks capable of XOR/XNOR and other linearly inseparable functions.

Using combinations of stateful gates, one can build digital adders, multipliers, and full arithmetic units inside memristor arrays. For example, a 1-bit full adder can be mapped to a column of memristors and a sequence of stateful operations, as shown in Figure 6d,e. Researchers have proposed MAGIC-based designs for fixed-point multiplication and for floating-point multiplication adapted to crossbar arrays [127]. Such adders and multipliers can be composed to implement MVM primitives, which are central to NN inference and training. Complex nonlinear functions and gradients required by learning algorithms can be approximated by Taylor expansions and implemented using the same basic arithmetic primitives.

Several stateful IMC architectures are built upon these MAGIC-based stateful logic primitives to accelerate AI workloads. As shown in Figure 6f,g, FloatPIM is a representative architecture that decomposes high-precision operations into sequences of bitwise stateful gates and maps them efficiently onto crossbar arrays [128]. FloatPIM and related systems implement CNN and FCN by bit-serial or hybrid mappings, trading the number of bitwise cycles for reduced data movement and high array parallelism [128,129,130,131]. Other architectures—ConvPIM, RIME, ReHy, and DUAL—apply similar principles for CNNs, transformers, clustering, and other ML tasks [132,133,134,135]. Improvements in mapping, gate synthesis, and compiler-level scheduling are critical to achieve high throughput. On the other hand, hybrid analog–logic approaches may also be applied by combining analog crossbar MVM for bulk dot product with stateful digital logic for activations, normalization, and control, thus maximizing the strengths of both paradigms [136].

4.2. Attractor Network

Beyond utilizing the inherent unidirectional threshold behavior of memristor, their SET/RESET switching characteristics can also be leveraged simultaneously. This manifests as a significant hysteresis loop in the conductance-voltage (G-V) plot. Building on this observation, Li et al. first proposed that memristor intrinsically function as an artificial neuron, providing a hysteretic nonlinear activation function [137]. Furthermore, they proved that a circuit comprising a column of memristor connected to a grounded resistor (Figure 7a) constitutes an attractor network, with the externally applied voltage defining an antisymmetric weight matrix (Figure 7b). This network operates via KCL, enabling recursive behavior through device interactions. Specifically, each device’s state change couples dynamically to all others, and a resistance shift in one device generates circuit feedback that propagates changes throughout the network.

Attractor networks are primarily employed for associative memory, wherein attractors store memory content. As the network stabilizes, other states converge towards these corresponding attractors, achieving the associative memory recall. By formulating an energy function for memristor network and analyzing its properties, this work demonstrated that state transitions require overcoming an energy threshold (Figure 7c). This enables the network to store more attractors (a fraction of 2^N), surpassing the linear capacity scaling in current Hopfield networks [12,138,139,140]. Furthermore, previous implementations typically require specialized circuit designs and utilize relatively expensive amplifier circuits as neurons, suffering significant latency and power consumption penalties. In contrast, memristor networks comprise simple memristor arrays, where feedback operates continuously under KCL and accelerates attractor dynamics convergence.

4.3. Reservoir Computing and Spatiotemporal Signal Detection

Volatile memristors are particularly well suited for temporal and spatiotemporal signal processing. Their internal ionic or defect dynamics provide a controllable fading memory and intrinsic nonlinearity. The fading memory originates from ion migration and subsequent relaxation processes, which cause device responses to decay over characteristic time scales [86,141,142]. As a result, recent inputs strongly influence the current state, while the impact of older inputs gradually diminishes. This combination of short-term memory and nonlinear transduction makes volatile memristors natural candidates for hardware reservoir computing [143]. They are also effective for local spatiotemporal feature extraction in edge sensors.

A memristor-based reservoir maps time-varying inputs into a high-dimensional dynamical state. Only the readout layer is trained, keeping training simple and efficient. In hardware, the reservoir is formed by a set of volatile memristors. Their transient conductance changes encode the recent history of input pulses. Nonlinearity in device I–V characteristics and dynamic switching broaden the feature space. This improves separability of temporal patterns. Practical reservoir designs exploit these device-level properties together with input encoding and simple readout structures. They can perform classification, forecasting, and event detection in real time.

Experimental validation has employed arrays of 88 volatile memristors to build a compact reservoir. Input sequences were encoded as pulse trains, and the transient responses of the devices were used as reservoir states. A linear readout was trained to classify framed MNIST patterns and to predict nonlinear time series, with the same memristor dynamics simultaneously providing a fading memory of recent inputs and a nonlinear projection of temporal features. These are essential for framed-digit classification and time-series prediction in a small hardware footprint (Figure 8a,b) [144]. To further enhance state richness and resource efficiency, subsequent work combined simple masking with parallel device sampling [145]. This masked-parallel scheme generates virtual nodes from a limited number of physical devices through time-multiplexing. This approach achieved strong results on spoken-digit recognition and chaotic-series prediction (Figure 8c–h). However, this method faces a fundamental trade-off between hardware footprint and state richness. While generating virtual nodes conserves physical area, scalability remains inherently constrained. Increasing the mask length to expand state dimensionality dilutes the temporal feedback strength between sequential states [145]. This limits the maximum achievable complexity. Therefore, masked-parallel architectures suit resource-constrained edge scenarios [145]. True multi-device physical reservoirs remain essential for highly complex temporal tasks requiring massive parallelism and rich state topologies. The same research team later demonstrated a fully analog reservoir computing system in which volatile memristors serve as the reservoir and nonvolatile memristor arrays implement the readout layer. These systems enabled low-power, real-time spatiotemporal processing such as ECG and gesture recognition [146].

Beyond pure reservoir computing, volatile memristors have been integrated into adaptive neuromorphic perception pipelines [12,147,148,149,150,151,152,153,154]. These systems perform local spatiotemporal feature extraction and fast online adaptation. In these systems, memristor arrays implement tunable temporal kernels and rapid state updates that directly influence sensor-level decisions. For example, a differential neuromorphic pipeline was developed that uses memristor dynamics for near-sensor perception [147]. Their system enables fast adaptation in unstructured tasks and robust tactile and scene-level decision extraction in robotic scenarios (Figure 9), achieving low-latency responses by exploiting near-sensor processing that reduces data movement.

4.4. Spike-Timing-Dependent Plasticity

STDP is a local, timing-based synaptic learning rule [155,156]. It adjusts synaptic efficacy according to the relative timing of pre- and post-synaptic spikes. In the commonly used pair rule, the weight change follows

$$\begin{array}{c}\Delta w=A_{+}\mathrm{e}\mathrm{x}\mathrm{p}(-\Delta t/{\tau }_{+}) \mathrm{f}\mathrm{o}\mathrm{r} \Delta t>0,\\ \Delta w=-A_{-} \mathrm{e}\mathrm{x}\mathrm{p}(\Delta t/{\tau }_{-}) \mathrm{f}\mathrm{o}\mathrm{r} \Delta t<0.\end{array}.$$

(11)

where $\Delta t=t_{pre}-t_{post}$. Positive $\Delta t$ yields potentiation (LTP), and negative Δ$t$ yields depression (LTD) [155].

Hardware demonstrations have shown that memristors can implement STDP using simple spike protocols [157,158,159,160,161,162,163,164,165,166]. The first hardware evidence of memristor-based STDP was reported using a nonvolatile memristor as a synapse in a hybrid system that combined CMOS integrate-and-fire neurons with memristor-based synapses. In this system, the neuron circuit converted relative spike timing into pulse-width information to induce STDP [158]. Building on this foundation, passive memristor crossbars were integrated with analog leaky-integrate-and-fire (LIF) silicon neurons to experimentally measure the canonical pair-STDP window (Figure 10a) [167]. This work provided a practical route for device-level STDP in dense arrays. Pair-based STDP cannot capture all biological phenomena. Triplet-STDP models extend the rule by including higher-order spike interactions or trace variables. Devices with additional internal dynamics—so-called second-order memristors—can reproduce triplet effects. Device-level triplet-STDP has been demonstrated with weight updates under three-spike protocols (Figure 10b) [168]. The observed behavior matches triplet model predictions and highlights the role of internal device traces in shaping plasticity.

At system scale, STDP has been used for online learning and pattern tracking. Memristor-based synapses were integrated with simple spiking neurons [169]. Continuous online experiments were conducted in which synaptic weights evolved via STDP while the network learned and tracked spatiotemporal patterns (Figure 10c,d). These demonstrations validate that device-level plasticity can be harnessed for autonomous adaptation and unsupervised feature learning in hardware.

Beyond these core demonstrations, several research lines broaden the STDP rule. Studies on memristor-based stochasticity argue that device randomness can be used as a computational resource rather than only a defect; stochastic updates can improve exploration and generalization in some learning tasks [157]. System and architecture studies emphasize multi-memristor synapses, selector/transistor integration, and pulse engineering as practical routes to scalability and reliability [161,164].

4.5. Memristor-Enabled Stochastic Computation

Memristors exhibit intrinsic, pulse-dependent stochasticity originating from ion migration, filament nucleation/rupture and phase-transition kinetics [170]. Two measurable statistics summarize this behavior. One is the discrete switching probability $p_{\mathrm{s}\mathrm{w}\mathrm{i}\mathrm{t}\mathrm{c}\mathrm{h}}(V,t)$, which quantifies the likelihood that a device transitions between states under a specific pulse [171,172,173,174,175]. The other is the post-pulse multilevel conductance distribution, characterizing the continuous spectrum of conductance states that a device may assume after programming [176,177,178,179,180,181,182].

This device-level randomness can be repurposed as a computational resource through two complementary approaches. The first primitive is probabilistic bits (p-bits). Under near-threshold excitation, a memristor produces a binary outcome whose mean output follows a sigmoidal dependence on the applied bias; thus, modulating the bias directly tunes the sampling probability. Networks of p-bits realize hardware-native stochastic logic and can implement probabilistic primitives with minimal digital overhead. The second primitive is continuous conductance noise for Bayesian sampling and training. A single write pulse may produce a random conductance change; the distribution of such changes can sometimes be approximated as continuous and, under aggregation of multiple independent device currents, may approach a Gaussian perturbation via the central limit theorem. Such perturbations serve as the physical Langevin noise in memristor-based stochastic gradient Langevin dynamics (mSGLD) and other in-memory Bayesian update schemes.

Two representative experimental studies illustrate these modes. Cu_0.1Te_0.9/HfO₂Pt volatile memristors were demonstrated as reliable p-bit sources, with dynamic switching statistics systematically reported and a direct mapping established between pulse amplitude and sampling probability [171]. Small p-bit networks based on these devices were used to realize stochastic logic (Figure 11a,b). An in-memory deep Bayesian active-learning system was implemented [175]. This system leverages post-pulse conductance histograms, exploits device noise as the Langevin perturbation in mSGLD, and demonstrates improvements in labeling efficiency and energy consumption for active learning tasks (Figure 11c–e).

Additional works extend and validate these concepts across device types and applications. Versatile stochastic dot-product circuits have been demonstrated, exploiting controlled device and circuit variability to implement approximate probabilistic MVM operations suitable for edge inference [176]. Volatile memristors have been used to build stochastic neurons, enabling probabilistic spiking and Boltzmann-style sampling in neuromorphic circuits. NbO_x metal-insulator transition devices have been reported as self-oscillatory p-bits, broadening the set of physical primitives for stochastic computing [173].

5. Discussion

5.1. Functional Roles of Memristors Across AI Applications

Memristor-based accelerators for AI, whether leveraging static conductance for dense linear algebra or dynamic switching for temporal, logical, and stochastic operations, share a common hardware foundation and a common set of constraints. At the functional level, the applications summarized in

Table 3. Application statistics of static conductance and dynamic switching.

Application	Functional Role	Typical Device	Key Feature	Conductance States & Precision	Latency/Time Constants	Randomness Role	Endurance Stress	Peripheral Criticality
MVM	Synapse	Nonvolatile memristor: VCM, PCM, nonvolatile ECM (e.g., Ag/Ge30 Se70/W)	Highly parallel dot-products	Multilevel; medium precision (5–8 bits)	~10 ns	Harmful	Low (inference), high (training)	High (DAC/ADC, driver)
Closed-loop AMC circuits			Closed-loop for matrix computing (e.g., inversion)		50 ns to 10 μs (AMC topology-dependent)		High (second-order training), low (other tasks)	High (DAC/ADC, driver, op-amp)
Stateful logic	Neuron		Deterministic SET/RESET, binary	Binary or discretized multilevel; high precision	~10 ns		High (frequency switching)	Medium (pulse driver, selector)
Attractor networks					~100 ns
Stochastic computing—continuous noisy weights	Synapse		Analog statistical conductance	Multilevel; lower precision	~10 ns	Beneficial		Medium (sampling circuitry)
STDP			Pulse-induced incremental updates	Analog weight changes; low precision	100 μs to 100 ms	Mildly beneficial		High (pulse timing, neuron circuit)
Reservoir computing & spatiotemporal detection		Volatile memristor: VOx, WOx, NbOx, volatile ECM (e.g., Ag/SiO2)	Fading memory, nonlinear I–V, tunable τ	Binary or discretized multilevel; lower precision	10 μs to 100 ms	Beneficial		Medium (analog readout)
Stochastic computing—p-bit	Neuron		Probabilistic switching	Binary; 1-bit precision	~100 ns	Beneficial		Low (sampling circuitry)
Hybrid static + dynamic (SNN, reservoir computing)	Synapse (static), Neuron (dynamic)	Volatile (static) + nonvolatile (dynamic)	Co-design of static MVM and transient dynamics	Multilevel (static), binary/fading (dynamic)	~10 ns (static), 10 μs to 100 ms (dynamic)	Harmful (static), beneficial (dynamic)	Low (static), High (dynamic)	High (heterogeneous integration)

can first be distinguished according to whether memristors play synaptic or neuronal roles. Synaptic functions primarily store or modulate weights and therefore implement linear accumulation or plasticity mechanisms, including MVM, closed-loop AMC, reservoir computing, STDP, and stochastic computing based on continuous noisy weights. By contrast, neuronal functions implement nonlinear activation, thresholding, or state evolution, and thus include attractor networks, stateful logic, and stochastic computing based on p-bit behavior. This distinction follows the general structure of NNs, where synapses provide weighted signal integration while neurons introduce nonlinear transformation and decision mechanisms.

In this framework, Table 3 serves as the organizing framework of the discussion: it summarizes each application in terms of the typical device type, key computational feature, conductance states and precision, latency or characteristic time constants, role of randomness, endurance stress, and peripheral criticality.

Key device parameters determine suitability for specific computational primitives. For clarity, two operational modes are distinguished. Nonvolatile memristors, such as VCM, ECM, and PCM, provide persistent multilevel conductances and are the preferred substrate for dense MVM and many stateful or deterministic functions, including MVM, closed-loop AMC solvers, stateful logic, attractor networks, and STDP. Volatile memristors, such as WOx, NbOx, VOx, and part of Ag/Cu devices, exhibit fast decay and spontaneous reset, making them well suited for reservoir computing and spatiotemporal signal detection [13,16,30,31,171]. Stochastic computing generally follows two routes: continuous noisy weights realized with programmed nonvolatile memristors, or p-bit streams generated by volatile memristors. Furthermore, integrating both static and dynamic characteristics within hybrid architectures enables the realization of more complex applications [142]. Mapping any AI primitive onto hardware therefore begins with selecting device physics that match its functional role, namely persistence versus fading memory and deterministic versus stochastic behavior.

Table 3 further reveals that the same physical nonideality can play opposite roles depending on the application. Randomness is harmful for MVM and stateful logic when accuracy and determinism are required, but it becomes beneficial for reservoir computing and stochastic computing, where the device variability itself provides the computational resource [5]. Likewise, the required number of conductance states differs sharply across applications: MVM and closed-loop AMC solver benefit from multilevel states, stateful logic is naturally binary or discretized multilevel, whereas reservoir computing and STDP tolerate lower precision. The latency or characteristic time constant also separates the application classes, from nanosecond-scale latency in MVM and stateful logic to microsecond-to-millisecond-scale dynamics in reservoir computing and STDP.

In this sense, Table 3 is not only a summary of device features, but also a practical map between physical behavior and algorithmic role. It captures why the same memristor-based platform can support dense analog computing, digital in-memory logic, temporal signal processing, and probabilistic sampling, while also clarifying which applications are dominated by precision, which are dominated by timing, and which are dominated by controlled stochasticity.

To contextualize the system-level benefits of these functional roles,

Table 4. Performance summary of memristor-based computing systems across diverse applications.

Application	Problem	Array Size	Baseline Platform	Speedup	Energy Efficiency	Ref
MVM (CNN)	CIFAR-10	256 × 256	—	43 TOPS/W (peak)		[48]
AMC—linear regression	Signal processing	64 × 32	NVIDIA RTX 8000 GPU	—	1500×	[96]
AMC—Second-order Training	MNIST	256 × 256	NVIDIA V100 GPU	115.8×	41.9×	[99]
AMC—QP	Micro air vehicles control	100 × 100	STM32F405 MCU	2000×	5800×	[94]
AMC—PCA	Eigenface reconstruction	100 × 100	—	21 TFLOPS/W		[82]
Stateful logic (CNN)	ImageNet	1024 × 1024	NVIDIA GTX 1080 GPU	303.2×	297.9×	[128]
Attractor networks	associative memory	8 attractors	—	~100 ns	—	[137]
Reservoir computing	Gesture recognition	10 reservoirs	Intel i5-4460T CPU	Real-time	~1000×	[146]
STDP	Visual pattern learning	18 synapses	CMOS neuromorphic systems	~100×	—	[169]
Stochastic computing—continuous noisy weights	Robot’s pouring skill learning	4K	NVIDIA A100 GPU	1.44×	153×	[175]
Stochastic computing—p-bit	Boolean logic	4K	CMOS ALU, Quantum computing	One-shot	Low	[171]

Note: “—” indicates data not reported or not applicable.

summarizes the quantitative performance advantages of memristor-based accelerators across various applications. Compared to conventional digital baselines, memristor-based implementations consistently demonstrate significant improvements in energy efficiency and latency. For instance, AMC architectures can deliver orders-of-magnitude energy savings for optimization tasks, while crossbar-based static conductance implementations drastically accelerate neural network inference and training. By centralizing these metrics, it becomes evident that while different applications exploit different device physics, they share the overarching architectural benefit of reducing data movement and leveraging massive parallelism.

5.2. Practical Deployment Challenges and Mitigations

Although the application landscape is broad, practical deployment is still constrained by several interacting bottlenecks. For static conductance-based computing, accuracy and long-term stability are paramount [40]. Whether executing dense MVM or closed-loop AMC solvers, the effective numerical accuracy is limited by device nonlinearity, conductance variation, finite state resolution, and circuit noise [183,184]. High-precision analog computing explicitly treats reading noise and writing variability as primary obstacles, demonstrating that precision improvements require architectural co-design rather than device optimization alone. Recent work shows that arbitrarily high precision can be approached through carefully designed programming protocols and architecture-level error management, but at the cost of additional hardware and control complexity [35].

For MVM, the main practical response to this precision bottleneck has been bit slicing, mixed precision accumulation, and calibration-assisted mapping [34,48,185,186]. Bit slicing distributes one high-precision operation across multiple lower-precision arrays or multiple readout cycles and then recombines the partial results, which improves effective precision but inevitably increases array count, peripheral activity, and recombination cost [185]. The benefit is therefore not free precision, but a controlled precision energy trade off: more hardware and more readout steps obtain better accuracy, yet the system must still preserve the throughput advantage that motivated memristor-based MVM in the first place. This is especially important as array dimension grows, because wire resistance, voltage drop, and device mismatch all accumulate and amplify output error [48,183].

Closed-loop AMC circuit faces a different, and in some sense harder, precision problem. The closed-loop AMC solver is not only affected by the same conductance variability and interconnect resistance as MVM, but also by the stability of the feedback loop itself. Op-amp bandwidth, offset, settling dynamics, and loop gain all enter the accuracy equation, so the closed-loop AMC solver can become fragile long before the device array reaches its nominal size [79]. BlockAMC addresses the scalability barrier of large AMC by partitioning a large matrix into smaller block matrices that can be mapped to hardware-feasible array sizes, and by reconstructing the global solution from block-level solves [187]. To address the precision limitations of closed-loop AMC solvers, iterative refinement schemes leverage MVM to progressively minimize residual errors, combining an initial low-precision analog solution with high-precision MVM updates [188].

For dynamic switching applications, the dominant challenge is not only numerical precision, but also timing, endurance, and the controlled exploitation of stochasticity [189,190]. Stateful logic is a Boolean operation, so its scaling challenge is not correctness of the primitive itself, but the degree of parallel execution and the routing complexity needed to chain many gate instances. In practice, the output of stateful logic depends on the switching probability of the memristor and on the precise pulse conditions used to induce SET or RESET transitions. When many logic stages are cascaded, these probabilistic switching errors and the associated pulse propagation delay can accumulate, which increases the risk of incorrect outputs and reduces overall throughput. As a result, error correction or redundancy may be needed to maintain acceptable reliability. Reservoir computing scales differently. Its performance depends more on state richness, temporal diversity, and the matching between device time constants and task dynamics than on the raw size of the array. Experimental work shows that mask length and input scaling can tune reservoir richness, and that virtual node generation allows a small number of physical devices to emulate a much larger effective high-dimensional reservoir [145,191]. Thus, reservoir scalability is often improved through architectural expansion of the effective state space, rather than solely by increasing the number of physical devices.

Attractor networks, STDP, and stochastic computing have their own deployment limits. For attractor networks, the issue is not simply size, but the preservation of a stable energy landscape as the number of stored attractors increases. Once device mismatch and stochastic switching accumulate, the separation between attractor basins can blur, making recall less reliable [137]. For STDP, the challenge is precise spike timing, update symmetry, and reproducibility across many updates. For stochastic computing, the challenge is whether the switching statistics remain well calibrated over time so that probabilistic behavior stays meaningful rather than drifting into uncontrolled noise [167,171]. In these dynamic settings, the performance bottleneck is often the fidelity of local update statistics.

Across both modalities, manufacturing and commercialization impose constraints that extend beyond laboratory demonstrations. Practical memristor systems must be compatible with backend processing, foundry rules, and wafer-level yield requirements. Reported foundry-compatible crossbar circuits already demonstrate that low-temperature processing and high yield are possible, but they also make clear that variability control and device uniformity remain central to system-level accuracy [192]. More broadly, scalable deployment requires compact models, standardized test flows, and calibration procedures that can be used in a production design environment [193]. Without these ingredients, even impressive device demonstrations remain difficult to translate into reliable products. In this respect, commercialization is not only a materials issue, but also a software and verification issue, because the system must be predictable enough to be deployed repeatedly rather than just characterized once in a laboratory.

5.3. Future Research Directions

Future research should follow a full stack co-design path. At the device level, the field still needs improved control over linearity, symmetry, endurance, and conductance uniformity to support high-precision static workloads, alongside tunable relaxation kinetics and calibrated stochasticity for dynamic applications [48,170]. At the circuit level, more robust selectors, compensation schemes, and peripheral reduction strategies are needed to alleviate IR drop and ADC or DAC overhead. At the architecture level, the focus should shift toward heterogeneous integration, where static conductance arrays are deployed for deterministic linear algebra problem, dynamic switching substrates handle temporal and stochastic computations, and digital controllers manage orchestration, precision scaling, and error resilience [142]. At the algorithm level, hardware aware training, noise-aware optimization, and mixed-precision mapping should be developed together with device constraints in mind rather than as post hoc adaptations [89,193].

Complementing these hardware and algorithmic advances, software support is another important direction that has not yet been explored deeply enough. A realistic memristor-based computing platform will require robust compilers and toolchains that can map neural networks or optimization problems onto array tiles, schedule peripheral conversions, and manage precision decomposition automatically. Such software must also expose the hardware constraints to the user-level training framework, so that models can be adapted before deployment rather than after failure. This is especially important for LLMs and transformer-based systems, where hardware-aware training, blocked attention, and memory efficient key value handling are likely to be more effective than a direct mapping of full precision operations onto crossbar arrays [194]. In practice, the challenge is not merely accelerating individual computational primitives, but reducing end-to-end latency and data movement under realistic memory and bandwidth limits. Ultimately, establishing standardized compiler toolchains, robust calibration strategies, and reproducible system benchmarks will be essential before memristor-based accelerators can transition from laboratory prototypes to robust, deployable technologies.

Finally, deployment scenarios should be made more explicit. Edge systems, near sensor processing, and embedded neuromorphic platforms emphasize low-power, low-latency, and event-driven operation [42]. By contrast, larger scale accelerators emphasize throughput, bandwidth, and predictable integration with existing software stacks. A mature memristor-based AI ecosystem will therefore need to support both kinds of deployment, while matching hardware modalities to task structure. The most promising future direction is not a universal memristor platform for all applications, but a family of co-designed solutions in which device physics, circuit topology, algorithmic tolerance, compiler support, and deployment context are aligned for a specific class of workloads.

6. Conclusions

Memristors offer two complementary hardware primitives—static conductance and dynamic switching—that together open new pathways for energy-efficient, low-latency on-device AI. Static conductance in dense crossbar arrays enables highly parallel MVM and supports closed-loop AMC solvers. Together, these primitives directly accelerate core linear-algebra workloads in AI, spanning NN inference and training, as well as regression, classification, and constrained optimization tasks. Dynamic switching modality—spanning volatile relaxation, nonvolatile stateful transitions, and intrinsic stochasticity—supply fading memory, nonlinear activation, and probabilistic state transitions, enabling hardware-native implementations of stateful logic, attractor networks, reservoir computing, STDP, and Bayesian sampling. Together, these modalities permit compact implementations of both data-parallel and time-domain AI primitives.

Significant progress has been made at device, circuit, and system levels. Experimental demonstrations validate both static and dynamic paradigms. For instance, static crossbars have been shown to accelerate NN inference and one-step matrix equation solving, whereas dynamic switching substrates enable real-time reservoir computing, online STDP learning, and probabilistic Bayesian sampling. At the same time, non-idealities remain the major barrier to deployment. Device variability, stochastic switching, endurance and retention limits, wire parasitics, and peripheral overhead constrain achievable accuracy, throughput, and energy efficiency.

Realizing the full potential of practical memristor-based AI requires integrated solutions. We advocate coordinated device–circuit–algorithm co-design, task-specific heterogeneous architectures that strategically assign each modality to its most effective, robust calibration and pulse-engineering strategies, and standardized software toolchains for automated workload mapping. Standardized benchmarks and reproducible system demonstrations will be essential to quantify benefits. With these efforts, memristor technologies can move from compelling laboratory demonstrations to scalable, application-ready accelerators, fundamentally reshaping the landscape of next-generation, hardware-native AI.