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Article

A Wide-Range Soft-Switching AHB-Flyback Converter for Flat-Top Pulsed Magnetic Field Power Supplies

Wuhan High Magnetic Field Center, Huazhong University of Science and Technology, Wuhan 430074, China
*
Author to whom correspondence should be addressed.
Electronics 2026, 15(10), 1997; https://doi.org/10.3390/electronics15101997
Submission received: 26 March 2026 / Revised: 21 April 2026 / Accepted: 3 May 2026 / Published: 8 May 2026
(This article belongs to the Special Issue Advances in Power Electronics Converters for Modern Power Systems)

Abstract

The central adjustment coil of a gasdynamic Electron Cyclotron Resonance (ECR) ion source requires wide-range bipolar current regulation over ±100 A with flat-top stability within 0.1% (1000 ppm) and a current rise time below 4 ms. Conventional fully controlled H-bridge converters operating under hard-switching conditions are unable to satisfy these requirements simultaneously, as the switching loss penalty restricts the control bandwidth and degrades flat-top stability. This paper presents an Asymmetrical Half-Bridge Flyback (AHB-Flyback) converter specifically designed for this application. By incorporating a dedicated resonant branch L r C r on the primary side, the converter achieves primary-side Zero-Voltage Switching (ZVS) and secondary-side Zero-Current Switching (ZCS) over the full operating range, enabling 100 kHz operation without incurring the switching losses that would otherwise limit control bandwidth. A decoupled energy management architecture is adopted in which the primary circuit pre-charges an energy storage capacitor during idle intervals, and the coil current is subsequently established through an autonomous capacitor-to-coil discharge, effectively decoupling the peak power demand from the upstream supply network. The operating modes of the flat-top maintenance stage are analyzed through time-domain state equations, yielding an explicit closed-form expression for the Mode 3 duty cycle D T 3 . This expression demonstrates that D T 3 is determined solely by the switching frequency and circuit parameters, independent of the load current setpoint, which is the fundamental mechanism enabling stable wide-range current regulation without parameter re-tuning. Parameter selection guidelines are derived from this result. Simulation results across the 20–100 A operating range and experimental validation on a scaled prototype confirm flat-top current stability within 1000 ppm and a current rise time of 4 ms, demonstrating the suitability of the proposed converter for precision ECR ion source power supply applications.

1. Introduction

High-current gasdynamic Electron Cyclotron Resonance (ECR) ion sources are indispensable for generating high-brightness ion beams in nuclear physics research [1,2]. The precise configuration of a minimum-B magnetic field requires the mirror ratio R to be accurately regulated by a central adjustment coil, which demands an excitation current adjustable within a ± 100 A range [3,4]. Magnet power supplies for ion-source applications cover a wide spectrum of topology choices, each optimized for a specific application envelope. For high-field superconducting main coils, DC power supplies with direct IGBT switch control have been adopted in the development of fourth-generation ECR ion source magnets, providing robust current regulation at the rated operating point [5]. While simple and reliable, such architectures lack inherent wide-range adjustability: the DC bus voltage is sized for peak-current operation and the switching devices experience similar electrical stress regardless of the operating setpoint, limiting their applicability to fixed-duty operations. For ion beam focusing, specialized solenoid magnets have been designed to produce tailored field profiles [6]; these designs emphasize magnet-side optimization while leaving the flexibility of the associated power supply as the determining factor for system-level adaptability.
For pulsed magnetic field generation, open-loop discharge schemes have been applied to laser-ion-source scenarios where the usable pulse duration is naturally short: for instance, a pulsed magnetic field of only ∼ 400 μ s duration has been reported for laser-ion-source current-waveform control [7]. Such open-loop schemes do not incorporate a flat-top regulation stage, which renders them unsuitable for applications requiring stable field conditions throughout the ion beam extraction window. At the DC-regulated end of the spectrum, multi-phase interleaved Buck converters combined with LC-RC output filters have been used to generate high-stability DC magnetic fields [8], providing low output ripple suitable for continuous operation. These architectures, however, are designed for steady-state DC currents and do not address the rapid current establishment required for pulsed flat-top operation.
The central adjustment coil of an ECR ion source occupies a distinct operating envelope that none of the above architectures directly addresses: it requires (i) bipolar wide-range current regulation over ± 100 A, (ii) millisecond-scale rise time, and (iii) 1000 ppm flat-top stability during each pulse. The following subsection examines existing FTPMF power supply technologies against this requirement set.
Currently, power supplies for these coils predominantly utilize conventional fully controlled H-bridge topologies, as depicted in Figure 1. However, these converters operate under hard-switching conditions, where switching losses scale proportionally with the operating frequency. The resulting thermal dissipation constrains the practically achievable switching frequency to a low level (typically below 20 kHz), which in turn limits the attainable closed-loop control bandwidth and results in a flat-top current stability of only approximately 1%. Furthermore, in conventional H-bridge configurations, the coil current is established by sustaining the full DC bus voltage directly across the inductive load. The instantaneous power drawn from the supply therefore reaches its maximum at the end of the excitation interval when the load current is at its peak value. This transient power concentration imposes considerable stress on the upstream power network and may compromise the stability of adjacent electromagnetically sensitive instruments.
Extensive research on Flat-Top Pulsed Magnetic Field (FTPMF) power supplies has yielded a range of regulation strategies aimed at improving flat-top quality [9,10,11]. These include active bypass regulation employing IGBTs operating in the active region [12], sequentially fired pulse-forming networks [13], active closed-loop regulation schemes [14], and hybrid topologies combining capacitor banks with battery storage to handle heavily inductive loads [15]. Although these architectures improve flat-top stability, they generally rely on either hard-switching operation or complex multi-stage circuit configurations, which constrains the overall system efficiency and control bandwidth. Moreover, the requirement for wide-range bipolar current regulation at medium power levels, as encountered in ECR adjustment coil applications, introduces additional demands that are not fully addressed by the topologies developed for high-power single-polarity pulsed field generation.
To address these limitations, this article proposes a wide-range soft-switching Asymmetrical Half-Bridge Flyback (AHB-Flyback) converter [16,17,18]. By realizing primary-side Zero-Voltage Switching (ZVS) and secondary-side Zero-Current Switching (ZCS), the proposed topology eliminates the switching losses that would otherwise prohibit high-frequency operation. This allows the system to operate at 100 kHz, providing sufficient control resolution to achieve a flat-top current stability within 0.1% (1000 ppm).
Crucially, the proposed converter adopts a decoupled energy management architecture to mitigate transient loading of the power network. During idle intervals, the primary-side AHB circuit operates in a constant-power charging mode to pre-charge an energy storage capacitor C c h , presenting a smooth and sustained power demand to the DC bus. During the excitation phase, the primary switches remain inactive and the stored energy is delivered to the load through an autonomous capacitor-to-coil RLC discharge circuit. This separation of the energy storage and delivery functions effectively decouples the peak power demand from the supply network, enabling a 4 ms current rise time without inducing transient disturbances on the upstream bus.
The main contributions of this work are as follows: (1) a comprehensive time-domain analytical model is established for all resonant modes during both the charging and flat-top stages; (2) an explicit closed-form expression for the Mode 3 duty cycle D T 3 is derived, demonstrating its independence from the load current setpoint and thereby enabling wide-range current regulation without parameter re-tuning; and (3) experimental validation on a scaled prototype confirms stable 1000 ppm flat-top output and low transient impact on the supply network.

2. Operating Principle and Modeling Analysis of AHB-Flyback Flat-Top Topology

2.1. Circuit Structure

The flat-top current converter structure based on AHB-Flyback is shown in Figure 2. This circuit primarily consists of an asymmetrical half-bridge main power stage, an isolation transformer, a secondary rectification stage, an energy storage capacitor, and a discharge control circuit. The main power stage comprises an upper transistor Q 1 and a lower transistor Q 2 forming an asymmetrical half-bridge structure, which provides high-frequency excitation to the transformer’s primary side through alternating conduction. The transformer magnetizing inductance L m and the resonant branch L r , C r jointly determine the resonant characteristics and soft-switching conditions, achieving ZVS over a wide power range. The secondary side consists of a rectifier diode D 1 , an energy storage capacitor C c h , and a discharge control branch. The energy storage capacitor receives the energy transferred from the primary side and, upon completion of charging, releases it to the coil load L load through the discharge branch to achieve a rapid current rise. The discharge branch includes three sets of control switches: S Charge , S Drain , and S Discharge . The load coil is connected to the full-bridge unit S1S4, which regulates the current direction based on the control logic to achieve bipolar magnetic field output.
During operation, the circuit sequentially undergoes five stages: capacitor charging, capacitor-to-coil discharging, flat-top maintenance, energy recovery, and capacitor recharging. These five stages cycle periodically to produce a continuous flat-top magnetic field. Only the capacitor-charging and flat-top maintenance stages require the primary-side AHB-Flyback circuit to participate in energy transfer; in the remaining stages, the primary switches Q 1 and Q 2 remain off. Thanks to the resonant cavity formed by L r and C r , the primary switching devices achieve ZVS turn-on during the dead time, while the secondary diode achieves ZCS when the current naturally decays to zero, significantly reducing switching losses and device stress.
Unlike traditional AHB-Flyback circuits where L m L r , the AHB-Flyback circuit utilized in this study introduces an additional resonant inductance L r to the primary side. The resonant cavity stores more energy, facilitating soft switching, and gain regulation is achieved through simultaneous frequency and duty-cycle modulation. Consequently, the system operates closer to LLC characteristics, necessitating a re-derivation of its gain characteristics and ZVS conditions.

2.2. General Gain Model Based on First Harmonic Approximation

Since the resonant inductance L r is on the same order of magnitude as the primary magnetizing inductance L m , the resonant tank exhibits strong band-pass filtering characteristics. Therefore, the First Harmonic Approximation (FHA) method is employed to derive the voltage gain. The equivalent circuit model is shown in Figure 3.
Ignoring the dead time, Q 1 and Q 2 operate complementarily with duty cycles D and 1 D . The fundamental RMS voltage V i n , F H A at the input terminal of the resonant tank is
V i n , F H A = 2 π V d c sin ( π D )
Assuming that the secondary output voltage is V o , the fundamental voltage amplitude at the transformer secondary side V o , F H A is related to V o via an equivalent coefficient α V :
V o , F H A = α V N V o
Similarly, the equivalent AC resistance R a c reflected to the primary side is
R a c = α R N 2 R o
In the frequency domain, the primary resonant cavity consists of a series branch ( L r , C r ) and a parallel branch ( L m R ac ) , whose impedances are, respectively,
Z s = j ω L r 1 ω C r ,
Z p = j ω L m R ac R ac + j ω L m .
The transfer function between the primary parallel branch voltage and the fundamental source voltage is
H ( ω ) = V o , F H A V i n , F H A = Z p Z s + Z p .
Defining the normalized frequency f n = f s / f r , quality factor Q = Z r / R a c , and inductance ratio k = L m / L r , the magnitude of H ( ω ) is
| H ( f n , Q ) | = 1 1 + 1 k 1 k f n 2 2 + Q 2 f n 1 f n 2
As shown in Figure 4, the gain curve is consistent with that of an LLC resonant circuit. The peak of the gain curve divides the operating region into a capacitive region (ZCS region) on the left and an inductive region (ZVS region) on the right. The converter is designed to operate in the inductive region (to the right of the gain curve peak) to achieve ZVS for the primary switches.
Combining Equations (1) and (2), the total DC voltage gain M from V i n to V o is derived as
M ( f n , D , Q ) = 2 sin ( π D ) π α V N · 1 1 + 1 k 1 k f n 2 2 + Q 2 f n 1 f n 2
Equation (8) indicates that the output voltage of the AHB-Flyback converter is not only regulated by the switching frequency f s but also explicitly modulated by the duty cycle D. Although the FHA-based gain derivation above is formally analogous to that of a standard LLC resonant converter, the proposed circuit differs from both the conventional LLC and the traditional AHB-Flyback converter in two fundamental respects:
(1) Duty-cycle modulation of the input fundamental. In a symmetric half-bridge or full-bridge LLC converter, the two legs operate at a fixed 50% duty cycle, and the amplitude of the input fundamental is therefore a constant ( 2 / π ) V d c . In the proposed AHB-Flyback, Q 1 and Q 2 operate complementarily with duty cycles D and ( 1 D ) , which introduces the modulation factor sin ( π D ) into the input fundamental expression (Equation (1)). This gives the converter a second independent control variable in addition to the switching frequency, whereas a conventional LLC converter can only regulate its output gain by varying f s . This feature is particularly valuable for the present application, since the output current must be adjustable over a wide range without forcing the switching frequency to deviate excessively from the optimal ZVS operating point. (2) Non-negligible resonant inductance relative to the magnetizing inductance. Traditional AHB-Flyback converters are designed under the assumption L m L r , so that the magnetizing inductance dominates the primary-side energy storage and the converter behavior reduces to a duty-cycle-controlled volt-second balance on L m , with a gain that is essentially load-independent and proportional to D. The circuit analyzed here deliberately introduces an explicit resonant inductor L r whose value is of the same order of magnitude as L m ( k = L m / L r = 3 in this design). As a consequence, the gain can no longer be approximated by the simple duty-cycle expression of a conventional AHB-Flyback. Instead, the resonant tank L r C r L m jointly shapes the gain characteristic, which becomes a two-variable function of both f n and D, as expressed in Equation (8). This is the reason a dedicated re-derivation of the gain model is necessary rather than a direct reuse of either the AHB-Flyback or the LLC result.
These two distinctions collectively define the operating characteristics of the proposed converter and motivate the dedicated time-domain analysis presented in the following section.

2.3. Operating Principle and Time-Domain Modeling Analysis

The following analysis assumes: (1) all switching devices are ideal with zero on-state voltage drop and instantaneous switching transitions; (2) the transformer is modeled by its magnetizing inductance L m and an ideal turns ratio N, with winding resistance neglected; (3) dead time is negligible relative to the switching period (at 100 kHz with a dead time of approximately 100 ns, the dead-time fraction is less than 1%); (4) the resonant capacitor voltage varies negligibly within the short duration of each sub-interval transition. The impact of these simplifications on model accuracy is assessed through comparison with PLECS simulation results, which inherently include device non-idealities, in Section 4.
The overall operating process of the AHB-Flyback flat-top converter is divided into five main stages. Among these, only the capacitor-charging and flat-top maintenance stages require primary-side energy transfer.

2.3.1. Capacitor-Charging Stage

As shown in Figure 5, during the capacitor-charging stage, the circuit operates in DCM mode. Based on whether the secondary diode conducts and on the polarity of the resonant tank input voltage, four resonant modes arise: positive LLC, negative LLC, positive LC, and negative LC. Their equivalent circuits are shown in Figure 6.
Taking the state variables as x [ i L r v C r i L m ] and defining the initial values at the start of each mode t k as v k v C r ( t k ) , i k i L r ( t k ) , i m , k i L m ( t k ) , the time-domain solutions for the four modes are derived as follows:
(1) Positive LLC Resonant Mode: Secondary is cut off. V in = V dc . Setting ω LLC = 1 / ( L r + L m ) C r , the time-domain solution is
v C r ( t ) = 1 D V dc + v k 1 D V dc cos ω LLC ( t t k ) + i k C r ω LLC sin ω LLC ( t t k ) , i L r ( t ) = C r ω LLC v k 1 D V dc sin ω LLC ( t t k ) + i k cos ω LLC ( t t k ) , i L m ( t ) = i L r ( t ) .
(2) Negative LLC Resonant Mode: Secondary is cut off. V in = 0 .
v C r ( t ) = D V dc + v k + D V dc cos ω LLC ( t t k ) + i k C r ω LLC sin ω LLC ( t t k ) , i L r ( t ) = C r ω LLC v k + D V dc sin ω LLC ( t t k ) + i k cos ω LLC ( t t k ) , i L m ( t ) = i L r ( t ) .
(3) Positive LC Resonant Mode: Secondary conducts. V in = V dc . Setting ω L C = 1 / L r C r ,
v C r ( t ) = ( 1 D ) V dc + N V o + v k ( 1 D ) V dc N V o cos ω L C ( t t k ) + i k C r ω L C sin ω L C ( t t k ) , i L r ( t ) = C r ω L C v k ( 1 D ) V dc N V o sin ω L C ( t t k ) + i k cos ω L C ( t t k ) , i L m ( t ) = i m , k N V o L m ( t t k ) .
(4) Negative LC Resonant Mode: Secondary conducts. V in = 0 .
v C r ( t ) = D V dc + N V o + v k + D V dc N V o cos ω L C ( t t k ) + i k C r ω L C sin ω L C ( t t k ) , i L r ( t ) = C r ω L C v k + D V dc N V o sin ω L C ( t t k ) + i k cos ω L C ( t t k ) , i L m ( t ) = i m , k N V o L m ( t t k ) .
Depending on whether the secondary diode experiences a delayed turn-on during the lower transistor conduction phase, the charging process is divided into DCM1 and DCM2 modes. Regardless of the mode, as long as the circuit operates in the ZVS region, ZVS for Q 1 and Q 2 can be achieved. Upon reaching the target voltage V chset , the circuit stops switching, and residual energy is dissipated.

2.3.2. Capacitor-to-Coil Discharging Stage

Once the storage capacitor C c h is charged to V chset , the primary AHB-Flyback circuit halts and the storage capacitor discharges to the load coil L load via the full bridge (Figure 7). Taking the forward discharge as an example, with the coil modeled as L load in series with R eq , the state-space equation is
x ˙ ( t ) = R eq L load 1 L load 1 C ch 0 i L ( t ) v ch ( t ) .
Since R eq < 2 L load / C ch in practice, the circuit is underdamped. Defining the damping coefficient α = R eq / ( 2 L load ) and the damped oscillation frequency ω d = 1 / ( L load C ch ) α 2 , the analytical solution for the coil current i L ( t ) starting from rest at t = t 0 is
i L ( t ) = V chset ω d L load e α ( t t 0 ) sin ω d ( t t 0 ) .
Since the discharge time is very short ( t t 0 1 / ω d ), using the approximations sin ( θ ) θ and e α t 1 , this simplifies to a near-linear current rise:
i L ( t ) V chset L load ( t t 0 ) .
This confirms that the current ramp rate during the discharge stage is primarily determined by the capacitor initial voltage and the load inductance, enabling fast and predictable current establishment.

2.3.3. Flat-Top Maintenance Stage

During the flat-top maintenance stage, the AHB-Flyback circuit resumes switching to provide dynamic compensation to the load current, as shown in Figure 8. By controlling the alternating conduction of Q 1 and Q 2 and adjusting their duty cycles, the secondary-side output is dynamically balanced with the coil load current, thereby maintaining a stable flat-top current. Since the load is inductive, ZVS is maintained throughout this stage in the same manner as during the DCM1 charging mode; the soft-switching mechanism therefore will not be repeated here. For the purpose of time-domain modeling, the dead time is neglected and only equivalent circuits are presented. Because the load current fluctuates only slightly around I ref , the load is approximated as a voltage source N V out = I ref N 2 R load in series with an inductance N 2 L load (both referred to the primary).
The flat-top maintenance cycle consists of five modes. The load current rises only during Mode 3 and decays through the freewheeling diode D S (the body diode of the reverse-biased secondary H-bridge arm) in all other modes. The key waveforms i L r , i L m , i out , and i load over one switching period [ t 0 , t 0 + T s ) are shown in Figure 9. The time-domain solutions for each mode are derived by applying KVL to the primary resonant tank and combining with the secondary-side circuit equations.
Mode 1 ( t 0 t 1 ): Q 1 conducts, V in = V dc , and the secondary rectifier D 1 is reverse-biased, as depicted in Figure 10. No energy is transferred to the secondary side. The primary resonant current i L r flows entirely through the magnetizing inductance, i.e., i L m = i L r , and the primary and secondary sides are decoupled. The transformer appears on the primary side as the magnetizing inductance L m , so the primary resonant tank evolves along the L r + L m C r trajectory. On the secondary side, the load current freewheels through the body diode of the reverse-biased H-bridge arm, which is collectively represented by D S .
Applying KVL to the primary resonant loop yields the state equations
( L r + L m ) d i L r d t = V dc v C r tot , C r d v C r tot d t = i L r .
Defining the LLC resonant angular frequency ω L L C and characteristic impedance Z L L C as
ω L L C = 1 ( L r + L m ) C r , Z L L C = L r + L m C r ,
and denoting the initial values at t 0 as I L r ( t 0 ) and V C r ( t 0 ) , the primary time-domain solution is
i L r ( t ) = i L m ( t ) = I L r ( t 0 ) cos ω L L C ( t t 0 ) + V dc V C r ( t 0 ) Z L L C sin ω L L C ( t t 0 ) , v C r tot ( t ) = V dc V dc V C r ( t 0 ) cos ω L L C ( t t 0 ) + Z L L C I L r ( t 0 ) sin ω L L C ( t t 0 ) .
For the secondary-side load loop, the load current i load freewheels through D S . Since the load has been represented as a referred voltage source N V out in series with N 2 L load , the referred load-loop equation is
N 2 L load d ( i load / N ) d t + N V out = 0 ,
which simplifies to a constant rate of change
d i load d t = V out L load .
Hence, during Mode 1, the load current decreases linearly. With the initial value i load ( t 0 ) at t 0 , the time-domain solution is
i load ( t ) = i load ( t 0 ) V out L load ( t t 0 ) ,
and the freewheeling diode current equals the load current:
i D S ( t ) = i load ( t ) .
Mode 1 ends at t 1 , when Q 1 turns off.
Mode 2 ( t 1 t 2 ): Q 1 turns off, V in switches to 0, and the secondary rectifier D 1 begins to conduct, transferring energy to the secondary side. As shown in Figure 11, because both D 1 and D S conduct simultaneously, the transformer secondary winding voltage is clamped to approximately zero, which also clamps the voltage across L m to zero. As a result, L m does not participate in the resonance, and the primary tank reduces to a series L r C r resonance. The state equations are
L r d i L r d t = v C r D V dc , C r d v C r d t = i L r , d i L m d t = 0 .
Defining the LC resonant parameters as
ω L C = 1 L r C r , Z L C = L r C r ,
and using the substitution v C r tot = v C r + D V dc , the magnetizing current remains constant:
i L m ( t ) = i L m ( t 1 ) = const .
With initial values I L r ( t 1 ) and V C r tot ( t 1 ) at t 1 , the primary time-domain solution is
i L r ( t ) = I L r ( t 1 ) cos ω L C ( t t 1 ) V C r tot ( t 1 ) Z L C sin ω L C ( t t 1 ) , v C r tot ( t ) = V C r tot ( t 1 ) cos ω L C ( t t 1 ) + Z L C I L r ( t 1 ) sin ω L C ( t t 1 ) .
The secondary-side state variables are derived as follows: Since the transformer winding voltage is clamped to zero, the load inductance L load sees the same input-node voltage as in Mode 1, so the load current continues to decrease linearly:
i load ( t ) = i load ( t 1 ) V out L load ( t t 1 ) .
For the transformer output current i out , applying Ampere’s law (equivalently, the magnetomotive-force balance across the transformer) gives
i L r = i L m + 1 N i out .
Since i L m is constant during Mode 2, the output current is
i out ( t ) = N i L r ( t ) i L m ( t 1 ) ,
which is obtained explicitly by substituting i L r ( t ) from Equation (26). The freewheeling diode current is then obtained from secondary-side KCL:
i D S ( t ) = i load ( t ) i out ( t ) .
During this mode, i L r transitions from positive to negative, causing i out to rise and i D S to fall. At t 2 , i D S ( t 2 ) = 0 and i out ( t 2 ) = i load ( t 2 ) , whereby D S turns off naturally (achieving ZCS and eliminating reverse-recovery loss), and the circuit transitions to Mode 3.
Mode 3 ( t 2 t 3 ): D S has turned off and remains reverse-biased by the negative voltage across L m until the next mode; D 1 continues to conduct, so the transformer output current equals the load current, i out = i load . The transformer secondary voltage is no longer clamped, and the primary input voltage V in = 0 . The circuit therefore becomes a series combination of L r C r with the parallel network of L m and the referred load branch, as illustrated in Figure 12.
Let L load = N 2 L load and V out = N V out denote the load inductance and output voltage referred to the primary. The parallel equivalent inductance L p of L m and L load is
L p = L m L load L m + L load ,
so the total equivalent primary inductance is L eq 3 = L r + L p . Applying KVL, the parallel branch voltage v p satisfies
v p = L p d i L r d t V out L load ,
and substituting into the primary-loop equation L r d i L r d t + v C r tot + v p = 0 yields
( L r + L p ) d i L r d t + v C r tot = L p V out L load = L m L m + L load N V out .
Defining the effective driving voltage
V drive = L m L m + N 2 L load N V out ,
and the Mode 3 resonant parameters
ω 3 = 1 L eq 3 C r , Z 3 = L eq 3 C r ,
with initial values I L r ( t 2 ) and V C r tot ( t 2 ) at t 2 , the primary resonant solution is
i L r ( t ) = I L r ( t 2 ) cos ω 3 ( t t 2 ) + V drive V C r tot ( t 2 ) Z 3 sin ω 3 ( t t 2 ) , v C r tot ( t ) = V drive V drive V C r tot ( t 2 ) cos ω 3 ( t t 2 ) + Z 3 I L r ( t 2 ) sin ω 3 ( t t 2 ) .
For the secondary side, since D S is off, i out ( t ) = i load ( t ) throughout Mode 3. From the parallel branch current-sharing relation (and accounting for the effect of the voltage source V out ), the load current rate of change is
d i load d t = N L load v p V out ,
where v p ( t ) = v C r tot ( t ) L r d i L r d t . Equivalently, the load current can also be obtained from
i load ( t ) = N i L r ( t ) i L m ( t ) ,
where i L m is no longer constant but is now driven by v p . Owing to the relatively large L m and the short duration of this mode, i load ( t ) may be approximated as tracking i L r ( t ) , which sustains the flat-top current. This mode ends at t 3 when v p rises back to zero; D S is no longer reverse-biased and begins to conduct, and the circuit transitions to Mode 4.
Mode 4 ( t 3 t 4 ): At t 3 , as v p rises to zero, D S starts to conduct again. The transformer output current i out begins to fall while the freewheeling diode current i D S rises from zero. With both D 1 and D S conducting, the transformer secondary winding is again short-circuited, clamping the voltage across L m to zero. The equivalent circuit is identical to that of Mode 2 (Figure 11): V in = 0 , and the circuit reduces to a series L r C r resonance with L m short-circuited.
The resonant parameters ω L C and Z L C are identical to those in Mode 2. Because the voltage across L m is zero, the magnetizing current remains at its t 3 value:
i L m ( t ) = i L m ( t 3 ) = const .
With initial values I L r ( t 3 ) and V C r tot ( t 3 ) at t 3 , the primary-side solution is
i L r ( t ) = I L r ( t 3 ) cos ω L C ( t t 3 ) V C r tot ( t 3 ) Z L C sin ω L C ( t t 3 ) , v C r tot ( t ) = V C r tot ( t 3 ) cos ω L C ( t t 3 ) + Z L C I L r ( t 3 ) sin ω L C ( t t 3 ) .
On the secondary side, the transformer winding voltage is clamped to zero, so the load inductance sees N V out across it (neglecting diode drops). The load current therefore continues its linear decay:
i load ( t ) = i load ( t 3 ) V out L load ( t t 3 ) .
A commutation between i out and i D S occurs during this mode. The transformer output current is determined by the primary current:
i out ( t ) = N i L r ( t ) i L m ( t 3 ) .
As shown in Figure 9, | i L r | decreases (or reverses) during Mode 4, causing i out to fall from its peak value. The freewheeling diode D S takes up the remaining load current:
i D S ( t ) = i load ( t ) i out ( t ) ,
which rises from zero. At t 4 , the input voltage jumps from 0 to V dc , and the circuit transitions to Mode 5.
Mode 5 ( t 4 t 0 + T S ): At t 4 , the primary upper switch Q 1 turns on, and the input voltage V in jumps from 0 to V dc . The secondary-side commutation is not yet complete, so both D S and D 1 remain conducting, keeping the voltage across L m clamped to zero. The equivalent circuit is shown in Figure 13. The circuit operates as a positive LC resonance driven by V dc , with L m short-circuited.
The primary resonant parameters ω L C and Z L C are identical to those in Modes 2 and 4. Since the voltage across L m remains zero, the magnetizing current is constant:
i L m ( t ) = i L m ( t 4 ) = const .
Applying KVL to the primary loop gives L r d i L r d t + v C r tot = V dc . With initial values I L r ( t 4 ) and V C r tot ( t 4 ) at t 4 , the primary time-domain solution is
i L r ( t ) = I L r ( t 4 ) cos ω L C ( t t 4 ) + V dc V C r tot ( t 4 ) Z L C sin ω L C ( t t 4 ) , v C r tot ( t ) = V dc V dc V C r tot ( t 4 ) cos ω L C ( t t 4 ) + Z L C I L r ( t 4 ) sin ω L C ( t t 4 ) .
Because the oscillation center is now V dc , i L r rises rapidly during this mode.
On the secondary side, D S remains on so the load-inductance input node is clamped to zero, and the load current continues its linear decay:
i load ( t ) = i load ( t 4 ) V out L load ( t t 4 ) .
The transformer output current rises as i L r increases (since i L r = i L m + i out / N with i L m constant):
i out ( t ) = N i L r ( t ) i L m ( t 4 ) ,
and the freewheeling diode current correspondingly decreases:
i D S ( t ) = i load ( t ) i out ( t ) .
At t 0 + T S , in steady state, i D S falls to exactly zero, D S turns off naturally with ZCS, and the circuit transitions back to Mode 1, completing one switching period.
The five stages above form a complete cyclic energy flow path: the primary AHB-Flyback circuit completes energy injection and steady-state compensation during the charging and flat-top stages, respectively; the secondary circuit handles energy transfer, recovery, and recharging during the remaining stages.

3. Analysis of Operating Characteristics and Parameter Calculation

3.1. Steady-State Balance Equation and Current Ripple

From the flat-top mode analysis, the load current rises only during Mode 3 and decays through the freewheeling diode in all other modes, as illustrated in Figure 14. Define the Mode 3 duty cycle as D T 3 = ( t 3 t 2 ) / T s .
During Mode 3, the load current rise is
Δ i rise = 1 L load L m U C r N ( L m + L r ) ω ( 1 cos ( ω D T 3 T s ) ) I ref R load D T 3 T s
During all remaining modes, the current fall is
Δ i fall = I ref R load L load ( 1 D T 3 ) T s
At steady state, Δ i rise = Δ i fall . After applying the trigonometric identity 1 cos ( 2 π D T 3 ) = 2 sin 2 ( π D T 3 ) and introducing a correction factor to account for the DC bias effect on the resonant capacitor voltage zero-crossing, the load current balance condition becomes
U C r = 1.1 π N I ref R load ( L m + L r ) L m sin 2 ( π D T 3 ) .
To eliminate the unknown U C r , we use the following approximation, valid when the magnetizing current ripple is much smaller than the resonant current amplitude and the resonant current is dominated by the load current:
I L r I ref 2 N , U C r I ref 4 π f s N C r .
Substituting into Equation (51) and canceling I ref , a key result is obtained:
D T 3 = 1 π arcsin 4 π 2 N 2 C r R load L m + L r L m · f s
This result shows that D T 3 depends only on the switching frequency f s and circuit parameters, and is independent of the load current setpoint I ref , the load inductance L load , and the supply voltage. This is the fundamental reason why the AHB-Flyback topology can maintain stable flat-top current regulation over a wide current range without re-tuning the operating point. Consequently, the peak-to-peak current ripple Δ i pp is
Δ i pp = I ref R load L load f s 1 1 π arcsin 4 π 2 N 2 C r R load L m + L r L m · f s
Equation (54) serves as a key design reference: for a given set of circuit parameters and load current command I ref , the ripple Δ i pp is a single-variable function of f s , making it straightforward to select the switching frequency to meet a ripple specification.

3.2. Gain Function and Maximum Stable Output Current

Using fundamental phasor analysis, the maximum input voltage fundamental component (achieved at D = 0.5 ) dictates the boundary of the maximum output current. Performing a Fourier decomposition of the piecewise equivalent magnetizing voltage u m ( t ) and establishing the phasor balance U i n 1 = U C r + U L r + U m 1 , and then substituting Equation (51), yields the general relationship between the DC bus voltage and the load current:
V d c = π 2 N I ref R load 2 k m sin 2 ( π D T 3 ) 1 ( 2 π f s ) 2 L r C r k m 2 D T 3 sin ( 4 π D T 3 ) 2 π 2 + k m π sin 2 ( 2 π D T 3 ) 2 ,
where
k m = L m L m + L r
is the resonant–magnetizing inductance ratio coefficient.

3.2.1. Normalized Gain as a Function of the Frequency Ratio f s / f o

To express Equation (55) in the conventional resonant-converter form with the frequency ratio f n = f s / f o as the independent variable, we define the series resonant frequency and the normalized load factor:
f o = 1 2 π L r C r , K = 2 π N 2 R load L m + L r L m C r L r .
The quantity K combines the load reflected to the primary and the characteristic impedance of the resonant tank, playing a role analogous to the quality factor of a conventional LLC converter. Substituting Equation (53) (recall from Equation (53) that D T 3 = 1 π arcsin K f n , which is independent of I ref ) into Equation (55) and rewriting the term ( 2 π f s ) 2 L r C r as f n 2 , the normalized gain becomes
G ( f n ) = N I ref R load V d c = 2 k m K f n π 2 Φ ( f n ) 2 + Ψ ( f n ) 2 ,
with
Φ ( f n ) = 1 f n 2 k m 2 π arcsin K f n 2 π K f n ( 1 K f n ) 1 2 K f n ,
Ψ ( f n ) = 4 k m π K f n ( 1 K f n ) .
Equation (58) is mathematically complete but not immediately useful as a design aid, because of the arcsine and nested square-root terms in Φ ( f n ) .

3.2.2. Engineering Approximation with Taylor Expansion

For typical FTPMF design conditions, the argument x K f n is small ( x 0.3 at the rated operating point). Applying the Taylor expansion of the arcsine function, arcsin x x + 1 6 x 3 / 2 + O ( x 5 / 2 ) , together with x ( 1 x ) ( 1 2 x ) x 5 2 x 3 / 2 , the bracketed term inside Φ ( f n ) reduces to a clean closed form:
2 π arcsin x 2 π x ( 1 x ) ( 1 2 x ) 16 3 π x 3 / 2 .
Substituting Equation (61) into Equation (58) gives the following compact engineering approximation accurate to O ( x 5 / 2 ) :
G ( f n ) = N I ref R load V d c 2 k m K f n π 2 1 f n 2 16 k m 3 π ( K f n ) 3 / 2 2 + 4 k m π K f n ( 1 K f n ) 2 .
This form preserves the essential resonant-gain behavior while expressing the gain as an explicit algebraic function of f n , K and k m . The numerator grows linearly with f n , and the denominator captures both the LC resonant detuning ( 1 f n 2 ) and the load-induced damping through the K f n terms.

3.2.3. Gain Curves and Design Boundary

Figure 15 plots the normalized gain of Equation (62) as a function of f n for k m and K corresponding to the design parameters ( L m / L r = 3 , nominal load R load = 77.991 mΩ). For comparison, the gain computed from the full expression (Equation (58)) is also shown; the two curves are indistinguishable in the operating frequency range, confirming the accuracy of the approximation.
The gain curve rises from low values in the capacitive region ( f n < 1 ), peaks near the series resonant frequency (slightly below f n = 1 ), and decreases in the inductive (ZVS) region at f n > 1 . The nominal flat-top operating point ( f s = 100 kHz, f o = f L C = 98 kHz, i.e., f n 1.02 ) is placed slightly above unity to ensure operation in the inductive region required for primary-side ZVS.
The maximum value of the normalized gain within the designed operating range corresponds to the upper boundary of the output-current capability under the specified DC bus voltage, and therefore serves as the key design reference for determining the transformer turns ratio. Denoting the maximum normalized gain in the operating range by
G max = max N I ref R load V d c ,
the corresponding maximum achievable output current is
I ref , max = G max V d c N R load .

3.3. Parameter Calculation

Based on physical field constraints, the coil parameters are R load = 77.991 m Ω , L load = 1.12542 mH , and I ref = 100 A . The DC bus voltage is selected as V dc = 390 V , with the design targets of current ripple Δ i pp < 0.1 A and rise time below 2 ms .
Transformer turns ratio N: To guarantee a sufficient output-current margin under temperature rise, the transformer turns ratio is determined from the maximum normalized gain within the operating frequency range. Considering a 50 % current margin and a 30 % resistance margin, the design condition is
1.5 I ref G max V d c N · 1.3 R load ,
which gives the maximum allowable turns ratio
N max = G max V d c 1.5 I ref · 1.3 R load 4.08 .
Hence, N = 4 is selected, ensuring a maximum output current of 150 A even when the coil resistance rises to 1.3 R load 100 m Ω .
Switching frequency f s : From Equation (54) with D T 3 0 (worst case for ripple), the condition Δ i pp < 0.1 A requires
f s > I ref R load Δ i pp L load 69.55 kHz
Hence, f s = 100 kHz is selected.
Energy storage capacitor C c h and charging voltage V chset : The minimum average discharge voltage needed to ramp the coil from 0 to 100 A in 2 ms is estimated as V avg L load · I ref / t rise = 56.27 V . After balancing dynamic performance, volume, and cost constraints, C c h = 3600 µF is selected. Using the underdamped discharge analytical solution (Equation (14)) and back-solving for the required initial capacitor voltage at t rise = 2 ms , the nominal charging voltage is V chset 71.44 V . For the extreme operating condition ( I set = 150 A , R eq = 1.3 R load ), the extreme charging voltage is V chextreme = 109.35 V .
Resonant parameters: To prioritize wide-range current output capability, the inductance ratio k = L m / L r = 3 is selected. The upper bound on C r is derived by requiring that D T 3 in Equation (53) remains valid (the arcsin argument 1 ) under the worst-case resistance R load _ max = 1.3 R load :
C r 3 16 π 2 N 2 R load _ max f s 118.75 nF
To place the steady-state D T 3 in the sensitive linear region (0.1∼0.2), C r = 33 nF is chosen. Setting f r = f s gives L r = 1 / ( ( 2 π f s ) 2 C r ) 76.76 µH; to ensure the switching frequency is slightly above the series resonant frequency for ZVS, L r = 80 µH is adopted, and L m = k · L r = 240 µH.
The two resonant frequencies are
f L C = 1 2 π L r C r 98.0 kHz , f L L C = 1 2 π ( L r + L m ) C r 49.0 kHz .
During flat-top operation, f s > f L C is maintained throughout, ensuring that the circuit remains in the inductive (ZVS) region. A summary of all design parameters is given in Table 1.

3.4. Comparison with Alternative Topologies

The proposed AHB-Flyback topology is one of several candidate architectures capable of driving an inductive load such as the ECR adjustment coil. This subsection compares the proposed converter with two representative alternatives: the conventional hard-switched full-bridge (H-bridge) converter, which represents the current mainstream solution for this application, and the full-bridge LLC resonant converter, which represents a soft-switched resonant alternative. The comparison is summarized in Table 2.
Several aspects of Table 2 warrant further discussion in the context of the target application. Switch count and device utilization. Although the proposed topology requires secondary-side switches ( S 1 S 4 , S Charge , S Drain , S Discharge ) that are not present in a bare H-bridge or LLC converter, these devices serve the bipolar output and energy management functions that are intrinsic to the application. If an H-bridge or LLC architecture were deployed in the same role, equivalent functional blocks would still be required—a bipolar output stage for direction control and a storage element for the wide-range current rise. The comparison should therefore focus on the primary-side power stage, where the AHB-Flyback uses two switches against four for the alternatives.
Device voltage stress asymmetry. A key advantage of the proposed topology is the asymmetric voltage stress between the primary and secondary sides. The primary switches withstand the full DC bus voltage ( V d c = 390 V), necessitating high-voltage SiC MOSFETs. The secondary switches, by contrast, are exposed only to the storage capacitor voltage V chset 71 V at the rated operating point (or up to V chextreme 109 V in the extreme scenario). This permits the use of low-voltage, low- R D S ( o n ) devices on the secondary side, reducing conduction losses despite the larger number of secondary switches.
Decoupled energy management. Neither the H-bridge nor the LLC converter, in their conventional form, decouples the peak load power demand from the upstream supply network. In a direct-drive architecture, the full V d c I ref power flows through the supply during the current rise phase. In the proposed topology, the primary-side switches remain inactive during the 4 ms current rise, and energy is delivered from the pre-charged storage capacitor C c h . The primary AHB-Flyback circuit draws energy from the bus only during the slower-charging and flat-top compensation intervals, smoothing the power demand over time. This architectural property cannot be replicated by the alternatives without adding a storage element that would effectively turn them into variants of the proposed topology.
Switching loss estimation. Using the datasheet parameters of the selected devices (NTHL040N120SC1 primary SiC MOSFET, E on 320 µJ, E off 85 µJ at 400 V/40 A from the reference datasheet), a conventional hard-switched H-bridge at 100 kHz driving the rated current would incur approximately ( E on + E off ) · f s 40 W of switching loss per device, or roughly 160 W aggregate for the four-switch bridge at the rated operating point. In the proposed topology, ZVS operation reduces E on effectively to zero, and the two-switch primary contributes only ≈17 W of turn-off loss. This represents an order-of-magnitude reduction in switching-related thermal burden, and is the direct mechanism enabling 100 kHz operation within a practical thermal budget.
In summary, while full-bridge soft-switching alternatives such as LLC can match the ZVS capability of the proposed topology, the combination of reduced primary switch count, asymmetric voltage stress distribution, decoupled energy management, and dual-control-variable flexibility ( f s and D) makes the AHB-Flyback particularly well-suited to the requirements of ECR adjustment coil excitation.

4. Simulation and Experimental Validation

4.1. Simulation Validation

A PLECS simulation model (version 4.7.3, Plexim GmbH, Zurich, Switzerland) was established according to the calculated parameters, which are summarized in Table 1.
Figure 16 illustrates a complete working sequence, including charging, a 50 A positive flat-top, energy recovery, recharging, and a 100 A negative flat-top. This sequence verifies the feasibility of bipolar wide-range operation. Zoomed-in views across all four active phases confirm primary-side ZVS and secondary-side ZCS, consistent with the analytical predictions in Section 2.3.
To verify the accuracy of the time-domain analytical model, flat-top currents at different reference values were generated at a switching frequency of 111.11 kHz ( T s = 9 μ s ). The steady-state current waveforms at 30 A and 100 A are shown in Figure 17. According to Equation (53), the theoretical Mode 3 duration is
T 3 = D T 3 T s 0.1631 × 9 μ s 1.468 μ s .
The simulated Mode 3 durations are in close agreement with this theoretical value across the full 20–100 A range.
Table 3 compares the theoretical predictions and simulated measurements of the Mode 3 duration and resonant capacitor voltage amplitude U C r across the 20–100 A range. The relative errors in Mode 3 duration are all within ± 2 % , and the errors in U C r decrease from 5.75% at 20 A to below 0.1% at high currents, confirming the precision of the proposed time-domain model. The theoretical prediction that D T 3 is constant across the entire current range is clearly confirmed by the nearly invariant simulated Mode 3 duration.
The comparison is further visualized in Figure 18, which plots both the Mode 3 duration and U C r theoretical and simulated values against I ref .
Extreme-condition tests were also performed with R load = 101.4 m Ω , f s = 100 kHz , and D = 0.5 . The maximum achievable flat-top current was approximately 144.2 A, against the design target of 150 A (error of 3.8%), effectively meeting the design margin.

4.2. Experimental Validation

A scaled physical prototype was developed to verify the topology’s operational mechanism. Constrained by the current-probe measurement range, the bus voltage was scaled to V d c = 130 V to test flat-top waveforms at 10 A , 20 A , and 30 A . The experimental platform is shown in Figure 19, and the component list is given in Table 4.
Figure 20, Figure 21 and Figure 22 show the full flat-top charge–discharge waveforms at 10 A , 20 A , and 30 A . In all three cases, the current rises rapidly to I ref during the discharge phase, and then enters the flat-top maintenance stage where it fluctuates only slightly around the setpoint. No oscillation or instability is observed as the flat-top current is varied across this range, confirming the wide-range current regulation capability of the proposed topology.
The zoomed-in flat-top detail waveforms at 10 A , 20 A , and 30 A are shown in Figure 23. In all three cases, the primary switches achieve zero-voltage turn-on (the switch voltage drops to zero before the gate signal arrives) and the secondary rectifier achieves zero-current turn-off (the diode current decays naturally to zero at turn-off). These soft-switching characteristics are consistent across all three current levels, validating that the ZVS/ZCS conditions are inherently satisfied over the tested operating range.
The experimental outcomes consistently corroborate the theoretical modeling and simulation analyses, confirming that the AHB-Flyback topology achieves stable flat-top current output with inherent soft-switching over a wide current range.

Dynamic Response During Flat-Top Establishment

In a general-purpose DC-DC converter, dynamic response is conventionally evaluated by a load-step test in which the current reference is stepped from one value to another during steady-state operation. This test is not representative of the operating profile of the present converter. In the target application, i.e., excitation of the central adjustment coil of an ECR ion source, the mirror field configuration must remain stable throughout each excitation pulse, so the reference current I ref is held constant for the entire duration of a given pulse. Adjustment of the field strength is performed between pulses, with sufficient idle time allocated for the storage capacitor C c h to be recharged or partially discharged to the new setpoint. Runtime step changes in I ref within a single flat-top interval are therefore neither required nor physically meaningful for this application.
Instead, the dynamic performance figure of merit for this converter is the transition from the end of the current rise phase to the onset of a stable flat-top plateau. This transition, during which the closed-loop controller takes over from the capacitor-to-coil RLC discharge and establishes steady-state regulation around I ref , directly determines the usable flat-top duration and the initial flat-top stability. Figure 24 shows the measured current waveform during this transition at I ref = 30 A , with an enlarged vertical scale of 0.1 A/div to resolve the small-signal behavior around the setpoint. At approximately 24 ms, the current reaches the end of the rise phase with a peak value of about 30.3 A, corresponding to an initial overshoot of roughly 1% relative to I ref . This overshoot arises from the underdamped nature of the capacitor-to-coil RLC discharge at the moment when the load current first reaches the reference value. The closed-loop controller subsequently takes over, damping the residual oscillation and driving the load current toward the steady-state flat-top. As indicated by the annotated time interval, the current settles to within ± 0.05 A (approximately ± 1700 ppm) of the reference value within 1.397 ms after the end of the rise phase. Once past this settling interval, the current enters the stable flat-top regime where the 1000 ppm stability specification is maintained, as confirmed by the zoomed-in flat-top waveforms presented earlier in Figure 23.
This settling time is short relative to the full flat-top duration designed for the ECR adjustment coil application (on the order of tens of milliseconds), so the transient establishment phase does not materially reduce the usable flat-top window. Furthermore, the absence of sustained oscillation or long-duration drift after the settling interval confirms that the closed-loop controller successfully suppresses the underdamped discharge dynamics and delivers the steady-state flat-top stability required by the application.

4.3. Efficiency Analysis

To quantify the efficiency advantage of the proposed AHB-Flyback converter over a conventional hard-switched H-bridge solution, a comprehensive loss analysis is carried out following the methodology of [19,20]. This subsection presents the loss decomposition model, the full-power efficiency comparison between the two topologies obtained through PLECS simulation, and the experimental verification on the scaled prototype.

4.3.1. Loss Model and Simulation Methodology

The converter loss is decomposed into the following contributions, each evaluated from the corresponding device datasheet parameters and operating-point variables:
  • Primary-side SiC MOSFET turn-off loss P off , pri : calculated from the datasheet turn-off energy E off of NTHL040N120SC1 with linear voltage and current scaling. The turn-on loss is zero due to ZVS operation.
  • Primary conduction loss P cond , pri : Computed from the primary resonant current RMS value and the on-resistance R D S ( on ) at the operating junction temperature.
  • Secondary synchronous-rectification (SR) conduction loss P SR : With three parallel NCEP02T10 MOSFETs each carrying I ref / 3 , P SR = 3 · ( I ref / 3 ) 2 R D S ( on ) , SR . Body-diode conduction during dead time is separately accounted for.
  • Output H-bridge conduction loss P S , cond : P S , cond = 2 I ref 2 R D S ( on ) , S , corresponding to two IRF200P222 MOSFETs conducting the full output current at any instant.
  • Magnetic losses: transformer copper loss (primary and secondary windings) and core loss (via Steinmetz model), together with the resonant inductor L r copper and core losses.
  • Fixed losses: gate-drive power, control and auxiliary supply consumption, and PCB stray losses.
All device and magnetic loss parameters are imported into PLECS via the thermal description library. The converter efficiency is obtained by steady-state time-domain simulation with the input and output powers computed by averaging V dc ( t ) I dc ( t ) and V load ( t ) I load ( t ) over a switching cycle. The same procedure is applied to a hard-switched H-bridge benchmark driving the same coil load; for a fair comparison, the benchmark H-bridge uses four IRF200P222 MOSFETs (matching the voltage class of V dc ) with synchronous freewheeling, so that the body-diode conduction losses are replaced by channel conduction through R D S ( on ) .

4.3.2. Loss Breakdown at the Rated Operating Point

Figure 25 shows the PLECS-based loss breakdown of the proposed AHB-Flyback converter at the rated operating point I ref = 100 A, V dc = 390 V. The total loss is 112.21 W, yielding an efficiency of 87.42%.
The dominant loss contribution is the output H-bridge conduction loss (76.50 W, 68% of the total), which is an I ref 2 R D S ( on ) term inherent to any topology delivering 100 A to the magnet load through active switches. The secondary SR conduction loss (14.41 W) is the second-largest contribution, reduced by a factor of three compared with a single-path rectification scheme thanks to the SIPO configuration. Primary-side switching and conduction losses together amount to only 9.52 W, demonstrating the effectiveness of the ZVS operation—the turn-on loss component is entirely eliminated. Magnetic and fixed losses contribute a combined 8.48 W. This decomposition identifies the output-stage I 2 R loss as the ultimate bottleneck for further efficiency improvement, which is common to all low-voltage high-current isolated DC-DC topologies and is largely independent of the primary-stage topology choice.

4.3.3. Efficiency Comparison in Full-Power Conditions

Figure 26 presents the PLECS-based efficiency curves of the proposed AHB-Flyback converter and the hard-switched H-bridge benchmark over the I ref = 30 –100 A range at the rated bus voltage V dc = 390 V.
The proposed converter maintains an efficiency above 86% across the entire 30–100 A operating range, with a peak efficiency of 88.46% at I ref = 100 A. In contrast, the hard-switched H-bridge exhibits significantly lower efficiency, particularly at light load where switching losses dominate the relatively low output power: 67.13% at I ref = 30 A rising to 82.27% at I ref = 100 A. The efficiency advantage of the proposed topology is therefore most pronounced at partial load (+19.56 pp at 30 A) and remains substantial at full load (+6.19 pp at 100 A). This advantage originates directly from the ZVS elimination of primary turn-on loss, which in the hard-switched H-bridge grows linearly with switching frequency and becomes the dominant loss contribution at the 100 kHz operating point selected to satisfy the 1000 ppm flat-top ripple specification.

4.3.4. Experimental Verification in Scaled Conditions

Due to the experimental prototype being operated at a reduced bus voltage of 130 V (one-third of the full-scale design value) for current-probe measurement compatibility, the experimental efficiency characterization is performed in the 10–30 A current range. Input and output powers are measured from the averaged V I products using precision voltage and current probes. A corresponding PLECS simulation under identical scaled conditions is also carried out for direct comparison.
Figure 27 compares the measured and simulated efficiency of the proposed converter under the scaled experimental condition.
The measured efficiency ranges from 86.61% at 10 A to 89.59% at 30 A, closely tracking the PLECS simulation with a consistent deviation of approximately 1–2 percentage points. This level of agreement is characteristic of analytical/simulation efficiency models that do not include all parasitic effects (e.g., interconnect resistance, high-frequency skin-effect winding losses, and EMI filter losses), which is consistent with the observations in similar studies [19,20]. The systematic offset between simulation and measurement, together with the matching trend across the tested current range, confirms the validity of the loss model used for the full-power efficiency projection in Figure 26.
Owing to the limited availability of a full-power H-bridge prototype for direct experimental comparison, the efficiency advantage of the proposed topology over the hard-switched H-bridge is established exclusively through PLECS simulation in this work. Experimental characterization of a full-scale H-bridge implementation is identified as future work.

5. Conclusions

This paper systematically analyzed the flat-top current generation mechanism of an AHB-Flyback-based power topology designed for ECR magnetic mirror field adjustment coils, with emphasis on the wide-range current regulation capability and the underlying analytical model.
By deriving an explicit time-domain model for the flat-top maintenance stage, the Mode 3 duty cycle D T 3 is shown to depend only on the switching frequency and circuit parameters, and to be independent of the load current setpoint. This property directly explains why the AHB-Flyback topology can maintain stable, low-ripple flat-top current output over a 20–100 A range without re-tuning, which is a fundamental advantage over hard-switched H-bridge solutions. The inherent soft switching of the primary ZVS and secondary ZCS further allows operation at higher switching frequencies, reducing current ripple while keeping switching losses low.
Both simulation results (matching theoretical Mode 3 durations to within ± 2 % across the full current range) and scaled experimental results (stable flat-top waveforms at 10 A, 20 A, and 30 A with confirmed ZVS/ZCS) validate the analytical model and demonstrate the practical feasibility of the proposed topology for advanced ion source power supply applications.

Author Contributions

Conceptualization, D.Z. and H.D.; methodology, D.Z. and Y.L.; software, D.Z.; validation, D.Z., S.M. and C.Z.; formal analysis, D.Z.; investigation, D.Z. and W.C.; resources, H.D.; data curation, D.Z.; writing—original draft preparation, D.Z.; writing—review and editing, D.Z. and H.D.; visualization, D.Z.; supervision, D.Z. and H.D.; project administration, H.D.; funding acquisition, H.D. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the National Key Research and Development Program of China under Grant 2023YFA1607603.

Data Availability Statement

The data presented in this study are contained within the article.

Conflicts of Interest

The authors declare no conflicts of interest.

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  20. Qi, Q.; Ghaderi, D.; Guerrero, J.M. Sliding mode controller-based switched-capacitor-based high DC gain and low voltage stress DC-DC boost converter for photovoltaic applications. Int. J. Electr. Power Energy Syst. 2021, 125, 106496. [Google Scholar] [CrossRef]
Figure 1. Topology of the conventional H-bridge converter for ECR magnet loads [4].
Figure 1. Topology of the conventional H-bridge converter for ECR magnet loads [4].
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Figure 2. Schematic diagram of the AHB-Flyback topology. The asterisk (*) indicates the dot-polarity terminal of transformer.
Figure 2. Schematic diagram of the AHB-Flyback topology. The asterisk (*) indicates the dot-polarity terminal of transformer.
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Figure 3. Fundamental equivalent circuit diagram of the AHB-Flyback topology.
Figure 3. Fundamental equivalent circuit diagram of the AHB-Flyback topology.
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Figure 4. Gain curve of the normalized fundamental voltage transfer function.
Figure 4. Gain curve of the normalized fundamental voltage transfer function.
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Figure 5. Equivalent circuit diagram of the capacitor-charging stage. The asterisk (*) indicates the dot-polarity terminal of transformer.
Figure 5. Equivalent circuit diagram of the capacitor-charging stage. The asterisk (*) indicates the dot-polarity terminal of transformer.
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Figure 6. Equivalent circuits of the four resonant modes.
Figure 6. Equivalent circuits of the four resonant modes.
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Figure 7. Capacitor-to-coil discharging stage. The asterisk (*) indicates the dot-polarity terminal of transformer.
Figure 7. Capacitor-to-coil discharging stage. The asterisk (*) indicates the dot-polarity terminal of transformer.
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Figure 8. Circuit configuration during the flat-top maintenance stage. The asterisk (*) indicates the dot-polarity terminal of transformer.
Figure 8. Circuit configuration during the flat-top maintenance stage. The asterisk (*) indicates the dot-polarity terminal of transformer.
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Figure 9. Waveform schematic of the flat-top maintenance stage.
Figure 9. Waveform schematic of the flat-top maintenance stage.
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Figure 10. Equivalent circuit of Mode 1 during the flat-top maintenance stage.
Figure 10. Equivalent circuit of Mode 1 during the flat-top maintenance stage.
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Figure 11. Equivalent circuit of Mode 2 during the flat-top maintenance stage.
Figure 11. Equivalent circuit of Mode 2 during the flat-top maintenance stage.
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Figure 12. Equivalent circuit of Mode 3 during the flat-top maintenance stage.
Figure 12. Equivalent circuit of Mode 3 during the flat-top maintenance stage.
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Figure 13. Equivalent circuit of Mode 5 during the flat-top maintenance stage.
Figure 13. Equivalent circuit of Mode 5 during the flat-top maintenance stage.
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Figure 14. Flat-top current ripple diagram.
Figure 14. Flat-top current ripple diagram.
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Figure 15. Normalized gain N I ref R load / V d c as a function of f n = f s / f o . The nominal flat-top operating point ( f n slightly above unity, corresponding to the inductive ZVS region) is marked. The dashed reference line indicates the peak gain, which defines the maximum-stable-output-current boundary.
Figure 15. Normalized gain N I ref R load / V d c as a function of f n = f s / f o . The nominal flat-top operating point ( f n slightly above unity, corresponding to the inductive ZVS region) is marked. The dashed reference line indicates the peak gain, which defines the maximum-stable-output-current boundary.
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Figure 16. Simulation waveforms of the AHB-Flyback flat-top topology under dynamic sequencing.
Figure 16. Simulation waveforms of the AHB-Flyback flat-top topology under dynamic sequencing.
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Figure 17. Flat-top current stability waveforms at different reference currents.
Figure 17. Flat-top current stability waveforms at different reference currents.
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Figure 18. Comparison of theoretical and simulated values at different flat-top currents.
Figure 18. Comparison of theoretical and simulated values at different flat-top currents.
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Figure 19. Experimental platform photograph.
Figure 19. Experimental platform photograph.
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Figure 20. Experimental flat-top waveform at V d c = 130 V , I ref = 10 A .
Figure 20. Experimental flat-top waveform at V d c = 130 V , I ref = 10 A .
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Figure 21. Experimental flat-top waveform at V d c = 130 V , I ref = 20 A .
Figure 21. Experimental flat-top waveform at V d c = 130 V , I ref = 20 A .
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Figure 22. Experimental flat-top waveform at V d c = 130 V , I ref = 30 A .
Figure 22. Experimental flat-top waveform at V d c = 130 V , I ref = 30 A .
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Figure 23. Experimental flat-top waveform details at V d c = 130 V .
Figure 23. Experimental flat-top waveform details at V d c = 130 V .
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Figure 24. Measured current waveform during the transition from the end of the rise phase to the stable flat-top plateau at V d c = 130 V , I ref = 30 A . The vertical scale is expanded to 0.1 A / div to resolve the small-signal settling behavior.
Figure 24. Measured current waveform during the transition from the end of the rise phase to the stable flat-top plateau at V d c = 130 V , I ref = 30 A . The vertical scale is expanded to 0.1 A / div to resolve the small-signal settling behavior.
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Figure 25. Loss breakdown of the proposed AHB-Flyback converter at I ref = 100 A, V dc = 390 V, f s = 100 kHz.
Figure 25. Loss breakdown of the proposed AHB-Flyback converter at I ref = 100 A, V dc = 390 V, f s = 100 kHz.
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Figure 26. PLECS-based efficiency comparison between the proposed AHB-Flyback converter and the hard-switched H-bridge benchmark at V dc = 390 V, f s = 100 kHz.
Figure 26. PLECS-based efficiency comparison between the proposed AHB-Flyback converter and the hard-switched H-bridge benchmark at V dc = 390 V, f s = 100 kHz.
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Figure 27. Efficiency comparison between PLECS simulation and experimental measurements in the scaled condition ( V dc = 130 V, f s = 100 kHz).
Figure 27. Efficiency comparison between PLECS simulation and experimental measurements in the scaled condition ( V dc = 130 V, f s = 100 kHz).
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Table 1. Main simulation circuit parameters.
Table 1. Main simulation circuit parameters.
CategoryParameterSymbolValue
DC sourceDC bus voltage V dc 390 V
Resonant tankResonant inductor L r 80 µH
Resonant capacitor C r 33 nF
Magnetizing inductance L m 240 µH
Turns ratioN4
Storage sideStorage capacitance C ch 3600 µF
Nominal charging voltage V chset 71.44 V
Extreme charging voltage V chextreme 109.35 V
Load sideLoad inductance L load 1.12542 mH
Nominal load resistance R load 77.991 m Ω
Extreme load resistance (1.3×) R load _ max 101.4 m Ω
Operating pointFlat-top min. switching freq. f s 100 kHz
Charging min. switching freq. f s , charge 62.5 kHz
Charging max. duty cycle D charge 0.5
Table 2. Comparison of candidate topologies for ECR adjustment coil driving.
Table 2. Comparison of candidate topologies for ECR adjustment coil driving.
AttributeH-BridgeFB LLCProposed AHB-Flyback
Primary active switches442
Secondary rectifier devices– (non-isolated)4 diodes1 diode
Primary switch voltage stress V d c V d c V d c
Primary switch peak current I ref I ref / N 1.5 I ref / ( 2 N )
Soft switching (primary)HardZVSZVS
Soft switching (secondary)ZCSZCS
Turn-on loss at rated currentProportional to V d c I ref f s ≈0≈0
Control degrees of freedomPWM (D)PFM ( f s )PFM + PWM ( f s , D)
Decoupled energy managementNoNoYes
Primary active during rise phaseYes (peak stress)Yes (peak stress)No (storage capacitor)
Bipolar current outputNativeRequires extensionVia secondary H-bridge
Table 3. Comparison of simulated and theoretical values under different flat-top currents.
Table 3. Comparison of simulated and theoretical values under different flat-top currents.
I ref (A)Mode 3 Time (μs) U Cr (V)
SimTheoError (%)SimTheoError (%)
201.4731.4680.34126.9120.05.75
301.4731.4680.34188.7180.14.78
401.4741.4680.41249.6240.13.96
501.4721.4680.27309.3300.13.07
601.4731.4680.34367.6360.12.08
701.4751.4680.48423.8420.20.86
801.4731.4680.34480.0480.2−0.04
901.4661.468−0.14537.6540.2−0.48
1001.4401.468−1.91599.8600.2−0.07
Table 4. AHB-Flyback experimental component and instrument list.
Table 4. AHB-Flyback experimental component and instrument list.
DeviceModel/SpecParameters
DC power supplyHYJG-3000E400C0–400 V/DC, 0–7.5 A, 0–10 kW
Resonant inductor L r Custom82.89 µH
Resonant capacitor C r Film capacitor33 nF
HF transformerCustom ×3Avg. L m = 80 µH, turns ratio N = 4 / 3
Storage capacitor C c h Electrolytic bank3600 µF, 400 V
Magnet loadCustom coil1.21 mH, 103.91 mΩ
Primary SiC MOSFETNTHL040N120SC11200 V, 60 A
Secondary switch MOSFETIRF200P222200 V, 182 A
Secondary rectifier MOSFET (SR)NCEP02T10200 V, 100 A
Current sensorACS37003KMCATR-180B5±180 A/DC, 400 kHz
Current probeCYBERTEK HCP8030±30 A/DC, 50 MHz
ControllerTI TMS320F28379D200 MHz CPU, 16-bit ADC
OscilloscopeHIOKI MR60001 MHz
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MDPI and ACS Style

Zhang, D.; Ding, H.; Liu, Y.; Mao, S.; Zhao, C.; Chen, W. A Wide-Range Soft-Switching AHB-Flyback Converter for Flat-Top Pulsed Magnetic Field Power Supplies. Electronics 2026, 15, 1997. https://doi.org/10.3390/electronics15101997

AMA Style

Zhang D, Ding H, Liu Y, Mao S, Zhao C, Chen W. A Wide-Range Soft-Switching AHB-Flyback Converter for Flat-Top Pulsed Magnetic Field Power Supplies. Electronics. 2026; 15(10):1997. https://doi.org/10.3390/electronics15101997

Chicago/Turabian Style

Zhang, Dandi, Hongfa Ding, Yingzhe Liu, Shuning Mao, Chengyue Zhao, and Wenhao Chen. 2026. "A Wide-Range Soft-Switching AHB-Flyback Converter for Flat-Top Pulsed Magnetic Field Power Supplies" Electronics 15, no. 10: 1997. https://doi.org/10.3390/electronics15101997

APA Style

Zhang, D., Ding, H., Liu, Y., Mao, S., Zhao, C., & Chen, W. (2026). A Wide-Range Soft-Switching AHB-Flyback Converter for Flat-Top Pulsed Magnetic Field Power Supplies. Electronics, 15(10), 1997. https://doi.org/10.3390/electronics15101997

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