Lightweight Hardware Implementation of a State of Charge Estimation Algorithm Using a Piecewise OCV–SOC Model

Abstract

State of charge (SOC) estimation is a key function in battery management systems (BMSs) because it directly affects safe operation and available energy prediction. In embedded BMS platforms, information from multiple cells must be processed within tight computation and memory budgets. The estimator therefore needs to balance accuracy and implementation cost. This paper presents a lightweight SOC estimation method based on the relationship between open circuit voltage and state of charge (OCV–SOC) in lithium-ion batteries, together with a standalone gauge IP based on finite-state machine (FSM) control. The reference OCV–SOC curve of a commercial 3.7 V lithium-ion cell is approximated by a two-region quadratic model. The IP estimates OCV from the measured terminal voltage with equivalent series resistance (ESR) correction and updates SOC iteratively. To obtain predictable runtime behavior and to suppress oscillatory behavior near convergence, the hardware combines a 1-LSB termination rule with a guard based on a maximum iteration count of $N_{max}=10$. Real-time validation on an FPGA-based battery measurement testbed achieves an overall normalized mean absolute error (NMAE) of 1.6% over charge and discharge data. When synthesized for an Artix-7 XC7A100T, the proposed gauge IP used only 504 LUTs (0.79%) and 580 FFs (0.46%). A TSMC 28 nm MPW implementation further demonstrates feasibility for integration at chip level.

1. Introduction

Lithium-ion batteries are widely used in electric vehicles (EVs), energy storage systems (ESSs), and portable electronics because of their high energy density and long cycle life. As their application range expands, battery management systems (BMSs) have become essential for accurately monitoring and controlling battery states [1,2,3,4,5,6]. A BMS periodically measures key variables such as voltage, current, and temperature and uses them to provide protection and operational control, thereby ensuring system safety and reliability [7,8,9]. Among BMS functions, state of charge (SOC) estimation is particularly important because it directly determines awareness of remaining energy, available energy prediction, power limitation, and protection thresholds. When SOC estimation errors accumulate, uncertainty in available energy prediction increases and protection control can become overly conservative, degrading both system efficiency and user experience [4,5,10,11]. In practice, EV and small scale ESS BMSs are commonly implemented on low power microcontrollers or SoC platforms, where information from multiple cells must be processed periodically under limited computational and memory resources. Accordingly, SOC estimation is an industrially important function, and embedded implementations must balance estimation performance against resource and power budgets [12,13,14].

A wide range of SOC estimation methods has been studied, including coulomb counting, observers and filters based on models, voltage-based estimation, and data-driven approaches. Each method offers different tradeoffs in terms of implementation simplicity, estimation performance, and dependence on models or data, and embedded BMS applications must consider computational and memory costs in addition to accuracy [12,13]. Recent studies have also reported strong performance using deep learning-based SOC estimation methods, including deep learning frameworks and Transformer–LSTM structures [15,16]. In addition, graph-based transfer learning and domain adaptation methods have achieved excellent results in intelligent fault diagnosis under domain shifts, as demonstrated by recent studies on knowledge correlation graph-guided multi-source interaction and spatial-channel collaborative multi-scale graph interaction [17,18]. These studies reflect the recent progress of data-driven methods that learn transferable representations from complex operating data. Electrochemical impedance spectroscopy (EIS)-based estimation has also been investigated for battery SOC estimation [19,20].

However, such methods may require additional training data, feature extraction, graph or domain adaptation processing, or dedicated excitation and measurement procedures. Their deployment in embedded BMS platforms therefore requires careful consideration of computational cost, memory usage, and implementation complexity. From a hardware design perspective, implementations should explicitly address not only resource usage but also bounded worst case latency and robust termination behavior. Many existing studies on FPGA implementation focus primarily on demonstrating functional feasibility or system level validation, and lightweight hardware for SOC estimation that simultaneously considers real-time operating constraints and implementation complexity remains needed.

This paper presents a lightweight hardware approach to SOC estimation for the development of a gauge IP in embedded BMS applications. The proposed method models the reference OCV–SOC curve of a lithium-ion battery with a piecewise polynomial that has two regions and estimates OCV from the measured terminal voltage together with ESR correction, after which SOC is updated iteratively. The estimator is implemented as a standalone gauge IP driven by finite state machines (FSMs), allowing us to address both hardware feasibility under constrained resources and robust real-time operation. The design is validated on a real-time FPGA battery measurement testbed, where SOC estimation accuracy and resource usage are evaluated. An MPW implementation is also presented to demonstrate ASIC feasibility.

The main contributions of this work are as follows:

• We propose an SOC estimation structure that combines a two-region piecewise OCV–SOC polynomial with an ESR lookup table (LUT). This structure reduces the memory demand of dense LUT-based mapping and provides a compact arithmetic structure suitable for fixed-point hardware implementation.
• We present a standalone gauge IP based on FSM control, a 1-LSB termination rule, a guard based on $N_{max}$, and an operator-reuse datapath. The proposed IP performs iterative SOC estimation using shared arithmetic resources while limiting excessive iteration and limit cycle behavior.
• Real-time validation on an FPGA battery measurement testbed demonstrates an overall NMAE of approximately 1.6% over charge and discharge data, with resource usage of 504 LUTs and 580 FFs, and a TSMC 28 nm ASIC implementation further confirms hardware feasibility.

The remainder of this paper is organized as follows. Section 2 reviews related studies. Section 3 describes the proposed estimation method based on the OCV–SOC relationship. Section 4 presents the hardware design and implementation of the gauge IP. Section 5 reports the experimental results, including FPGA real-time validation and MPW results. Section 6 discusses the significance and limitations of the work and outlines future directions, and Section 7 concludes the paper.

2. Related Work

2.1. SOC Estimation Methods

Because SOC is a state variable that cannot be measured directly, indirect estimation based on available sensor signals is commonly employed, and a variety of estimation techniques have been investigated [10]. Coulomb counting, which integrates battery current over time, is simple to implement and computationally inexpensive; however, sensor offset, gain error, and sampling error can accumulate over time and gradually increase the long-term SOC estimation error [21,22]. To mitigate this limitation, observer and filter approaches built on equivalent circuit models (ECMs) have been widely studied. Among them, the extended Kalman filter (EKF) is frequently used to improve estimation performance by incorporating the dynamic behavior of voltage and current [22,23,24,25]. Nevertheless, such methods typically require repeated state and parameter updates, linearization, and matrix operations, which increase computational cost and often require parameter identification and calibration procedures [12]. Data-driven and learning-based methods have also reported strong performance under diverse conditions, but their model size, inference cost, data dependence, and verification burden require additional consideration before deployment in embedded BMS platforms.

In voltage-based approaches, the relationship between open circuit voltage and SOC serves as a key source of information for SOC estimation, and the OCV–SOC curve is usually approximated and stored as either a polynomial or a lookup table (LUT) [26,27]. OCV–SOC models are attractive because of their relatively simple structure and good reproducibility, but the required storage and computational cost depend strongly on the fitting strategy and storage format [21]. Their applicability also depends on how variations in the OCV–SOC characteristic under different operating conditions are handled, making model selection important for practical BMS design. Methods based on the OCV–SOC relationship have been used alone or combined with coulomb counting and filters based on models in hybrid forms, and when iterative update structures are employed, termination design for real-time operation becomes an important part of the estimator [28,29,30,31,32,33].

2.2. Hardware Implementations for SOC Estimation

The practical implementation of SOC estimation algorithms depends strongly on the target platform. Embedded BMSs are commonly built on low power MCUs or SoCs, where battery information such as voltage and current is sampled and processed periodically under limited computational capability, memory capacity, and power budgets. Consequently, algorithmic complexity and memory demand are major constraints that determine whether a method can be deployed in embedded environments. FPGA implementations, by contrast, can exploit parallelism and deterministic execution and have therefore been used to realize filter-based estimators such as EKF, as well as voltage-based estimators in hardware [34,35,36,37]. However, many existing hardware studies emphasize proof of concept implementation or system-level validation rather than jointly designing and quantifying resource efficiency and termination behavior for lightweight hardware. Reports that extend beyond FPGA verification to chip fabrication and measurement are also still limited. Against this background, hardware for embedded BMS applications should not only simplify the SOC estimation model but also clarify how the selected model is translated into a resource-efficient implementation. In OCV–SOC-based estimation, dense LUT-based mapping can increase memory demand, whereas piecewise approximation can still require non-negligible arithmetic resources depending on the implementation. Therefore, a lightweight gauge architecture should jointly consider model storage, arithmetic structure, termination behavior, and latency bounds under real-time operating constraints.

3. OCV–SOC-Based Estimation Method

3.1. Overview of the Proposed Method

The goal of this study is real-time SOC estimation for lithium-ion batteries in embedded BMS environments. To this end, we propose a lightweight SOC estimation algorithm and a hardware structure suitable for implementation. The algorithm is based on the OCV–SOC characteristic of a lithium-ion battery, but to reduce dependence on large LUTs and higher order models, the OCV–SOC curve is partitioned into two voltage regions and each region is approximated by a quadratic polynomial. Measured terminal voltage V and current I are used as inputs. During the iterative update, the ESR corresponding to the current SOC estimate is obtained from an LUT, an OCV input is constructed, and SOC is then updated. The overall computation follows an iterative update structure: OCV is updated from the current SOC estimate, the resulting OCV is applied to the piecewise polynomial model, and the next SOC estimate is computed. For real-time operation, termination is guaranteed by a 1-LSB convergence criterion together with a maximum iteration limit. The main symbols and parameters used in this paper are summarized in

Table 1. Key symbols and parameters used in this work.

Symbol	Definition	Value
k	Sampling index	–
i	Iteration index within a sample	$i=0,1,\dots$
$V_k,I_k$	Measured terminal voltage and current at sample k	–
${\mathrm{OCV}}_i$	Estimated OCV at iteration i	–
${\widehat{S}}_i$	Estimated SOC at iteration i	–
${\widehat{S}}_{i+1}$	Updated SOC at iteration $i+1$	–
${\widehat{S}}_k$	Final SOC at sample k	–
$N_{max}$	Maximum number of iterations	10

. SOC is denoted by S, and the estimate at iteration i is written as ${\widehat{S}}_i$.

Figure 1 summarizes the overall processing pipeline of the proposed method. At each sampling instant, the terminal voltage $V_k$ and current $I_k$ are acquired. The ESR associated with the current SOC estimate ${\widehat{S}}_i$ is then read from the LUT, and this value is used together with the measured voltage and current to construct the OCV input to the model. The resulting OCV estimate is applied to the piecewise quadratic OCV–SOC model to compute the updated SOC estimate ${\widehat{S}}_{i+1}$. This sequence is repeated iteratively until the termination rule described in Section 3.3 is satisfied, after which the final SOC is reported as ${\widehat{S}}_k$.

3.2. Piecewise OCV–SOC Modeling

This section describes how the OCV–SOC relationship, which forms the core of the proposed method, is modeled in a form suitable for hardware implementation. The OCV–SOC curve of a lithium-ion battery is nonlinear, and its voltage slope varies with SOC. As a result, approximating the entire range with a single low-order polynomial can increase fitting error in certain regions, whereas increasing the polynomial order raises implementation complexity. To reduce dependence on large LUTs or higher order polynomial models, we partition the OCV–SOC curve into two voltage regions and approximate each region with a quadratic polynomial, thereby obtaining a lightweight model that computes SOC from OCV. SOC is normalized to the range 0–1 to match the fixed-point representation and scaling used in hardware. In Figure 1, this model corresponds to the Piecewise OCV–SOC model block and provides the updated SOC value for a given OCV during each iteration.

3.2.1. Reference OCV–SOC Characterization

The OCV–SOC reference data were derived from a characterized single lithium-ion cell dataset and used as the basis for both the piecewise polynomial model and the ESR LUT design. The reference SOC used for error evaluation was obtained by OCV–SOC mapping from the same dataset. The battery model stores Voc and ESR over SOC states and provides 101 SOC points with 1 mV Voc resolution and 1 mΩ ESR resolution. The uncertainty of the reference dataset is affected by both the battery-model resolution and the voltage/current measurement accuracy used during dataset generation. The reference OCV–SOC curve exhibits a steep slope change in the low SOC region and becomes gradually flatter as SOC increases. Because of this region’s specific nonlinearity, applying a single low order approximation across the entire range can increase fitting error in the low voltage region. Figure 2a and b compare the approximation error of the single full-range approximation and the two-region piecewise approximation in the low voltage and high voltage regions, respectively. In this comparison, the NMAE values are normalized by the full SOC range so that both approximation structures can be interpreted on a common basis. As shown in Figure 2, the two-region piecewise approximation follows the region’s specific nonlinearity more effectively than the single approximation, particularly in the low-voltage region. Therefore, this study adopts a two-region approximation to reduce region-specific fitting error while keeping model complexity low.

3.2.2. Two-Region Piecewise Polynomial Approximation

The polynomial order and partition boundary of the two-region model were determined through offline analysis using the reference OCV–SOC data. Given the nonlinearity discussed in Section 3.2.1, the polynomial order was selected by considering both local approximation capability and implementation complexity. A quadratic polynomial is the polynomial of the lowest order that can explicitly represent local curvature within each region, whereas models of higher order require additional coefficients and arithmetic operations. Therefore, the quadratic form was considered a suitable model of minimum order for the proposed piecewise approximation intended for hardware implementation.

Candidate models of low polynomial order in the two-region structure were then compared in terms of approximation accuracy. Figure 3a shows the overall NMAE as a function of polynomial order in the two-region structure. Although the overall error decreases as the polynomial order increases, the additional reduction becomes limited once the dominant local curvature is represented by the quadratic term. This result supports the adoption of the two-region quadratic model as a practical trade-off between approximation capability and implementation complexity.

Figure 3b compares the reference OCV–SOC data with the selected two-region quadratic approximation. The partition boundary was chosen by comparing the approximation accuracy of each region for the selected model structure, and the final model was configured so that region selection can be performed using only a single comparison with the OCV threshold voltage $V_{\mathrm{th}}$. In each region, the SOC output for OCV input x is approximated by a quadratic polynomial, and the SOC update at iteration i is defined as follows:

$${\widehat{S}}_{i+1}=a_r{x}^2+b_{r}x+c_r,x={\mathrm{OCV}}_i,r\in \{1,2\}.$$

(1)

Here, $r\in \{1,2\}$ denotes the region selected by the OCV threshold $V_{\mathrm{th}}$, with $r=1$ for $x\le V_{\mathrm{th}}$ and $r=2$ for $x>V_{\mathrm{th}}$. The coefficients $a_r$, $b_r$, and $c_r$ for each region are listed in

Table 2. Two-region quadratic OCV–SOC coefficients.

Range	${\mathit{a}}_{\mathit{r}}$	${\mathit{b}}_{\mathit{r}}$	${\mathit{c}}_{\mathit{r}}$
$x\le V_{\mathrm{th}}$	$0.09394$	$-0.4874$	$0.6322$
$x>V_{\mathrm{th}}$	$-0.3601$	$4.1235$	$-9.8592$

.

Both regions share the same arithmetic structure, while the coefficients are selected according to the active region. This two-region quadratic approximation is well suited to fixed-point iterative updating because it uses only a small number of coefficients and a simple arithmetic structure, reducing both storage cost and computational complexity compared with mapping based on a large LUT. Applying the same polynomial order in both regions also provides a uniform implementation flow, so model switching requires only coefficient selection after region comparison. The iterative SOC estimation flow based on the above piecewise quadratic OCV–SOC model is summarized in Figure 4.

3.3. The 1-LSB-Based Termination Rule for Predictable Runtime Behavior

This section presents a 1-LSB termination rule together with a guard based on the maximum number of iterations so that the fixed-point iterative SOC update shows predictable runtime behavior in real-time hardware. At sample k, the proposed method updates SOC iteratively, and the estimate at iteration i is denoted by ${\widehat{S}}_i$. Following the processing flow in Section 3.1, each iteration constructs the required input from the current estimate and computes the next SOC value.

In fixed-point implementations, even after the iterative update enters the vicinity of convergence, scaling and quantization errors can prevent the estimate from settling exactly at a single fixed point. Instead, the estimate may fluctuate slightly between adjacent representable values. In such cases, the actual variation is very small, but an overly strict termination condition can cause unnecessary additional iterations even after sufficient convergence has been reached. Therefore, this work determines termination based on the difference $\Delta S_i$ between two successive estimates. The tolerance ${\epsilon }_S$ is set to 1 LSB, which corresponds to the minimum distinguishable change in the fixed-point SOC representation. This 1-LSB criterion reduces unnecessary iteration and enables stable final SOC decisions even when the estimate jitters within approximately $\pm 1\mathrm{LSB}$ because of input noise or quantization error.

However, the 1-LSB criterion alone does not completely prevent prolonged termination in regions where the estimate alternates between neighboring quantization levels. In that case, the updated magnitude can remain near the threshold for repeated iterations. To bound the iteration count, we therefore introduce a maximum number of iterations, $N_{max}$. This guard provides predictable worst case execution time in real-time hardware, and the final output ${\widehat{S}}_k$ is taken as the last updated value at the termination point. The resulting definition and termination rule are summarized in Algorithm 1.

Algorithm 1 Termination rule for iterative SOC update

Require: Measured inputs at sample k ($V_k,I_k$), initial estimate ${\widehat{S}}_0$, tolerance ${\epsilon }_S$, maximum    iterations $N_{max}$ Ensure: Final SOC ${\widehat{S}}_k$   1:  Initialize $i\leftarrow 0$   2:  while $i<N_{max}$do   3:  Construct required inputs based on ${\widehat{S}}_i$   4:  ${\widehat{S}}_{i+1}\leftarrow f\left({\widehat{S}}_i\right)$   5:  $\Delta S_i\leftarrow \left|{\widehat{S}}_{i+1}-{\widehat{S}}_i\right|$   6:  if $\Delta S_i\le {\epsilon }_S$ then   7:     break   8:  end if   9:  ${\widehat{S}}_i\leftarrow {\widehat{S}}_{i+1}$   10:   $i\leftarrow i+1$   11:  end while   12:  ${\widehat{S}}_k\leftarrow {\widehat{S}}_{i+1}$

4. Hardware Design and Implementation

This section describes the hardware structure used to implement the iterative update method based on the OCV–SOC relationship that was presented in Section 3 as a standalone gauge IP that does not rely on a microprocessor. In this paper, the gauge IP denotes a hardware block that can perform SOC estimation independently, and its main computational engine is referred to as the Gauge Core. The proposed implementation adopts fixed-point arithmetic and a minimal LUT structure to accommodate limited computational and memory resources. To ensure predictable runtime in real-time operation, it employs a termination guard that combines a 1-LSB termination rule with a limit on the maximum number of iterations. The gauge IP was described in synthesizable RTL and validated on an FPGA hardware platform. ASIC feasibility is further demonstrated in Section 5 through MPW results.

4.1. System Hardware Design

This subsection summarizes the system-level hardware organization and data flow used to apply the gauge IP to real-time SOC estimation. The proposed system separates measurement and estimation functions and repeats the same measurement, estimation and output pipeline at every sampling period. Sensing of battery terminal voltage and current and initial data acquisition are handled by an external measurement AFE board. At each sampling instant, the gauge IP receives the measured data, starts computation, calculates SOC through the Gauge Core, and provides the result to an external observation path. Accordingly, the system interface is minimized to the reception of measured data and the observation of the resulting SOC, whereas the estimation and termination logic reside entirely inside the gauge IP.

At the system level, the hardware structure and data flow are as follows. As shown in Figure 5, the gauge IP consists of four main modules: (i) an I2C module, (ii) a Top Controller, (iii) the Gauge Core, and (iv) a UART module. The I2C module acts as a bidirectional serial interface that receives raw voltage and current data for each sample from the external AFE board. The Top Controller is an FSM that drives the system sequentially, initiating input acquisition and estimation at each sampling instant and generating control signals for the modules in the required order. The Gauge Core stores the received measurement data in an input buffer, applies fixed-point scaling to convert them into the internal numeric format, computes OCV, selects the active region, evaluates the polynomial, and updates SOC iteratively. Iteration termination is decided by the termination guard inside the Gauge Core, which implements the 1-LSB rule, and the finalized SOC is sent to a PC through the UART module for performance evaluation and validation.

Therefore, in the proposed system, both SOC estimation and termination are executed inside the Gauge Core without processor intervention, while the external components support operation verification by supplying measurement data and observing results.

4.2. Gauge Core Design

The Gauge Core is the computational block that receives the terminal voltage $V_k$ and current $I_k$ acquired at sampling instant k and determines the final SOC ${\widehat{S}}_k$ through iterative updating based on the OCV–SOC relationship. The Gauge Core constructs the OCV input using the ESR value associated with the current SOC estimate, updates SOC by applying the OCV to the piecewise polynomial model, and determines when to terminate iteration through the termination guard. In summary, the structure repeatedly computes the next SOC value from the current estimate and then updates the stored estimate.

4.2.1. Fixed-Point Representation

To perform real-time SOC estimation under tight hardware resource constraints, the Gauge Core processes all internal computations using fixed-point arithmetic. The raw voltage and current values received from the external AFE board are buffered and then converted, through scaling, into the internal numeric format used for computation. This scaling stage aligns the units and ranges of the raw measurements with the internal arithmetic range, secures the numerical resolution needed for polynomial evaluation and iterative updating, and also acts as preprocessing that suppresses overflow and excessive bit width growth during arithmetic operations.

A single fixed-point format is used throughout the internal calculations of the Gauge Core. As illustrated in Figure 6, all internal operations use a 16-bit signed fixed-point format, and the same format is applied to OCV calculation, region selection, polynomial evaluation, iterative updating, and termination checking. The incoming voltage and current values are also converted into this format during scaling. This use of a single format reduces implementation complexity by preserving format consistency across the full computation path while still providing sufficient resolution.

The fixed-point format was selected by considering both the range and resolution of key variables, including input voltage and current, the estimated OCV, SOC state values, polynomial coefficients, and intermediate accumulation terms. In particular, the minimum SOC resolution is defined as 1 LSB, and the internal format was chosen so that SOC variables can represent this resolution without loss. The format consistency also helps prevent accumulation error from unduly affecting the convergence decision during iterative updates.

4.2.2. Gauge Core Architecture

The Gauge Core receives voltage and current samples from the AFE, performs SOC estimation based on iterative updating, and outputs the final SOC and a valid completion signal for each sample. Figure 7 shows the internal organization used to support this functionality. The architecture consists of an input and state register block, an ESR lookup block, an SOC Calculator that performs the iterative computation, a Gauge Core Controller that manages the computation sequence, and a Termination Guard that decides when the iteration should stop.

Once a valid sample is received, the input and state register block maintains the voltage, current, and SOC estimate for the current iteration. The ESR LUT returns the ESR corresponding to the current SOC estimate and passes it to the SOC Calculator. By storing ESR values and polynomial coefficients instead of the full OCV–SOC relation in a dense table, the proposed structure reduces memory demand.

The Gauge Core Controller manages the full processing order as an FSM, including the start of computation for each sample, the progress of iterative updates, termination checking, and final output generation. The control flow initiates iterative computation after input reception and sequentially activates the SOC Calculator and Termination Guard at each iteration step. As a result, all blocks operate under controller supervision in the order required to process one sample from input reception to the final SOC output.

The SOC Calculator computes the next SOC value from the input sample and the current SOC estimate. It scales the input voltage and current, constructs the OCV input using the ESR value and then selects the active polynomial region to evaluate the corresponding quadratic model. These operations are scheduled over multiple clock cycles using a shared 16 × 16 fixed-point multiplier, thereby reducing arithmetic resource usage without allocating separate multipliers to each step.

The Termination Guard evaluates the difference between the newly computed SOC and the previous estimate at each iteration and determines whether to stop based on the rule defined in Section 3. When the termination condition is met, the controller ends the iterative computation for that sample and outputs the final SOC. Otherwise, the updated estimate becomes the state for the next iteration. Through this structure, the Gauge Core performs the full iterative data flow—ESR lookup, OCV construction, piecewise polynomial evaluation, termination checking, and result output—consistently within the hardware.

4.2.3. Operator-Reuse Datapath

This subsection describes the operator-reuse datapath adopted by the Gauge Core to perform SOC estimation based on iterative updating within limited hardware resources. The focus is on reducing arithmetic cost by sharing a single multiplier across the input scaling stage, OCV construction, and piecewise quadratic evaluation instead of distributing the required multiplications across multiple parallel multipliers.

The SOC Calculator uses a sequential add–shift multiplier for 16 × 16 fixed-point multiplication. Fixed-point multiplication is implemented by first performing integer multiplication and then aligning the scale through a shift according to the predefined number of fractional bits, followed by normalization to the required bit width. Signed operation is handled using two’s complement representation. Because battery measurements arrive sample by sample, the overall timing budget is sufficiently relaxed that a sequential multiplier can complete the required computations within one sampling period. Thus, the proposed structure trades some arithmetic latency for lower hardware usage by avoiding duplicated multipliers.

The 16 × 16 fixed-point multiplier is shared across the datapath. As shown in Figure 8, the same multiplier is reused over time for input scaling, ESR-based OCV construction, and piecewise quadratic evaluation, allowing the computation to be carried out without additional multipliers. During this process, multiplier inputs are selected step by step through MUXA and MUXB, and the products are combined sequentially through the accumulation path to form intermediate terms and the final updated value. The progression of the arithmetic stages and operand selection is handled by a local FSM inside the SOC Calculator, coordinated with the top-level Gauge Core Controller so that iterative updating for each sample proceeds in a consistent order.

This operator-reuse datapath maintains the arithmetic precision and processing flow required for iterative updating while reducing redundant use of area intensive operators such as multipliers, making it advantageous for lightweight hardware implementation.

5. Experimental Results

This section presents experimental results that verify the real-time viability of the proposed gauge IP from a hardware perspective. Operation on a real-time FPGA battery measurement testbed is demonstrated, and the collected logs are used to evaluate SOC estimation accuracy quantitatively. In addition, synthesis and implementation reports are used to summarize hardware resource usage and timing, and ASIC layout and measurement results obtained through MPW fabrication are presented to support ASIC feasibility. Overall, this section shows that a lightweight gauge architecture based on FSM control can operate in real time without processor control, as evaluated from the viewpoints of estimation accuracy, implementation cost, and operating characteristics.

5.1. Experimental Setup

To verify the real-time operation of the gauge IP, an integrated testbed consisting of a 5S lithium-ion battery pack, an AFE board, an FPGA board, and a host PC was constructed. Figure 9 shows the overall testbed organization and interface connections, while Figure 10 presents the implemented validation setup. Battery terminal voltage and current were measured by an external analog front end (AFE) board and transmitted to the FPGA through an I2C interface. The gauge IP implemented on the FPGA then performed SOC estimation using the received measurements and output the result through an external observation path. All computations required for SOC estimation, including the termination decision of the iterative update, were executed in hardware logic, while the external components supported validation through data delivery and result logging. The experiments were conducted on a 5S series pack built from commercial lithium-ion cells, and the specifications of the 3.7 V cells used are summarized in

Table 3. Specifications of Samsung ICR18650-26F [38].

Parameter	Value	Unit
Cell format	18,650	–
Nominal capacity	2600	mAh
Nominal voltage	3.7	V
Charge voltage	4.2	V
Max. charge current	2600	mA
Max. discharge current	5200	mA
Discharge cutoff voltage	2.75	V

. Charge and discharge current profiles were applied, and terminal voltage and current measurements together with SOC estimation results were collected.

The FPGA target platform was a Digilent Nexys A7-100T board based on a Xilinx Artix-7 XC7A100T FPGA device (Xilinx Inc., San Jose, CA, USA). The RTL was written in Verilog HDL (IEEE Std 1364-2005) and synthesized using Xilinx Vivado Design Suite 2024.1 (Xilinx Inc., San Jose, CA, USA), and the generated bitstream was programmed onto the FPGA via a USB-JTAG interface. During real-time measurement, SOC estimation results generated by the gauge IP operating at a 50 MHz system clock were transmitted to the host PC through the board’s USB-UART interface and stored for accuracy evaluation.

To inspect the internal timing and control flow, a debugging environment based on the Vivado Integrated Logic Analyzer (ILA) was configured. ILA probes were connected to major input and output signals of the gauge IP, as well as the I2C and UART signals required for operation monitoring. This setup was used to verify that measurement reception, estimation, and result transmission proceeded as intended and to inspect communication waveforms and the timing of the control signals.

5.2. Accuracy Evaluation

This subsection quantitatively evaluates the SOC estimation accuracy of the proposed gauge IP. The evaluation was based on voltage and current logs collected during charge and discharge conditions on the real-time testbed described in Section 5.1, together with the SOC output logs from the gauge IP. Accuracy metrics were computed by aligning the gauge IP SOC output and the reference SOC at each sample index. The purpose of this subsection is to present the estimation performance of the lightweight hardware implementation using quantitative metrics under real-time operating conditions.

The adopted accuracy metrics are mean absolute error (MAE), normalized MAE (NMAE), and root mean square error (RMSE). MAE represents the average absolute error between the estimated SOC and the reference SOC over all samples. NMAE normalizes MAE by the SOC range so that results can be compared across conditions. RMSE is more sensitive to larger errors and is therefore reported as a complementary measure of error dispersion. In this paper, SOC is represented as a normalized quantity, and the same unit and range are used consistently in metric calculation. Letting N denote the total number of samples, the error between the reference SOC $S_{\mathrm{ref}}$ and the gauge IP output ${\widehat{S}}_k$ is defined as follows:

$$\mathrm{MAE}={\displaystyle \frac{1}{N}}{\displaystyle \sum _{k=1}^N}\left|S_{\mathrm{ref},k}-{\widehat{S}}_k\right|.$$

(2)

$$\mathrm{NMAE}(\%)={\displaystyle \frac{\mathrm{MAE}}{S_{\mathrm{range}}}}\times 100.$$

(3)

$$\mathrm{RMSE}=\sqrt{{\displaystyle \frac{1}{N}}\sum _{k=1}^N{\left(S_{\mathrm{ref},k}-{\widehat{S}}_k\right)}^2}.$$

(4)

Here, N is the total number of samples and $S_{\mathrm{range}}$ is the normalized SOC range. In this study, SOC was normalized to the range 0–1, so $S_{\mathrm{range}}=1$ was used for NMAE calculation.

The reference SOC in the experiments was generated offline from the measured voltage and current logs using the same reference OCV–SOC mapping data employed to construct the piecewise model and the ESR LUT. The gauge IP output ${\widehat{S}}_k$ and $S_{\mathrm{ref}}$ were then aligned using the sample index, and the error metrics were calculated.

Accuracy evaluation was performed for both charge and discharge tests. The charge test followed a CC/CV condition, whereas the discharge test used a CC condition, optionally including rest intervals. For each test, the collected voltage and current samples and the gauge IP SOC output were compared using the same indexing basis to calculate the error metrics. The results are presented through representative SOC trajectories and error distributions, together with summary metrics. Figure 11 presents representative SOC trajectories for the charge and discharge tests together with box plots of the sample-wise absolute error distributions across Cells 1–5.

Table 4. Error metrics of the proposed gauge IP under charge and discharge tests.

Condition	MAE	NMAE (%)	RMSE
Charge	0.0105	1.05	0.0127
Discharge	0.0241	2.41	0.0269

summarizes the achieved accuracy, and

Table 5. Accuracy comparison with representative hardware implementations.

Reference	Algorithm	Hardware Platform	Error (%)
Baccouche et al. [30]	Piecewise OCV–SOC + CC	MCU (PIC18F)	2
Nishanth et al. [36]	EKF	MCU (STM32F446RE)	4.2
Jemmali et al. [12]	EKF	ZC702 FPGA (XC7Z020)	0.84
Benkara et al. [35]	EKF	Spartan-6 FPGA (XC6SLX150)	5
Kim et al. [24]	EKF + FIR	Zynq-7020 FPGA (XC7Z020)	2
Proposed	Piecewise OCV–SOC + iterative update	Nexys A7-100T FPGA (XC7A100T)	1.6

CC: coulomb counting; FIR: finite impulse response. Error (%) values are reported as stated in each reference. Bold indicates the proposed implementation.

compares the overall sample error of this work with representative MCU and FPGA implementations reported in the literature. The 1.6% value reported in Table 5 is the overall NMAE computed over all charge and discharge samples.

5.3. Hardware Implementation Results

This subsection summarizes the FPGA resource usage and timing characteristics of the proposed gauge IP and then presents the MPW ASIC results. FPGA resource utilization was obtained from the Vivado implementation report. The resulting usage was 504 LUTs (0.79%) and 580 FFs (0.46%). In addition, no BRAM or DSP blocks were used, confirming that the proposed structure is a lightweight logic implementation that does not rely on dedicated memory or DSP resources. Resource efficiency was compared against FPGA implementations that explicitly reported absolute resource counts, and the comparison is summarized in

Table 6. FPGA resource utilization comparison with representative hardware implementations.

Reference	Jemmali et al. [12]		Benkara et al. [35]		Kim et al. [24]		Proposed
FPGA	ZC702 (XC7Z020)		Spartan-6 (XC6SLX150)		Zynq-7020 (XC7Z020)		Nexys A7-100T(XC7A100T)
Logic Utilization	Used	Util.	Used	Util.	Used	Util.	Used	Util.
LUT	12,192	22%	11,442	12%	1666	0.55%	504	0.79%
FF	5520	5%	15,395	8%	1140	0.19%	580	0.46%
BRAM	33	11%	–	–	4	0.39%	0	0%
DSP	220	100%	94	52%	10	0.36%	0	0%

Utilization values are reported as stated in each reference and may not be directly comparable across devices. An en dash (–) indicates that the value was not reported in the cited work. Bold indicates the proposed implementation.

.

To examine the convergence behavior of the termination rule, the number of iterations required until termination was recorded for each sample. As summarized in

Table 7. Iteration count results under charge and discharge conditions.

Condition	Average	Maximum	${\mathit{N}}_{max}$ Reached (%)
Charge	2.32	10	0.11
Discharge	2.43	10	0.35

, most samples terminated before reaching the maximum iteration guard. This result indicates that the 1-LSB criterion served as the main termination condition in normal operation, while the $N_{max}$ guard bounded rare prolonged iterations.

In terms of timing, the internal SOC computation latency of the proposed gauge IP was measured as 186 cycles at a 50 MHz system clock, corresponding to approximately 3.72 μs. This is about 0.0015% of the 250 ms sampling period used in the real-time testbed, indicating that SOC computation for each sample comfortably completes before the next update instant. Therefore, even though the proposed structure relies on sequential computation with a shared multiplier, it satisfies the timing budget required for real-time SOC updating for each sample.

The ASIC implementation results of the proposed gauge IP are summarized in

Table 8. ASIC implementation results of the proposed gauge IP.

Metric	Proposed Gauge IP
Process technology	TSMC 28 nm CMOS
Die size of shared chip	2.2 mm × 3.3 mm
Chip target frequency	200 MHz
Operating frequency	50 MHz
Gate count	12,026 gates

. The IP was integrated as one block in a shared MPW chip fabricated in a TSMC 28 nm CMOS process, and the die size of the shared chip is 2.2 mm × 3.3 mm. The proposed gauge IP was configured to operate with a divided 50 MHz clock, and its gate count was estimated as 12,026 gates. Figure 12 shows the physical layout of the chip containing the proposed gauge IP. This layout result indicates that the proposed SOC estimation logic based on FSM control is sufficiently lightweight to be integrated as a digital block in an MPW chip.

6. Discussion

The significance of this work lies in implementing an iterative estimation flow based on the OCV–SOC relationship as a standalone gauge IP based on FSM control and translating it into a lightweight hardware architecture suitable for actual implementation. The proposed structure combines a polynomial OCV–SOC model, an ESR LUT, fixed-point arithmetic, and an operator-reuse datapath, and it performs both estimation and termination checking entirely in hardware. By combining a 1-LSB termination rule with a guard based on the maximum number of iterations, the design achieves predictable runtime behavior for iterative estimation in real-time operation. From this perspective, the proposed gauge IP can be interpreted as a lightweight hardware architecture for SOC estimation in resource constrained environments.

The FPGA and ASIC implementation results support the validity of this design direction. The proposed gauge IP achieved an overall error of about 1.6% on the charge and discharge datasets collected from the real-time testbed while using only 504 LUTs and 580 FFs. In addition, the internal SOC computation latency was approximately 3.72 μs at 50 MHz, which is well within the 250 ms sampling period used in the real-time testbed. Furthermore, the design was integrated as a block in an MPW chip fabricated in a TSMC 28 nm CMOS process, demonstrating that the proposed architecture can be realized as a lightweight gauge IP suitable for integration at chip level.

This work prioritizes lightweight hardware implementation, and thus factors, such as temperature variation, long term aging, hysteresis, and cell-to-cell mismatch, in environments with multiple cells are not explicitly incorporated in the current structure. These factors can change the OCV–SOC and ESR characteristics of the cell and may therefore require additional compensation or calibration mechanisms. Accordingly, the proposed design should be understood not as a complete battery state estimator that covers all possible operating conditions, but rather as a baseline architecture focused on hardware implementation. Future work can broaden the applicability of the design through temperature dependent OCV–SOC and ESR modeling, aging aware coefficient calibration, multichannel extension based on time sharing, and integration with higher level control structures for multiple cells. Further validation under more diverse load profiles and long-term operating conditions could also evolve the proposed gauge IP into a lightweight estimation core for BMS SoCs or ASICs.

7. Conclusions

This paper proposed an iterative SOC estimation method based on the OCV–SOC relationship and a corresponding standalone gauge IP based on FSM control for lightweight hardware implementation in embedded BMS environments. The method models the reference OCV–SOC curve with a two-region quadratic polynomial, corrects OCV using an ESR LUT, and updates SOC iteratively using 16-bit fixed-point arithmetic and an operator-reuse datapath. In addition, the design incorporates an FSM control structure without a microprocessor together with a termination guard, so that the compact OCV–SOC model, fixed-point datapath, and operator-reuse structure can support real-time operation under constrained hardware resources.

Real-time validation on an FPGA testbed showed that the proposed gauge IP achieved an overall NMAE of 1.6% and was implemented on an Artix-7 XC7A100T using only 504 LUTs and 580 FFs. The design was also integrated as a block in an MPW chip fabricated in a TSMC 28 nm CMOS process, yielding a physical layout corresponding to 12,026 gates. These results demonstrate that the proposed architecture is a lightweight hardware solution capable of real-time SOC estimation in resource constrained environments.