Design of Lossless Negative Capacitance Multiplier Employing a Single Active Element

: In this paper, a new negative lossless grounded capacitance multiplier (GCM) circuit based on a Current Feedback Operational Ampliﬁer (CFOA) is presented. The proposed circuit includes a single CFOA, four resistors, and a grounded capacitor. In order to reduce the power consumption, the internal structure of the CFOA is realized with dynamic threshold-voltage MOSFET (DTMOS) transistors. The eﬀects of parasitic components on the operating frequency range of the proposed circuit are investigated. The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters. The total power consumption of the circuit was 1.6 mW. The functionality of the circuit is provided by the capacitance cancellation circuit. PVT (Process, Voltage, Temperature) analyses were performed to verify the robustness of the proposed circuit. An experimental study is provided to verify the operability of the proposed negative lossless GCM using commercially available integrated circuits (ICs).


Introduction
High-value capacitors in IC technology require a large silicon area.To address this issue, capacitance multiplier (CM) circuits capable of multiplying capacitance have been proposed to obtain large capacitance from small capacitance values.Therefore, CM circuits play an essential role in obtaining high-value capacitances.
A literature survey reveals that there are various CM circuits are reported using numerous versatile active building blocks (ABBs).However, upon careful examination of the circuit configurations published in the literature, they are considered to suffer from some of the limitations given below.
The resistance-controlled negative capacitance multiplier circuit presented by Abuelma'a i and Dhar consists of two CFOAs, two floating resistors, and a floating capacitor [20].The negative CM circuit proposed by Dogan and Yuce includes a single CFOA, three resistors, and a capacitor [21].The circuit proposed by Al-Absi and Abuelma'a i includes one CFOA and two OTAs.It is configured as an OTA-negative resistor to achieve an adjustable negative impedance multiplier [22].The resistor-free circuit presented by Stornelli et al. consists of an E-VCII-and a capacitor [23].
Many of the negative CMs available in the literature contain two or more ABBs [19,20,22,24,25,27,28].There are also circuits that contain only one active device [19,21,23,26,[29][30][31]. When designing negative CMs, excessive use of active and passive elements should be avoided as this will increase power consumption.Negative CMs presented by researchers have generally been realized through the use of three or more passive elements [19][20][21]24,25,28,30,31].Negative CMs containing a single capacitor have also been proposed, but each of these circuits operates with two or more active components [22,27].
The aim of this work was to design a negative lossless GCM circuit using currently commercially available ICs, namely the AD844 [32].The proposed circuit is designed with a single CFOA, four resistors and a grounded capacitor.The internal structure of the CFOA is built with DTMOS transistors to reduce power consumption.The total power consumption of the circuit is 1.6 mW.The non-ideal analysis for the proposed circuit has been investigated in detail.A capacitance cancellation circuit is presented as an application example.To verify the operability of the proposed circuit, it has been experimentally tested using commercially available ICs, namely AD844s.
The paper is structured as follows: Section 2 introduces the proposed circuit utilizing a CFOA.The non-ideal analysis is given in Section 3. SPICE simulation results and discussions are given in Section 4.An application example is presented in Section 5. Finally, Section 6 concludes the paper.

The Proposed Circuit
The terminal relations of CFOAs, whose circuit symbol and equivalent circuit are given in Figures 1 and 2, respectively, can be represented in the following matrix equation: where α(s) represents the current gain which is ideally equal to unity.Also, the β(s) and η(s) correspond to voltage gains and ideally both of them are equal to unity.Furthermore, α(s), β(s), and η(s) can be given by Herein, represents the current-tracking error, ideally equal to zero, while and denote the voltage tracking errors, also ideally equal to zero.It is assumed that | |, , and are significantly smaller than one.
In addition, , , and denote corner frequencies of the relevant parameter.Furthermore, in an ideal case, Rin is infinity and the port relationships of the CFOA are expressed by the following equations: VX = VY, IY = 0, IZ = IX, and VW = VZ.The proposed negative lossless GCM is depicted in Figure 3. Without passive element matching conditions, the input admi ance (Yin) of the circuit is obtained as follows: If R2 = R1 is selected for the circuit in Figure 3, the input admi ance is simplified as follows.When this condition is met, the circuit can simulate negative lossless GCM.The equivalent capacitance (Ceq) and the multiplication factor (K) are given by As can be seen from Equation ( 8), if one of the resistors R3 or R4 is replaced with an MOS-based voltage-controlled resistor, the multiplication factor becomes electronically controllable.
The sensitivity of the K with respect to the tuning resistors is given below.

Non-Ideal Analysis
The non-ideal equivalent circuit of a CFOA is shown in Taking into account the effects of the non-ideal gains of the CFOA, the input admittance of the circuit is obtained as follows.
Considering the non-ideal gains of the CFOA, the equivalent circuit of the proposed circuit is given in Figure 5; the values of the equivalent components are given in Equations ( 14)-( 16).
The sensitivity analysis is given below.

= ( + )
= + = − ( + ) Under the specified condition where only the parasitic impedances of the X, Y, Z, and W terminals are considered, the input admi ance is derived in the form presented in Equation (22).
In this context, ai and bi represent the real coefficients of the driving point admi ance Yin(s).
In the ideal case, the input admi ance of the capacitor is of the form Yin(s) = a1s/b0.To obtain a lossless capacitor, the terms other than a1s and b0 need to be small enough.In other terms, when s is substituted with jω, the following inequalities must be concurrently fulfilled to approximate the ideal capacitor admi ance: According to the inequalities given above, the operating frequency range of the proposed circuit is calculated approximately as follows.

Simulation Results
In order to reduce the power consumption of analog integrated circuits, operations with lower supply voltages can be provided by DTMOS technology [33][34][35][36][37].To obtain a DTMOS transistor, the body and gate terminals of the MOSFET are short-circuited as shown in Figure 6.The DTMOS-based implementation of the CFOA, derived from the CCII+ presented in reference [38], is depicted in Figure 7.  1.The parasitic impedances and non-ideal gains of the CFOA are delineated in Table 2. Internal structure of the CFOA using DTMOS transistors [8].
The functionality of the proposed negative GCM was examined under the following simulation conditions.Detailed simulation se ings are included in Table 3.The frequency response of the input impedance of the proposed negative lossless GCM is given in Figure 8 for various multiplication factors (K).By selecting the passive elements as = 100 , = = 10 Ω, = = 100 Ω, = 10 Ω, = 1 Ω, and = = 10 Ω, the multiplication factors are set to = −10, = −50.5, and = −500.5,resulting in Ceq = −1 nF, −5.05 nF, and −50.05 nF, respectively.In Figure 9, a comparison of the proposed negative GCM with the ideal capacitor for Ceq = 5, 50, and 500 nF is given by selecting K = 10, C = 0.5, 5, and 50 nF, respectively.The frequency responses of the proposed circuit to various supply voltages are shown in Figure 10.Monte Carlo (MC) simulations were conducted for 100 runs.The simulation results for a 10% change in the threshold voltages and gate oxide thicknesses of all MOS transistors and a 5% change in the width of all MOS transistors are shown in Figures 11 and 12, respectively.A temperature analysis of the circuit is also depicted in Figure 13.
A table of comparisons of previously reported negative CM circuits using various ABBs can be seen in Table 4.The proposed circuit contains a single CFOA.Compared to other circuits implemented with a single active component, the number of passive elements is relatively high.However, to reduce power consumption, the internal structure of the CFOA is designed using the DTMOS technique.Power consumption can be reduced by using MOS-based resistors.The multiplication factor of the circuit can be adjusted up to 500.In addition, according to Figure 8, the operating frequency reaches 80 MHz.Considering its simplicity, operating frequency, and multiplication factor, it is clear that the proposed circuit is superior to the circuits in the literature.

Application Example
This section presents an application example to demonstrate the robustness and workability of the proposed GCM.The application example shown in Figure 14 is the capacitive cancellation circuit in which the parasitic capacitors in the output circuits are eliminated.Here, the negative capacitor (Ceq) is obtained with the proposed negative lossless GCM.The resistance currents and in the circuit are given below.If the condition = − is satisfied, and will be equal., is given in Figure 15.According to the results, the circuit is compatible with ideal results up to 10 MHz.
A sinusoidal waveform of 300 mV amplitude and 100 kHz frequency was applied to the input of the circuit.Waveforms of and currents are given in Figure 16.The current waveforms have the same amplitude and phase, indicating that the parasitic capacitance is eliminated in the proposed circuit.

Conclusions
In this study, a new circuit configuration was introduced to realize the negative lossless GCM.The proposed circuit contains a single CFOA, four resistors, and a grounded capacitor.A detailed analysis of the circuit has been carried out.The factors affecting the frequency range have been investigated through mathematical analyses.In order to reduce the power consumption of the circuit, a CFOA was obtained by using DTMOS transistors.The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters.The total power consumption of the circuit was 1.6 mW.The workability of the circuit has been shown by providing a capacitive cancellation circuit application and an experimental study.
Author Contributions: Conceptualization of this manuscript was by M.V.; the methodology by M.V., E.Ö. and F.K.; software verifications in SPICE by M.V.; validation by M.V., E.Ö. and F.K.; formal checking of the analysis by E.Ö. and F.K.; investigation by M.V.; resources by M.V., E.Ö. and F.K.; data curation by M.V.; writing-original draft preparation by M.V.; writing-review and editing by M.V., E.Ö. and F.K.; visualization by M.V.; supervision by E.Ö. and F.K.; project administration by M.V., E.Ö. and F.K. All authors have read and agreed to the published version of the manuscript.
Funding: This research received no external funding.

Figure 1 .
Figure 1. Circuit symbol of the CFOA.

Figure 2 .
Figure 2. Equivalent circuit of the CFOA.

Figure 4 .
Here, RX, RZ, and RW indicate parasitic resistors.Also, CY and CZ demonstrate the parasitic capacitors.Ideally, these parasitic elements are X = RW = CZ = CY = 0 and RZ = ꝏ.The terminal relations of the CFOA in non-ideal conditions are given in Equation (12).

Figure 5 .
Figure 5. Equivalent circuit taking into account the non-ideal gains of the CFOA.

Figure 8 .
Figure 8. Frequency response of the proposed negative lossless GCM and ideal capacitor for K = −10, −50.5, and −500.5 by selecting C = 100 pF; (a) magnitude and (b) phase responses.

Figure 10 .
Figure 10.Frequency responses of the proposed negative lossless GCM for various supply voltages; (a) magnitude and (b) phase responses.

Figure 11 .
Figure 11.Monte Carlo simulation results for 10% variation in the threshold voltages (VTH) and gate oxide thickness (tox) of all the MOS transistors; (a) magnitude and (b) phase responses.

Figure 12 .
Figure 12.Monte Carlo simulation results for 5% variation in width of all the MOS transistors; (a) magnitude and (b) phase responses.

Figure 13 .
Figure 13.Temperature analysis for the proposed negative lossless GCM; (a) magnitude and (b) phase responses.

Figure 15 .
Figure 15.Frequency performance of the capacitance cancellation circuit.

Figure 16 .
Figure 16.The current waveforms of and for the circuit in Figure 14.

Table 1 .
The transistor dimensions.

Table 2 .
Parasitic impedances and non-ideal gains of the CFOA.

Table 3 .
Detailed simulation results and passive component se ings.

Table 4 .
Comparison of negative CM circuit.