Design and Implementation of Single-Phase Grid-Connected Low-Voltage Battery Inverter for Residential Applications

: Integrating residential energy storage and solar photovoltaic power generation into low-voltage distribution networks is a pathway to energy self-sufficiency. This paper elaborates on designing and implementing a 3 kW single-phase grid-connected battery inverter to integrate a 51.2-V lithium iron phosphate battery pack with a 220 V 50 Hz grid. The prototyped inverter consists of an LCL -filtered voltage source converter (VSC) and a dual active bridge (DAB) DC-DC converter, both operated at a switching frequency of 20 kHz. The VSC adopted a fast DC bus voltage control strategy with a unified current harmonic mitigation. Meanwhile, the DAB DC-DC converter employed a proportional-integral regulator to control the average battery current with a dynamic DC offset mitigation of the medium-frequency transformer’s currents embedded in the single-phase shift modulation scheme. The control schemes of the two converters were implemented on a 32-bit TMS320F280049C microcontroller in the same interrupt service routine. This work presents a synchronization technique between the switching signal generation of the two converters and the sampling of analog signals for the control system. The prototyped inverter had an efficiency better than 90% and a total harmonic distortion in the grid current smaller than 1.5% at the battery power of ± 1.5 kW.


Introduction
Reduction of CO 2 emissions has been driving shares of renewable energy in electricity generation systems.Solar photovoltaic (PV) technology has been the fastest-growing renewable energy technology since it can be adopted in small-scale to large-scale power generation systems [1].Grid-connected PV rooftop systems are commonly installed in the residential sector.However, the excess power from the residential PV rooftop systems poses power quality problems for low-voltage (LV) distribution networks.Voltage violation due to the outfeed of PV power is the most common issue for the LV grid [2].Extensive upgrades of LV distribution networks for supporting solar PV rooftop systems require a large amount of capital investment.Battery storage is an enabling technology for further deployment of variable renewable energy (VRE) technology.Moreover, integrating battery storage with LV grids reduces transmission congestion, improves power quality, and delays investment in upgrading existing networks [3,4].
Solar PV and battery storage integration into LV distribution networks can be implemented in various topologies.Battery storage can be connected to solar PVs on the DC side of the grid inverter, as depicted in Figure 1.These topologies are so-called DC coupling solar PV-battery hybrid inverters.The DC bus voltage is usually greater than the PV voltage, so non-isolated boost DC-DC converters interface the PV strings with the voltage, so non-isolated boost DC-DC converters interface the PV strings with the DC bus voltage.Maximum power point tracking (MPPT) is embedded with the control system of the boost DC-DC converter [5,6].A high voltage (HV) battery pack can be directly connected to the DC bus of the grid inverter, as shown in Figure 1a [7].The battery voltage must be greater than the minimum requirement of the grid inverter, i.e., the peak value of the grid voltage for a single-phase system, and the peak value of the line-line voltage of a three-phase system.An HV battery pack can be connected to the DC bus via a non-isolated DC-DC converter, as shown in Figure 1b.Typically, a bidirectional buck-boost DC-DC converter allows a wide battery voltage range (200-500 V).Meanwhile, the DC bus voltage is regulated above the minimum requirement of the grid-interfaced inverter.A battery back requires an electronic battery management system (BMS) for voltage balancing, management, and protection of the galvanic cells [8].Thus, HV battery storage with complex BMS may only be viable for some residential systems.Low-voltage battery storage (less than 100 V) with a less complicated and cheaper BMS can be a suitable option for a small household (less than 5 kW), as illustrated in Figure 1c [7].The LV battery pack is interfaced with the DC bus through a bidirectional isolated DC-DC converter, which employs a medium frequency (MF) (20-150 kHz) transformer for voltage matching the LV battery pack with the DC bus [9,10].Battery storage can be integrated with the LV network by the AC coupling topologies shown in Figure 2. A grid-interfaced inverter is dedicated to the battery systems of the DC coupling topologies in Figure 1.PV power  , battery power  , load power  , and grid power  are exchanged at the AC point of common coupling (PCC).The AC coupling topologies have a lower efficiency than the DC coupling systems due to an increased conversion stage [11].However, the AC coupling systems can be employed with existing grid-connected PV inverters or without any PV inverter for energy arbitrage or peak load shaving [7].AC-coupled two-stage LV battery inverters depicted in Figure 2c are common for small residential applications with a power lower than 5 kW.The power conversion stages can be integrated with the battery pack into a single package [12,13].voltage, so non-isolated boost DC-DC converters interface the PV strings with the DC bus voltage.Maximum power point tracking (MPPT) is embedded with the control system of the boost DC-DC converter [5,6].A high voltage (HV) battery pack can be directly connected to the DC bus of the grid inverter, as shown in Figure 1a [7].The battery voltage must be greater than the minimum requirement of the grid inverter, i.e., the peak value of the grid voltage for a single-phase system, and the peak value of the line-line voltage of a three-phase system.An HV battery pack can be connected to the DC bus via a non-isolated DC-DC converter, as shown in Figure 1b.Typically, a bidirectional buck-boost DC-DC converter allows a wide battery voltage range (200-500 V).Meanwhile, the DC bus voltage is regulated above the minimum requirement of the grid-interfaced inverter.A battery back requires an electronic battery management system (BMS) for voltage balancing, management, and protection of the galvanic cells [8].Thus, HV battery storage with complex BMS may only be viable for some residential systems.Low-voltage battery storage (less than 100 V) with a less complicated and cheaper BMS can be a suitable option for a small household (less than 5 kW), as illustrated in Figure 1c [7].The LV battery pack is interfaced with the DC bus through a bidirectional isolated DC-DC converter, which employs a medium frequency (MF) (20-150 kHz) transformer for voltage matching the LV battery pack with the DC bus [9,10].Battery storage can be integrated with the LV network by the AC coupling topologies shown in Figure 2. A grid-interfaced inverter is dedicated to the battery systems of the DC coupling topologies in Figure 1.PV power  , battery power  , load power  , and grid power  are exchanged at the AC point of common coupling (PCC).The AC coupling topologies have a lower efficiency than the DC coupling systems due to an increased conversion stage [11].However, the AC coupling systems can be employed with existing grid-connected PV inverters or without any PV inverter for energy arbitrage or peak load shaving [7].AC-coupled two-stage LV battery inverters depicted in Figure 2c are common for small residential applications with a power lower than 5 kW.The power conversion stages can be integrated with the battery pack into a single package [12,13].This study focuses on a two-stage single-phase grid-connected LV battery inverter for small residential applications.A dual-active bridge DC-DC converter with phase-shift modulation strategies is generally employed as the bidirectional isolated DC-DC converter for the LV battery pack.Meanwhile, LCL-filtered grid-connected voltage source converters (VSCs) are commonly adopted as the grid-interfaced inverter.However, a limited zerovoltage switching (ZVS) range of the DAB DC-DC converter causes a low efficiency if the voltage ratio between the sides deviates from the nominal value [14].The efficiency of the DAB DC-DC converter can be enhanced by adding resonant networks to the MF transformer to increase the ZVS range [15,16].However, power transfer of the resonant DAB DC-DC converter can be controlled by variation of the switching frequency, which is more complicated compared to the fixed frequency operation of the conventional DAB DC-DC converter.The DAB DC-DC converter is sensitive to an imbalance in the voltage-second applied to the MF transformer, which causes a DC offset in the transformer current [17].The primary and secondary currents of the transformer were sampled 10 times over a switching period to determine the DC offset component, from which the DC offset was compensated through the duty ratios applied to the two active bridges.This method can attenuate the dynamic and static DC offset components [18].For simplicity, the dynamic DC offset compensation can be embedded into the modulation scheme, where the phase angle of each leg of the DAB DC-DC converter is independently controlled [19,20].These dynamic DC offset compensation methods require only delay elements.
The bus voltage is controlled through the VSC.The intrinsic double-frequency ripple component in the bus voltage can distort the grid current waveform [21].A notch filter is usually employed to block the double-frequency ripple component to enter the bus voltage control loop so that the loop bandwidth can be increased with reduced bus capacitance and a near sinusoidal grid current waveform [22,23].However, low-frequency harmonic components in the grid voltage and VSC terminal caused by the dead time effect can still distort the grid current waveform [24].Recently, a unified current harmonic mitigation was adopted in a grid-connected VSC [24], which maintained the grid current near sinusoidal with a fast bus voltage control and rejection of voltage harmonic components in the grid and non-ideal switching of the VSC [24].
As mentioned above, the control techniques of the DAB DC-DC converter and gridconnected VSC have been widely presented.However, microcontroller-based implementation techniques of the two converters, with the generation of switching signals and interrupt request and analog signal sampling, have yet to be reported.Thus, this study covers the design and implementation of a single-phase grid-connected low-voltage battery inverter.The battery inverter consists of a DAB DC-DC converter and an LCL-filtered VSC thanks to their constant switching frequency application, which eases the implementation of the control system.The control systems of the two converters were implemented in the same microcontroller within the same interrupt service routine (ISR).Synchronous operations of the switching signal generation for the VSC and DAB DC-DC converter and sampling analog signals are highlighted.This work also presents a battery current control strategy with a dynamic DC offset mitigation of the MF transformer.Experimental validation of the proposed inverter is presented.

System Description
The main objective of this study is to design a 3 kW bidirectional inverter for interfacing a 16-cell lithium iron phosphate (LFP) battery pack with a single-phase 220 V 50 Hz grid for residential energy storage applications.Figure 3 shows the inverter topology in this study.The grid voltage v g (t) is converted to a 400 V DC voltage v D (t) through an LCLfiltered VSC.A DAB DC-DC converter well suits the second-stage battery converter as the voltage matching and galvanic isolation are achieved via the MF transformer.Moreover, if properly designed, the DAB DC-DC converter exhibits high efficiency thanks to the ZVS operation [14].The VSC adopts the cascade control structure with the bus voltage control as the outer loop and the grid current control as the inner loop.The VSC can inject reactive power through the reference current i * q (t) for grid support functionality.The inverse Park transformation phase-locked loop (PLL) [25] provides the estimated angle θ of the grid voltage for synchronization with the grid.The battery current i B (t) is regulated by a proportional-integral (PI) controller with the reference phase difference δ * between the primary and secondary voltages v p (t) and v s (t) of the transformer, which are generated by the LV and HV bridges with the single-phase shift (SPS) modulation.The DC offset mitigation technique for the transformer currents i p (t) and i s (t) is implemented with the SPS modulation.The series inductor L a limits the maximum charge/discharge current [20].The VSC and the DAB DC-DC converter's control systems and switching signal generation are implemented on a TMS320F280049C 32-bit microcontroller from Texas Instruments (Dallas, TX, USA) [26].Table 1 summarizes the main specifications of the battery inverter.Note that the winding resistance symbols R 1 , R a , and R g of the inductors L 1 , L a , and L g are not illustrated in Figure 1 for simplicity.Table 2 lists the parameters of the battery inverter.
control as the outer loop and the grid current control as the inner loop.The VSC can in reactive power through the reference current  *  for grid support functionality.The verse Park transformation phase-locked loop (PLL) [25] provides the estimated angl of the grid voltage for synchronization with the grid.The battery current   is re lated by a proportional-integral (PI) controller with the reference phase difference  * tween the primary and secondary voltages   and   of the transformer, which generated by the LV and HV bridges with the single-phase shift (SPS) modulation.T DC offset mitigation technique for the transformer currents   and   is imp mented with the SPS modulation.The series inductor  limits the maximum charge/d charge current [20].The VSC and the DAB DC-DC converter's control systems and swit ing signal generation are implemented on a TMS320F280049C 32-bit microcontroller fr Texas Instruments (Dallas, TX, USA) [26].Table 1 summarizes the main specification the battery inverter.Note that the winding resistance symbols  ,  , and  of the ductors  ,  , and  are not illustrated in Figure 1 for simplicity.Table 2 lists the rameters of the battery inverter.

VSC Modeling
The grid current i g (t) and bus voltage v D (t) of the VSC are the controlled variables.Averaging over a switching period T sw yields the governing equations for i g (t) as follows: where v c (t) is the VSC terminal voltage, d 1 (t) and d 2 (t) are the duty ratios of S 9 and S 11 ranging from zero to unity, and m(t) is the modulation signal.The grid current typically has a faster response than the bus voltage.Thus, the instantaneous bus voltage v D (t) in ( 5) can be approximated with its average value V D .Equations ( 1)-( 5) lead to the transfer function of the grid current given by Neglecting power losses in the VSC and the DAB DC-DC converter, the bus voltage is governed by where p B (t) is the battery power.The instantaneous power in the LCL filter is comparatively small, which yields where p g (t) is the instantaneous grid power.Substitution of ( 8) into (7) and linearizing around the average bus voltage setpoint V * D , the bus voltage dynamic becomes The grid voltage is given by where V1 is the amplitude of the fundamental component, and ω 1 = 2π f 1 is the fundamental frequency of the grid voltage.The grid current is usually controlled to be sinusoidal with an amplitude of Î1 and a phase angle of ϕ 1 , as given by The grid current in (11) can be decomposed to the dq−axes components i d (t) and i q (t) in the virtual synchronous reference frame as The grid current in (11) leads to the instantaneous grid power expressed by where P g1 (t) and Q g1 (t) are the average active and reactive power components, and ∼ p g1 (t) is the oscillating power component at the frequency of 2ω.The oscillating power component in the bus voltage, while the average power component P g1 (t) changes the average component V D (t) of the bus voltage.By substituting P g1 (t) in ( 13) into ( 9), V D (t) can be approximated as where P B (t) is the average component of the battery power.Note that ( 14) is accurate for a frequency below 2ω.

VSC Control System Implementation
Figure 4 shows the VSC control system.A proportional-integral (PI) regulator is employed for the bus voltage control loop with a low-pass filter (LPF) for shaping the loop frequency response.Meanwhile, the grid current controller adopts the unbalanced synchronous reference frame control with PI regulators for the fundamental component.This control technique employs the grid current as the α-component and the orthogonal reference current i * β (t) as the β-component for the axis transformation.In our previous work [24], the stationary reference frame equivalence G ci1 (s) of the unbalanced synchronous reference frame control with the PI regulators was theoretically and experimentally proven to be identical to a proportional-resonant regulator, as given by where K p1 and K i1 are the proportional and integral gains of the PI controller.Three possible harmonic sources distort the grid current waveforms, which can be suppressed by multiple resonant (MR) controllers given by where h is the harmonic order number, and K ih is the resonant gain at order h th .Figure 5 depicts the stationary reference frame's equivalent grid current control block diagram.The VSC is represented by where T d is the delay time caused by the sampling time of the control system and the transportation time of the pulse width modulation (PWM) process.Undesirable lowfrequency harmonic components can be present in the grid voltage v g (t) and in the VSC terminal voltage v c (t) due to switching dead times.The 2ω ripple component in the bus voltage control loop with a bandwidth greater than 0.2ω also distorts the reference current i * g (t) [24].With this current control structure, the transfer functions of the grid current to these three harmonic sources are written as follows [24].
Electronics 2024, 13, x FOR PEER REVIEW 7 of 20 where  is the delay time caused by the sampling time of the control system and the transportation time of the pulse width modulation (PWM) process.Undesirable low-frequency harmonic components can be present in the grid voltage   and in the VSC terminal voltage   due to switching dead times.The 2 ripple component in the bus voltage control loop with a bandwidth greater than 0.2 also distorts the reference current  *  [24].With this current control structure, the transfer functions of the grid current to these three harmonic sources are written as follows [24].
(20) The MR regulator has infinite gains at selective frequencies, attenuating the harmonic components in  *  ,   , and   .Meanwhile, the fundamental component of  *  is regulated by the unbalanced synchronous reference frame controller with an infinite gain at  .Figure 6 depicts the equivalent bus voltage control loop.The low-pass filter   This study employs the discontinuous PWM techniques shown in Figure 7.The positive half of   is used as the duty ratio reference for switches  and  , and the pos- The MR regulator has infinite gains at selective frequencies, attenuating the harmonic components in i * g (t), v g (t), and v c (t).Meanwhile, the fundamental component of i * g (t) is regulated by the unbalanced synchronous reference frame controller with an infinite gain at ω 1 .Figure 6 depicts the equivalent bus voltage control loop.The low-pass filter time constant T f designed with the PI controller's constants K pv and K iv is used for loop shaping.The grid current control loop is approximated as a unity gain because its bandwidth is far higher than the bus voltage control loop.The rejection of the harmonic components in the reference current allows the bandwidth of the bus voltage control loop to increase while maintaining the grid current near sinusoidal.This study employs the discontinuous PWM techniques shown in Figure 7.The positive half of   is used as the duty ratio reference for switches  and  , and the positive half of −  for switches  and  .This PWM technique has a lower commonmode voltage and switching loss than the unipolar PWM [27].Meanwhile, the VSC current   maintains a small ripple due to the three-level voltage output at the VSC terminal.Figure 8 illustrates the generation of the switching signals and interrupt setting.Time base counter 1 of the microcontroller [26] is set to operate in the up-down mode with the counter maximum value of PWMprd, which generates the interrupt signal when the counter value equals zero.The value of PWMprd is obtained from where  100 MHz is the microcontroller's clock frequency [26].Thus, PWMprd = 2500 for a switching frequency of 20 kHz.This interrupt signal simultaneously triggers the selected analog-to-digital converters (ADCs) for voltage and current signal sampling at the time instant  and the interrupt service routine (ISR) of the control algorithm for the VSC and DAB DC-DC converter.The resultant duty ratios are updated at the time instant  1.Each counter consists of two compare registers (CMPAx and CMPBx), independently controlling two PWM outputs (PWMxA and PWMxB).For the VSC control, only CMPAx registers generate the PWMxA outputs, while the PWMxB outputs are opposite to the relevant PWMxA outputs with a switching dead time (active high complementary with a dead time) [26].Thus, the PWM1A and PWM1B outputs of counter 1 control switches  and  , and the PWM2A and PWM2B outputs of counter 2 for switches  and  .The synchronized operation between the ADC and PWM samples the average value of the grid current in each switching period both for the positive and negative regions of the modulation signal, as illustrated in Figure 8.This study employs the discontinuous PWM techniques shown in Figure 7.The positive half of m(t) is used as the duty ratio reference for switches S 9 and S 10 , and the positive half of −m(t) for switches S 11 and S 12 .This PWM technique has a lower commonmode voltage and switching loss than the unipolar PWM [27].Meanwhile, the VSC current i 1 (t) maintains a small ripple due to the three-level voltage output at the VSC terminal.Figure 8 illustrates the generation of the switching signals and interrupt setting.Time base counter 1 of the microcontroller [26] is set to operate in the up-down mode with the counter maximum value of PWMprd, which generates the interrupt signal when the counter value equals zero.The value of PWMprd is obtained from where f clk = 100 MHz is the microcontroller's clock frequency [26].Thus, PWMprd = 2500 for a switching frequency of 20 kHz.This interrupt signal simultaneously triggers the selected analog-to-digital converters (ADCs) for voltage and current signal sampling at the time instant k and the interrupt service routine (ISR) of the control algorithm for the VSC and DAB DC-DC converter.The resultant duty ratios are updated at the time instant k + 1.Each counter consists of two compare registers (CMPAx and CMPBx), independently controlling two PWM outputs (PWMxA and PWMxB).For the VSC control, only CMPAx registers generate the PWMxA outputs, while the PWMxB outputs are opposite to the relevant PWMxA outputs with a switching dead time (active high complementary with a dead time) [26].Thus, the PWM1A and PWM1B outputs of counter 1 control switches S 9 and S 10 , and the PWM2A and PWM2B outputs of counter 2 for switches S 11 and S 12 .
The synchronized operation between the ADC and PWM samples the average value of the grid current in each switching period both for the positive and negative regions of the modulation signal, as illustrated in Figure 8.
Hence, the phase angle  is used as the controlled variable for the battery current control loop as shown in Figure 3.The theoretical range of the phase angle  is /2.The DAB DC-DC converter exhibits the ZVS operation if the ratio between the voltages of the two DC sides is close to the transformer's turn ratio [28].This ZVS range gets wider at a higher phase shift angle [14].On the other hand, the root mean square (RMS) values of the MF transformer's currents increase with the phase shift angle [10].The voltage v P (θ sw ) of the LV bridge leads the voltage v s (θ sw ) of the HV bridge by a phase angle of δ, which causes power to flow from the battery to the bus voltage.On the other hand, power transfers from the bus voltage to the battery with a phase angle of −δ.Thus, the transferred power P DAB of the DAB DC-DC converter is controlled by the angle δ by Neglecting losses in the DAB DC-DC converter, the average value I LVB of the LV bridge input current i LVB and the average battery current I B are derived from P DAB by Hence, the phase angle δ is used as the controlled variable for the battery current control loop as shown in Figure 3.The theoretical range of the phase angle δ is ±π/2.The DAB DC-DC converter exhibits the ZVS operation if the ratio between the voltages of the two DC sides is close to the transformer's turn ratio [28].This ZVS range gets wider at a higher phase shift angle [14].On the other hand, the root mean square (RMS) values of the MF transformer's currents increase with the phase shift angle [10].
Flux density B(t) is an essential parameter for the design of the MF transformer and series inductor.According to the circuit topology in Figure 3, the transformer's primary winding is directly connected to the LV bridge.So, the peak flux density BT of the transformer is proportional to the battery voltage, as given by where A c is the cross-sectional area of the transformer core.Meanwhile, the peak flux density BL of the series inductor is determined from the voltage across the inductor v La (θ sw ) in Figure 9, as given by where N L is the winding turn number of the inductor.The peak flux densities BT and BL must be kept below the saturation flux density Bsat of the core material.

𝐵 𝑣 𝑑𝑡
where  is the cross-sectional area of the transformer core.Meanwhile, the pea density  of the series inductor is determined from the voltage across the in   in Figure 9, as given by where  is the winding turn number of the inductor.The peak flux densities  a must be kept below the saturation flux density  of the core material.

Design of the Transformer and Series Inductor
The MF transformer of the DAB DC-DC converter is a crucial element for transferring power and voltage conversion between the two DC sides.Meanwhile, the series inductor L a limits the maximum power transfer.MnZn ferrite and nanocrystalline materials are suitable for the switching frequency of 20 kHz used in this study.For this application, the battery voltage varies with the state of charge and battery current, while the bus voltage is kept constant.Thus, the maximum allowable phase shift angle is ±π/3 to exploit a large ZVS range at the rated power and achieve a fine battery current resolution, while the RMS values of the transformer currents are still acceptable.It was reported that nanocrystalline materials exhibited better power density and efficiency than MnZn ferrite material [10].However, the cutting process of ribbon-wound nanocrystalline cores deteriorated their magnetic properties [10].Hence, we selected N87 MnZn ferrite cores due to consistency in magnetic properties and market availability [29].This core material has a saturation flux density of 0.39 T at 100 • C and is available in various core shapes.
An analytical transformer and inductor design method was chosen in this study [30].The generalized Steinmetz equation expresses the core loss P f e as a function of the core peak flux density B. Meanwhile, the copper loss P cu is derived from the RMS values of the transformer's currents and the winding resistance.Therefore, the winding resistance is derived from the core geometry, which is expressed as a function of the core peak flux density B. Setting P f e = P cu leads to the optimal peak flux density Bopt , from which the minimum core size is obtained.An actual core size should be selected close to the optimal one.
The MF transformer and the inductor were designed at the nominal battery voltage V Bn of 51.2 V using the peak flux densities given in (24) and (25).The transformer turn ratio is close to The peak flux densities BT and BL calculated at the maximum battery voltage of 60 V were ensured to be below the core saturation value.The core loss coefficient was identified from the manufacturer's specification at the temperature of 100 • C. Enameled Litz wires were employed to minimize the skin and proximity effects from the switching frequency.The required value of L a obtained from (23) is 297 µH.However, the inductance of 280 µH was used in the design to account for the leakage inductance of the MF transformer.Table 3 summarizes the key parameters of the MF transformer and series inductor.The actual core sizes are slightly larger than the required sizes.Thus, the peak flux densities BT and BL are smaller than their optimal values.This results in the estimated core losses being comparatively less than the copper losses.The predicted core loss using the generalized Steinmetz equation is based on the sinusoidal induction waveform.Moreover, the N87 ferrite material has a more significant core loss at low temperatures.In experiments, the core temperature was found to be lower than 60 • C, which agrees with our previous work with the same design methodology and core material [10].Thus, the actual core losses are expected to exceed the predicted values.The phase shift angle δ = 0 is set at π/2 of each ISR period to sample the average value of the battery current i B (t).The reference phase angles δ * 1 and δ * 4 for switches S 1 and S 4 of the LV bridge and δ * 5 and δ * 8 for switches S 5 and S 8 of the HV bridge are obtained from where δ * is the reference phase shift angle.Figure 9 shows the implementation diagram of the battery current control.The battery current is sampled every T s .The discrete-time PI controller G CB (z) regulates the battery current i B (k) at instant k with the reference phase angle δ * (k) as the output.The reference angles δ * 1 (k), δ 4 (k), δ * 5 (k), and δ * 8 (k) are obtained from (27).The reference angles δ * 1 (k) and δ * 8 (k) are translated to the values of the CMPA3, CMPB3, CMPA6, and CMPB6 registers as depicted in Figure 11.Meanwhile, the reference angles δ 4 (k) and δ * 5 (k) are delayed with a sampling period to prevent a large DC offset current in the transformer current i p (t) during the transient [20].This method is to control the volt-second applied to the transformer to maintain a small DC offset.So, the values of CMPA4, CMPB4, CMPA5, and CMPB5 are accordingly determined from δ 4 (k − 1) and δ * 5 (k − 1).The action qualifier submodule of each module defines the action of the PWMxA output when the CMPAx and CMPBx registers meet their conditions as indicated by "set" and "clear" in the brackets.Meanwhile, the PWMxB outputs are opposite to their PWMxA outputs, with a dead time of 1.25 µs similar to that of the VSC [26].

Tuning of the Battery Current Control Loop
Figure 12 depicts the equivalent circuit on the battery side.The variables are averaged over a switching period of T sw , denoted by the brackets ⟨ ⟩.Equation (23) yields the average current ⟨i LVB ⟩ of the DAB DC-DC converter, while the battery is simplified with an open- circuit voltage ⟨e 0 ⟩ and an internal resistance R i .The Thevenin-based equivalent circuit consisting of internal series resistance and capacitance paralleled with another resistance is more accurate than that in Figure 12 [32].The Thevenin-based capacitance is much larger than the battery-side capacitance C B [33].From the control point of view, thus, the open-circuit voltage ⟨e 0 ⟩ in Figure 12 including the voltage drops in the Thevenin-based capacitance is the disturbance of the battery current control loop.Figure 13 depicts the equivalent block diagram of the battery current in the continuous time domain, where a PI regulator with the constants K pb and K ib controls the battery current.A delay of T d = 2T s represents the sampling and transport delays, as illustrated in Figure 10.The gain K DAB is derived from the possible maximum value of (23), as given by According to (23), this gain  decreases with the angle current.However, the approximated gain  at its maximum maintenance of loop stability at a high current.

𝐺 𝑠 𝐾
where the delay  is neglected as it usually is much smaller than t The closed-loop transfer function is given as

𝐺 𝑠
Compared to the standard second-order system [34],  and

𝐾 𝜔 𝐾
where  is the natural frequency, and  is the damping factor tem.If  is unknown, a trial-and-error tuning method can be ado for  and  for .
According to (23), this gain  decreases with the angle  for a higher battery current.However, the approximated gain  at its maximum value guarantees the maintenance of loop stability at a high current.The open loop transfer function of the battery current control loop is written as where the delay  is neglected as it usually is much smaller than the time constant   .The closed-loop transfer function is given as Compared to the standard second-order system [34],  and  can be written as where  is the natural frequency, and  is the damping factor of the closed-loop system.If  is unknown, a trial-and-error tuning method can be adopted by adjusting  for  and  for .According to (23), this gain K DAB decreases with the angle δ for a higher battery current.However, the approximated gain K DAB at its maximum value guarantees the maintenance of loop stability at a high current.
The open loop transfer function of the battery current control loop is written as where the delay T d is neglected as it usually is much smaller than the time constant R i C B .The closed-loop transfer function is given as Compared to the standard second-order system [34], K pb and K ib can be written as where ω 0 is the natural frequency, and ξ is the damping factor of the closed-loop system.If R i is unknown, a trial-and-error tuning method can be adopted by adjusting K ib for ω 2 0 and K pb for ξ.

Experimental Setup
Figure 14 depicts the experimental setup.A TMS320F280049C microcontroller controlled the VSC and DAB DC-DC converter with the parameters listed in Table 2.A switching dead time of 1.25 µs was applied to each leg of the VSC and DAB DC-DC con-verter.A 16-cell 100 Ah LFP battery pack supplied the DAB DC-DC converter, while the VSC was connected to a Chroma 61860 grid simulator.We adopted the tuning procedure of the VSC presented in our previous work [24] with a bus voltage bandwidth of 30π rad/s and the current harmonic controllers, orders 3rd, 5th, 7th, and 9th for mitigation of the grid current waveform.The bus voltage was regulated at 400 V.The response of the battery current was tuned by the trial-and-error method with the guidelines given in (31).The battery management system has a maximum current of 30 A, which, unfortunately, limits the maximum system power within ±1.5 kW or 50% of the rated power.

Experimental Setup
Figure 14 depicts the experimental setup.A TMS320F280049C microcontroller controlled the VSC and DAB DC-DC converter with the parameters listed in Table 2.A switching dead time of 1.25 µs was applied to each leg of the VSC and DAB DC-DC converter.A 16-cell 100 Ah LFP battery pack supplied the DAB DC-DC converter, while the VSC was connected to a Chroma 61860 grid simulator.We adopted the tuning procedure of the VSC presented in our previous work [24] with a bus voltage bandwidth of 30π rad/s and the current harmonic controllers, orders 3rd, 5th, 7th, and 9th for mitigation of the grid current waveform.The bus voltage was regulated at 400 V.The response of the battery current was tuned by the trial-and-error method with the guidelines given in (31).The battery management system has a maximum current of 30 A, which, unfortunately, limits the maximum system power within ±1.5 kW or 50% of the rated power.

Validation of the Dynamic DC Offset Compensation Scheme
The grid simulator supplied the VSC, and the bus voltage was regulated at 400 V.The DAB DC-DC converter operated with the reference phase angle  * in the open-loop control.Figure 15a

Validation of the Dynamic DC Offset Compensation Scheme
The grid simulator supplied the VSC, and the bus voltage was regulated at 400 V.The DAB DC-DC converter operated with the reference phase angle δ * in the open-loop control.Figure 15a depicts the transient response of the primary and secondary voltages v p (t) and v s (t), the transformer's primary current i p (t), and the inverted battery current −i B (t) under the step change of the reference angle δ * changing from zero to π/4.In contrast, Figure 15b shows those waveforms for the reference angle δ * changing from zero to −π/4.Without the dynamic DC offset compensation scheme shown in Figure 11, i p (t) exhibits a DC offset of approximately 30 A. This large current can cause saturation in the transformer core and may damage the switching devices.The DC offset compensation technique in Figure 11 is effective as the dynamic DC component of i p (t) is reduced significantly during the changes in the reference angle δ * .Meanwhile, the DC offset compensation scheme does not affect the steady waveform of i p (t).The first-order response of the battery current i B (t) agrees with the equivalent circuit in Figure 12.
Electronics 2024, 13, x FOR PEER REVIEW 16 of 20 compensation scheme does not affect the steady waveform of   .The first-order response of the battery current   agrees with the equivalent circuit in Figure 12.

Validation of the Closed-Loop Control of the Battery Current
The battery current control loop was tuned for a smooth response with a settling time of approximately 80 ms.The reference battery current  * was set to create the battery power in the range of ±1.5 kW. Figure 16 shows the experimental results in the discharging mode with a battery power of 1.5 kW.Although the discharged power from the battery causes the bus voltage to increase, the bus voltage controller forces the bus voltage to return to the reference of 400 V within four cycles, as shown in Figure 16a.Figure 16b depicts the steady-state waveforms of   ,   , and   .The grid current waveform is nearly sinusoidal thanks to the current harmonic current controller, which attenuates the harmonic components in the reference grid current and the VSC terminal voltage caused by the dead time.Figure 16c illustrates that a step change in the battery reference current  * does not create a DC offset in the transformer's primary current   , thanks to the DC offset compensation scheme implemented in the SPS modulation system in Figure 11.Meanwhile, the battery current   smoothly increases toward its reference.The steadystate waveforms of   ,   , and   in Figure 16d agree with the sketched waveforms in Figure 10.At this operating point, the battery voltage was 51.5 V, close to the designed value of the MF transformer.

Validation of the Closed-Loop Control of the Battery Current
The battery current control loop was tuned for a smooth response with a settling time of approximately 80 ms.The reference battery current i * B was set to create the battery power in the range of ±1.5 kW. Figure 16 shows the experimental results in the discharging mode with a battery power of 1.5 kW.Although the discharged power from the battery causes the bus voltage to increase, the bus voltage controller forces the bus voltage to return to the reference of 400 V within four cycles, as shown in Figure 16a.Figure 16b depicts the steady-state waveforms of v D (t), v g (t), and i g (t).The grid current waveform is nearly sinusoidal thanks to the current harmonic current controller, which attenuates the harmonic components in the reference grid current and the VSC terminal voltage caused by the dead time.Figure 16c illustrates that a step change in the battery reference current i * B does not create a DC offset in the transformer's primary current i p (t), thanks to the DC offset compensation scheme implemented in the SPS modulation system in Figure 11.Meanwhile, the battery current i B (t) smoothly increases toward its reference.The steadystate waveforms of v p (t), v s (t), and i p (t) in Figure 16d agree with the sketched waveforms in Figure 10.At this operating point, the battery voltage was 51.5 V, close to the designed value of the MF transformer.
Figure 17 shows the experimental results in the charging mode with a battery power of −1.5 kW.The bus voltage v D (t), grid current i g (t), transformer's primary current i p (t), and battery current i B (t) respond to the battery reference current i * B in the same fashion as the discharging mode with the opposite direction.The steady-state grid current waveform remains nearly sinusoidal.However, the steady-state waveform of i p (t) indicates that the DAB DC-DC converter operates in the boost mode, where N s /N p V B > V D [19].At this operating point, the battery voltage was 54.3 V, causing N s /N p V B = 424 V.
Figure 18 shows the battery voltage, total efficiency of the VSC and DAB DC-DC converter, and total harmonic distribution (THD i ) of grid current with battery power.As expected, the battery voltage in the charging mode is greater than that in the discharging mode.The inverter's efficiency in the charging mode is lower than in the discharging mode.Partly, it is believed to be due to the mismatched voltage ratio of the MF transformer, which deviates the operating point out of the ZVS region o and increases RMS values in the transformer currents [28].Thus, a variable DC voltage strategy with the battery voltage and a duty ratio adjustment of the transformer would improve the inverter's efficiency.The THDi values at 50% of the rated power are less than 1.5%, which are expected to be lower at the rated power of 3 kW.
Figure 17 shows the experimental results in the charging mode with a battery power of −1.5 kW.The bus voltage   , grid current   , transformer's primary current   , and battery current   respond to the battery reference current  * in the same fashion as the discharging mode with the opposite direction.The steady-state grid current waveform remains nearly sinusoidal.However, the steady-state waveform of   indicates that the DAB DC-DC converter operates in the boost mode, where   ⁄   [19].
At this operating point, the battery voltage was 54.3 V, causing   ⁄  424 V.
Figure 18 shows the battery voltage, total efficiency of the VSC and DAB DC-DC converter, and total harmonic distribution (THDi) of grid current with battery power.As expected, the battery voltage in the charging mode is greater than that in the discharging mode.The inverter's efficiency in the charging mode is lower than in the discharging mode.Partly, it is believed to be due to the mismatched voltage ratio of the MF transformer, which deviates the operating point out of the ZVS region o and increases RMS values in the transformer currents [28].Thus, a variable DC voltage strategy with the battery voltage and a duty ratio adjustment of the transformer would improve the inverter's efficiency.The THDi values at 50% of the rated power are less than 1.5%, which are expected to be lower at the rated power of 3 kW.

Conclusions and Future Outlook
A single-phase grid-connected 51.2-V battery inverter consisting of an LCL-filtered voltage source converter (VSC) and a dual active bridge (DAB) DC-DC converter was constructed.The control systems of the two converters were implemented in the same interrupt service routine on a TMS320F280049C microprocessor with a sampling and switching frequency of 20 kHz-the time base counters for switching generation of the DAB DC-DC converter synchronized with those of the VSC.The single-phase shift modulation strategy of the DAB DC-DC converter was adjusted through two separate compare registers with the time base counters during the count-up and count-down periods.This phase shift modulation was easy to implement on a standard microcontroller for power converter control.A DC offset compensation integrated with the battery current control loop allowed a smooth change in the battery and medium-frequency transformer's currents in response to a reference current step.The VSC adopted a bus voltage control with a unified harmonic mitigation strategy.Experimental validations in the charge and discharge operations exhibited a total system efficiency better than 90% and total harmonic distortion in the grid current lower than 1.5%.
However, certain aspects must be studied further to improve the proposed residential battery inverter as follows: (1) Adoption of advanced battery current control schemes regardless of the battery's internal impedance parameters.(2) Increasing the switching frequency and improving the modulation strategies of the DAB DC-DC converter to enhance efficiency and power density.(3) Optimizing the design of the ripple filter on the battery side.
Funding: This research was partially supported by the Royal Golden Jubilee Ph.D. Program, grant number PHD02282560, and the Global and Frontier Research University Fund, Naresuan University, grant number R2567C002.

Figure 1 .
Figure 1.DC coupling grid-connected PV-battery hybrid inverters: (a) direct connection of the HV battery to the DC bus; (b) HV battery connected to the DC bus via a non-isolated DC-DC converter; (c) LV battery connected to the DC bus via an isolated DC-DC converter.

Figure 1 .
Figure 1.DC coupling grid-connected PV-battery hybrid inverters: (a) direct connection of the HV battery to the DC bus; (b) HV battery connected to the DC bus via a non-isolated DC-DC converter; (c) LV battery connected to the DC bus via an isolated DC-DC converter.

Figure 1 .
Figure 1.DC coupling grid-connected PV-battery hybrid inverters: (a) direct connection of the HV battery to the DC bus; (b) HV battery connected to the DC bus via a non-isolated DC-DC converter; (c) LV battery connected to the DC bus via an isolated DC-DC converter.

Figure 3 .
Figure 3. Circuit diagram and its simplified control system of the inverter in this study.

Figure 3 .
Figure 3. Circuit diagram and its simplified control system of the inverter in this study.

Figure 4 .
Figure 4. Bust voltage and grid current control block diagram of the VSC.

Figure 5
Figure 5 depicts the stationary reference frame's equivalent grid current control block diagram.The VSC is represented by

Figure 4 .
Figure 4. Bust voltage and grid current control block diagram of the VSC.Electronics 2024, 13, x FOR PEER REVIEW 8 of 20

Figure 5 .
Figure 5.The stationary reference frame's equivalent control block diagram of the grid current in the stationary reference frame.

Figure 6 .
Figure 6.Equivalent control block diagram of the bus voltage.

Figure 5 .
Figure 5.The stationary reference frame's equivalent control block diagram of the grid current in the stationary reference frame.

Figure 5 .
Figure 5.The stationary reference frame's equivalent control block diagram of the grid current in the stationary reference frame.

Figure 6 .
Figure 6.Equivalent control block diagram of the bus voltage.

Figure 6 .
Figure 6.Equivalent control block diagram of the bus voltage.

Figure 7 .
Figure 7. Discontinuous PWM block diagram for the VSC.

Figure 7 .
Figure 7. Discontinuous PWM block diagram for the VSC.

Figure 8 . 4 .Figure 9 1 | | ( 22 )
Figure 8. Timing diagram for interrupts, PWM generation, and analog signal samplings of the VSC: (a) for  *  0; (b) for  *  0. 4. Implementation of the Battery-Side DAB DC-DC Converter 4.1.Basic Operation of the DAB DC-DC Converter Figure 9 illustrates the basic operation waveforms of the DAB DC-DC converter in the SPS modulation mode, where  2 and   .The voltage   of the LV bridge leads the voltage   of the HV bridge by a phase angle of , which causes power to flow from the battery to the bus voltage.On the other hand, power transfers from the bus voltage to the battery with a phase angle of .Thus, the transferred power  of the DAB DC-DC converter is controlled by the angle  by

Figure 8 .
Figure 8. Timing diagram for interrupts, PWM generation, and analog signal samplings of the VSC: (a) for m * (t) ≥ 0; (b) for m * (t) < 0.4.Implementation of the Battery-Side DAB DC-DC Converter 4.1.Basic Operation of the DAB DC-DC Converter Figure 9 the basic operation waveforms of the DAB DC-DC converter in the SPS modulation mode, where ω sw = 2π f sw and θ sw = ω sw t.The voltage v P (θ sw ) of the LV bridge leads the voltage v s (θ sw ) of the HV bridge by a phase angle of δ, which causes power to flow from the battery to the bus voltage.On the other hand, power transfers from the bus voltage to the battery with a phase angle of −δ.Thus, the transferred power P DAB of the DAB DC-DC converter is controlled by the angle δ by

Figure 9 .
Figure 9. Voltage, current, and flux density waveforms of the DAB DC-DC converter with the SPS modulation strategy [28].

Figure 10
Figure 10 sketches the steady state timing diagram of the DAB DC-DC converter, implemented in the same ISR as the VSC control scheme in Figure 8. Counters 3-6 in the up-down mode generate the switching signals for the DAB DC-DC converter.The phase angles of counters 3-6 are synchronized with counter 1.Instead, the phase shift modulation is obtained by adjusting the CMPA3 to CMPA6 and the CMPB3 to CMPB6 registers of counters 3-6 [31].During the rising period of counters 3-6, switches S 1 , S 4 , S 5 , and S 8 are turned on when the values of the counters equal their CMPAs registers.For the falling period, switches S 1 , S 4 , S 5 , and S 8 are turned off when the values of the counters equal their CMPBs registers.Thus, this modulation strategy accommodates the maximum phase shift angle of ±π/2.Note that switches S 2 , S 3 , S 6 , and S 7 complement switches S 1 , S 4 , S 5 , and S 8 respectively.Electronics 2024, 13, x FOR PEER REVIEW 13 of 20

Figure 10 .
Figure 10.Steady-state timing diagram for the DAB DC-DC converter: (a) for i B (t) ≥ 0 (b) for i B (t) < 0.

Figure 11 .
Figure 11.Implementation diagram of the battery current control loop of the DAB DC-DC converter.

Figure 12 Figure 11 .
Figure 12 depicts the equivalent circuit on the battery side.The variables are averaged over a switching period of  , denoted by the brackets 〈 〉.Equation (23) yields the average current 〈 〉 of the DAB DC-DC converter, while the battery is simplified with an open-circuit voltage 〈 〉 and an internal resistance  .The Thevenin-based equivalent

Figure 12 .
Figure 12.Equivalent circuit on the battery side.

Figure 13 .
Figure 13.Equivalent control block diagram of the battery current.

Figure 12 .
Figure 12.Equivalent circuit on the battery side.

Figure 12 .
Figure 12.Equivalent circuit on the battery side.

Figure 13 .
Figure 13.Equivalent control block diagram of the battery current.

Figure 13 .
Figure 13.Equivalent control block diagram of the battery current.
depicts the transient response of the primary and secondary voltages   and   , the transformer's primary current   , and the inverted battery current   under the step change of the reference angle  * changing from zero to π/4.In contrast, Figure 15b shows those waveforms for the reference angle  * changing from zero to −π/4.Without the dynamic DC offset compensation scheme shown in Figure 11,   exhibits a DC offset of approximately 30 A. This large current can cause saturation in the transformer core and may damage the switching devices.The DC offset compensation technique in Figure 11 is effective as the dynamic DC component of   is reduced significantly during the changes in the reference angle  * .Meanwhile, the DC offset

Figure 15 .
Figure 15.Open-loop transient response of the DAB DC-DC converter with and without the dynamic DC offset compensation scheme: (a)  * changing from 0 to π/4; (b)  * changing from 0 toπ/4.

Figure 16 .
Figure 16.Experimental results of the closed-loop control of the battery current in the discharging mode with the battery power of 1.5 kW: (a) transient response of the bus voltage   , grid voltage   , and grid current   ; (b) steady-state waveforms of the bus voltage   , grid voltage   , and grid current   ; (c) transient response of the primary and secondary voltages   and   , the transformer's inverted primary current   , and the inverted battery current   ; (d) steady-state waveforms of the primary and secondary voltages   and   , the transformer's inverted primary current   , and the inverted battery current   .

Figure 16 .
Figure 16.Experimental results of the closed-loop control of the battery current in the discharging mode with the battery power of 1.5 kW: (a) transient response of the bus voltage v D (t), grid voltage v g (t), and grid current i g (t); (b) steady-state waveforms of the bus voltage v D (t), grid voltage v g (t),and grid current i g (t); (c) transient response of the primary and secondary voltages v p (t) and v s (t), the transformer's inverted primary current −i p (t), and the inverted battery current −i B (t); (d) steadystate waveforms of the primary and secondary voltages v p (t) and v s (t), the transformer's inverted primary current −i p (t), and the inverted battery current −i B (t).

Figure 17 .
Figure 17.Experimental results of the closed-loop control of the battery current in the charging mode with the battery power of −1.5 kW: (a) transient response of the bus voltage   , grid voltage   , and grid current   ; (b) steady-state waveforms of the bus voltage   , grid voltage   , and grid current   ; (c) transient response of the primary and secondary voltages   and   , the transformer's inverted primary current   , and the inverted battery current   ; (d) steady state waveforms of the primary and secondary voltages   and   , the transformer's inverted primary current   , and the inverted battery current   .

Figure 18 .
Figure 18.(a) Battery voltage  with battery power; (b) inverter's efficiency with battery power; (c) total harmonic distortion of grid current with battery power.

Figure 17 . 20 Figure 17 .
Figure 17.Experimental results of the closed-loop control of the battery current in the charging mode with the battery power of −1.5 kW: (a) transient response of the bus voltage v D (t), grid voltage v g (t), and grid current i g (t); (b) steady-state waveforms of the bus voltage v D (t), grid voltage v g (t), and grid current i g (t); (c) transient response of the primary and secondary voltages v p (t) and v s (t), the transformer's inverted primary current −i p (t), and the inverted battery current −i B (t); (d) steady state waveforms of the primary and secondary voltages v p (t) and v s (t), the transformer's inverted primary current −i p (t), and the inverted battery current −i B (t).

Figure 18 .
Figure 18.(a) Battery voltage  with battery power; (b) inverter's efficiency with battery power; (c) total harmonic distortion of grid current with battery power.

Figure 18 .
Figure 18.(a) Battery voltage V B with battery power; (b) inverter's efficiency with battery power; (c) total harmonic distortion of grid current with battery power.

Table 1 .
Specification of the battery inverter.

Table 2 .
Parameters of the battery inverter.

Table 1 .
Specification of the battery inverter.

Table 2 .
Parameters of the battery inverter.

Table 3 .
Parameters of the MF transformer and series inductor.