Generalization of Split DC Link Voltages Behavior in Three-Phase-Level Converters Operating with Arbitrary Power Factor with Restricted Zero-Sequence Component

: This article examines the impact of a power factor on the behavior of partial DC link voltages in three-phase three-level AC/DC (or DC/AC) converters operating without additional balancing hardware. We consider the case in which the controller utilizes a bandwidth-restricted (DC in steady state) zero-sequence component to achieve average partial DC link voltage equalization since the injection of high-order zero-sequence components is impossible or forbidden. An assessment of partial split DC-link capacitor voltage behavior (particularly that of ripple magnitudes and phases) is necessary for, e.g., minimizing the values of DC link capacitances and selecting reference voltage values. Previous studies assessed the abovementioned behavior analytically for operation under a unity power factor based on third-harmonic-dominated split partial voltages’ ripple nature. However, it is shown here that deviation from the unity power factor introduces additional (to the third harmonic) non-negligible harmonic content, increasing partial voltage ripple magnitudes and shifting their phase (relative to the mains voltages). As a result, the third-harmonic-only assumption is no longer valid, and it is then nearly impossible to derive corresponding analytical expressions. Consequently, a numerical approach is used in this work to derive a generalized expression of normalized ripple energy as a function of the power factor, which can then easily be utilized for assessments of split DC link voltage behaviors for certain DC link capacitances and reference voltages. Simulations and experimental results validate the proposed methodology applied to a 10 kVA T-type converter prototype


Introduction
With the increasing demand for high-power AC/DC and DC/AC converters in modern energy systems, the use of controlled multilevel converters is becoming more common [1].Multilevel converters offer several advantages over traditional two-level converters, including improved efficiency, reduced dv/dt, and lower total harmonic distortion of the output voltage [2].Common topologies of multilevel converters include cascaded H-bridge, flying capacitor and neutral point clamped [3].
Multilevel converters play a significant role in dual-stage power conversion systems that use an intermediate DC voltage link [4][5][6][7][8][9].In such systems, the DC link is usually implemented using a single capacitor in the case of two-level conversion or multiple split capacitors in the case of multi-level conversion [10,11].This arrangement provides power decoupling between phases, and allows for independent control of AC/DC and DC/AC converters using different methods of pulse width modulation (PWM) [12][13][14][15][16][17][18].The size, weight and cost of the DC-link capacitor depend on the DC link voltage reference value and power conversion system rating [19].In addition, capacitors' limited lifetime affects the overall system reliability [20].Hence, it is desirable to reduce both DC link voltage reference and capacitance values [21][22][23].
Among the various topologies, three-phase AC/DC and three-phase DC/AC converters have emerged as a viable choice for power ratings ranging from 10 kVA to 100 kVA and have found widespread use in industrial applications [24].The efficiency, reliability and quality of output waveforms in three-level converters are significantly affected by the PWM method employed [25].In carrier-based PWM, the main distinction between PWM methods lies in the injection of a zero-sequence voltage to balance the DC link split capacitance voltages [26].While other dedicated hardware solutions exist for split capacitance balancing [27,28], they lead to increase in system cost and physical size.Alternatively, various methods of zero-sequence injection have been proposed over the years, with the aim of balancing the average values or the instantaneous values of the split DC link voltages [29][30][31][32][33].This paper addresses the group of cases in which the harmonic content of the zero-sequence component is limited to the DC constituent only (due to, e.g., four-wire converter implementation or strict leakage current restraint).Such a limitation leads to a significant steady-state voltage ripple across split DC link capacitors, requiring the careful selection of both capacitance values and corresponding voltage set points.Previous studies evaluated these fluctuations using complex and non-analytical neutral point expressions [34,35].Another study proposed a methodology based on instantaneous split DC coupling forces, which allows for an analytical and intuitive quantification of corresponding voltage fluctuations [36].However, these methodologies were developed for the unity power factor only and do not account for arbitrary power factor operation.
While this paper mainly focuses on low-frequency oscillations and the influence of the power factor, frequency-related components are omitted for brevity in the present discussion and can be found in [35,37].It is found that, under balanced operation on the AC side with any power factor, total DC link voltage remains free of low-frequency oscillations.However, split DC-link capacitors absorb power components at the triple fundamental frequency of a magnitude equivalent to one-sixth the load power affected by the power factor, resulting in out-of-phase voltage fluctuations.Reference [38] asserts that the power factor does not impact the split link capacitor ripple voltages.However, this article presents analytical expressions that contradict this claim, demonstrating that the power factor does influence the harmonic content of the capacitor voltages.Particular emphasis is placed on the third harmonic, which is the most dominant component in the evaluation.The specialized expressions are validated through simulations and experiments, providing comprehensive insights into the effect of the power factor on the behavior of the capacitor voltages.Consequently, the selection of DC link capacitors and voltage set points must consider the expected magnitudes of the AC-side phase voltages, the power factor, as well as the voltage and current ratings of the split DC link capacitors.In [39], the authors demonstrated a method to minimize the capacitance values of split DC capacitors in three-phase three-level converters, but the analysis was restricted to a unity power factor scenario.However, when the power factor deviates from unity, the above-presented analysis becomes invalid, necessitating the results presented in this paper to extend the findings in [39].The present study is essential in providing insights and solutions for cases where the power factor is different from unity, thereby complementing and broadening the applicability of the results in [39].
The results of the proposed split DC link capacitor voltage evaluation can serve as a baseline for the evaluation of advanced high-order zero-sequence injection algorithms aiming to reduce low-frequency neutral voltage fluctuations and minimize the utilization of split DC link capacitors.The validity of the presented findings is strongly supported by simulations and experiments.

Steady-State Operation of a Generalized Three-Phase Three-Level AC/DC Converter
Figure 1 presents a typical three-phase dual-stage AC-DC power conversion system, comprising a three-level AC/DC (or DC/AC) converter, a DC link, and a DC/DC converter.It is important to emphasize that the direction of energy flow can be either from the AC side (R, S, T terminals) to the DC side (W, Z terminals) or vice versa, i.e., the "Load" signifies a power source when the energy flows from the DC side to AC side.In the case of threelevel conversion, the DC link is formed by three terminals (X, O, Y).During balanced operation, AC-side steady-state quantities (all discussed signals are subsequently averaged over a switching cycle) are given by with = 2 3 ⁄ , VM and IM representing voltage and current magnitudes, respectively, ω symbolizing base frequency, and denoting an arbitrary phase.
created by the controller shown in Figure 1, with and M(t), m0(t) denoting modulation index and zero-sequence component, respectively.It is considered in this paper that m0(t) contains the DC component only in steady state (allowing for an average values equalization of split DC link voltages), while in other designs it may contain both DC and high-order AC components (allowing for the equalization of split DC link voltages' instantaneous values).It should be emphasized that m0(t) may also be supplied by additional hardware-based equalization circuits [27,28].
Considering (1), the instantaneous AC-side phase power vector is given by Hence, total instantaneous AC-side power is ripple-free, given by On the other hand, assuming load-side voltage and current are governed by ( ) , ( ) , the corresponding steady-state instantaneous power is also constant, given by ( ) ( ) ( ) .
Consequently, instantaneous system power balance (neglecting the conversion losses and energy stored in AC-side L, LC or LCL type filters [37,40] cf. Figure 2) is given by cos , indicating that the instantaneous low-frequency power flow into the DC link in Figure 1   Since grid AC-side voltages ⃗ and currents ⃗ in Figure 2 cannot contain zero-sequence components (even for nonzero m0), corresponding power vectors are given by (4).On the other hand, converter-imposed AC-side voltages ⃗ = ( ) would contain DC components in case the corresponding modulation signals are DC-shifted, with v0 denoting the shift imposed by m0.Consequently, (cf. Figure 2) with P0/3 denoting DC power component imposed by m0.Therefore, the low-frequency partial power components exchanged between the AC side of the converter and the DC link of the converter (again, without considering conversion losses and energy stored in AC-side filters) can be expressed as with pAC denoting the zero-average pulsating power component and ΔpL representing load power mismatch.Note that P0 may be either positive, negative or zero, compensating for instantaneous energy shortages in one or both split DC link capacitors.Obviously, instantaneous system power balance ( 8) is sustained with P0 = ΔpL and partial low-frequency DC link power components are given in steady state by In the case where partial capacitor voltages vDC1 and vDC2 are regulated to set points given by * and * , respectively, the corresponding instantaneous low-frequency energies eDC1 and eDC2 and steady-state voltages are , respectively.Typically, are employed, with * denoting overall DC link voltage reference value, so that 2 max ( , ) 2 1 0.5 1 ( , ) 0.5 ( , ) , 1 0.5 0.5 0.5 i.e., split capacitor voltages contain DC components as well as the nonzero opposite-phase AC voltage ripples.The approximation in (15) is valid in practical systems where the AC ripple magnitude is much lower than the DC component [42].As a result, each instantaneous partial DC link capacitor's voltage is bounded by so that ( , ) ( , ) cos .
Likewise, assuming P0 = ΔpL, there is Lastly, normalized pulsating energy swing magnitude is obtained as Figure 3 illustrates the resulting normalized waveforms, with Figure 3a-c corresponding to individual phase voltages, currents and instantaneous power components as well as total AC-side power (cf.18), ( 19)). Figure 3d     It is well-evident that operating power factor considerably influences the harmonic content of normalized partial DC-side powers.It is interesting to note that, upon a decrease in power factor, the first harmonic magnitude reduces while the rest of the harmonic magnitudes inrease.As shown in [36,39] (and evident from Figure 4), normalized partial upper DC-side power components , , are given by Consequently, cf. ( , with corresponding spectra depicted in Figure 5 for different values of φ.It is again evident that operating power factor significantly influences the harmonic content of the normalized partial pulsating power component .Moreover, it is obvious that the third harmonic dominates the spectra.Consequently, (24) may be approximated as   so that normalized pulsating energy swing magnitude is obtained as (cf.( 22))
Combining this with (15), the partial DC link voltage ripple component is given by Contrary to the statement in [38], it turns out that the power factor influences both the amplitude ΔV and the phase α3 of the partial DC link voltage ripple component.It is important to emphasize that the normalized pulsating energy swing magnitude (27) and the phase α3 are generalized quantities that are valid for a given mains frequency ω, irrespective of system rated power, partial DC link capacitance values and corresponding voltage set points.Unfor-tunately, it is nearly impossible to obtain an analytical expression for both quantities.Consequently, multiple numerical simulations are carried out for different operating power factor values under 50 Hz mains frequency to evaluate the two parameters.Subsequently, polynomial approximations were derived based on the results, as shown in Figure 6.The following generalized expressions are obtained:  The obtained numerical expressions can be readily adapted to any system through a straightforward calculation of the DC link voltage ripple amplitude cf.(29).The inherent generality and adaptability of the expression makes it applicable across various systems, facilitating efficient evaluations and comparisons in different practical scenarios.It is important to note that, in case of operation under 60 Hz mains frequency, the first polynomial in (30) (magnitude) should be multiplied by 5/6 due to the frequency dependence in (27) while the second one (phase) should be left unchanged.

Validation
In order to validate the proposed methodology, a 10 kVA LCL-filter-based, threephase, three-level, T-type converter, as shown in Figure 7a is employed.A corresponding experimental prototype, based on design guidelines given in [41], is shown in Figure 7b      Figure 12 presents a comparison between the simulations, experimental results and corresponding analytical predictions.A near-perfect match between simulation results and analytical predictions is obvious, supporting the presented methodology.On the other hand, some deviations are visible between experiments and simulations/analytical predictions.These may be explained by voltage drops across capacitor ESRs, which were neglected in simulations and during theoretical modeling.In order to support this assumption, the ESR of electrolytic capacitors was included in simulations.Corresponding results are shown in Figure 12 as "Simulation (ESR)".It is evident that the modified simulation model outcomes accurately coincide with the experimental results, supporting the above assumption.

Conclusions
The article presents an evaluation of the impact of power factor on the ripple voltage of split DC link capacitors in three-phase three-level converters.The results indicate that deviations from the unity power factor leads to an increase in the amplitude of harmonic content and a phase shift.Due to the fact that the non-unity power factor gives rise to rich harmonic content, analytical expression derivations are non-feasible.As a result, a numerical analysis was carried out to obtain generalized relations of normalized pulsating energy magnitude and phase with the operating power factor.The obtained numerical expressions can be readily adapted to any system through a straightforward calculation of partial DC link voltages' ripple amplitude and phase.Simulations and experiments carried out by applying the proposed methodology to a 10 kVA T-type converter successfully validated the revealed findings.
is zero.Considering the AC/DC converter belonging to generalized three-level three-phase topology shown in Figure2, two split capacitors, CDC1 and CDC2, form the DC link.According to the above, pDC = pDC1 + pDC2 = PRST + PL = 0; hence, vDC is low-frequency-ripple-free without implying zero pDC1, pDC2 and low-frequency-ripple-free vDC1, vDC2, as shown next.Note that the line connecting the middle point of DC link with that of the load middle point in Figure1is virtual and may be non-existent in reality.It is only used to demonstrate that the power element pL may be split into two halves[41].

6 ⁄
Figure3illustrates the resulting normalized waveforms, with Figure3a-c corresponding to individual phase voltages, currents and instantaneous power components as well as total AC-side power (cf.18), (19)).Figure3dpresents normalized partial DC-side power components cf.(20) (upper ones only are shown for brevity), each possessing average value of 6 ⁄ = cosφ/6.The corresponding total upper partial DC-side power cf.

( 21 ) 2 ⁄
is depicted in Figure3e, possessing an average value of = cosφ/2.Subtracting the average value from the total upper partial DC-side power yields a normalized partial pulsating power component , shown in Figure3f.Lastly, the normalized pulsating energy component obtained by integrating is depicted in Figure3gwith normalizing pulsating energy swing magnitude shown in the same subplot.

Figure 5 .
Figure 5. Spectra of normalized partial pulsating power component .

Figure 6 .
Figure 6.Magnitude (top) and phase (bottom) of pulsating energy component versus cos .
. The converter was operated at 50 kHz switching frequency using the Texas Instruments TMS320F28335 DSP [43].The power stage was supplied from an 800 V DC power source and connected to a three-phase balanced load.Partial DC link capacitances of 440 μF, possessing equivalent series resistances (ESR) of 0.5 Ohm, were used [44].Pulse-width modulation signals (2) with M = 325/400 were applied to operate the power stage in a semi-openloop, feeding the load with a balanced three-phase 50 Hz, 400 V supply.The value of m0(t) was generated in closed-loop fashion, as shown in Figure 8, where NF150 represents a 150 Hz-tuned notch filter aiming to remove the triple-mains-frequency ripple, with K0 denoting a constant gain [38].Three experiments were performed under the rated loading, operating with different power factors, accompanied by matching PSIM software simulations.Corresponding results are shown in Figures 9-11 (only one phase current and voltage are shown experimentally, due to four-channel oscilloscope usage, along with partial DC link voltage ripples).

Figure 12 .
Figure 12.Comparison between simulations, experimental results and corresponding analytical predictions. 3