Highly Efﬁcient GaN Doherty Power Ampliﬁer for N78 Sub-6 GHz Band 5G Applications

: In this paper, a high-efﬁciency GaN Doherty power ampliﬁer (DPA) for 5G applications in the N78 sub-6 GHz band is introduced. The theoretical analysis of the matching networks for the peak and carrier transistors is presented, with a focus on the impact of unequal power splitting for both transistors and the recommendation of a post-harmonic suppression network. The proposed design features an unequal Wilkinson power divider at the input and a post-harmonic suppression network at the output, both of which are crucial for achieving high efﬁciency. The Doherty power ampliﬁer comprises two GaN 10 W HEMTs, measured across the 3.3 GHz to 3.8 GHz band (the N78 band), and the results reveal signiﬁcant improvements in gain, output power, drain efﬁ-ciency, and power-added efﬁciency. Speciﬁcally, the proposed design achieved a power gain of over 12 dB and 42 dBm saturated output power. It also achieved a drain efﬁciency of 80% at saturation and a power-added efﬁciency of 75.2%. Furthermore, the proposed harmonic suppression network effectively attenuated the harmonics at the output of the ampliﬁer from the second to the fourth order to more than − 50 dB, thus enhancing the device’s linearity.


Introduction
The demand for high-performance RF power amplifiers (PAs) has surged with the advent of 5G wireless communication networks.These PAs play a pivotal role in ensuring seamless signal transmission, making them critical components in bridging the gap between transmitters and receivers.Many applications depend mainly on PAs as detection systems [1], hyperthermia therapy system [2,3], and wireless communications networks [4].Some of the most important wireless communication networks are the 5G networks.As 5G networks continue to expand, particularly with the deployment of small cell networks, the management of power consumption and heat dissipation in wireless base stations poses significant challenges for system designers.The exponential growth in data rates and the increasing complexity of modulation schemes, such as 4096 Quadrature Amplitude Modulation, mandate PAs that are not only highly efficient but also capable of handling high peak-to-average power ratios (PAPR).The integration of multiple-input multiple-output

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Proposed a design for a high-efficiency GaN Doherty power amplifier tailored to the N78 sub-6 GHz band, the most widely used band in active 5G NR networks.

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Significantly improved PAE by 27% through the incorporation of a 2.5:1 unequal Wilkinson power divider at the amplifier's input, in contrast to using an equal Wilkinson divider.

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Introduced a seventh-order post-harmonic suppression network that effectively suppressed harmonics from the second to the fourth order to more than −50 dB, enhancing linearity and PAE.

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Achieved a gain of 12 dB, an output power of 42 dBm, a drain efficiency of 80%, and a power-added efficiency of 75.2% in the proposed DPA design.

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Validated the simulation results by fabricating and measuring both the power divider and the harmonic suppression network, showing good agreement.

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The paper serves as a valuable reference for future studies in the field and paves the way for further enhancements and optimizations in RF PA designs for 5G applications.
Overall, the paper offers a comprehensive and innovative approach to achieving high efficiency in GaN DPAs, addressing the specific requirements of 5G applications in the N78 band.Its findings contribute to the ongoing development of advanced RF technologies for enhanced connectivity and performance in the 5G era.
The paper is structured as follows: In Section 2, a revision of the Doherty technique to improve efficiency was performed.The basic structure and advantages of the Doherty technique and how to calculate the output power, gain, linearity, and efficiency of that technique are discussed.In Section 3, all parts of the proposed DPA design are presented, including the design of the unequal Wilkinson power divider and the harmonic suppression network.The expected performance of DPA as a function of both frequency and input power is presented and discussed in detail in Section 4, in addition to the review and discussion of simulation results and comparison of this work with the literature.Finally, Section 5 summarizes the conclusions drawn from this research.

Doherty Power Amplifier
The Doherty power amplifier (DPA), conceived by W.H. Doherty in 1936 [27], is designed for highly efficient linear power amplification.In Figure 1, we present the schematic of our proposed DPA, emphasizing its key components.This configuration includes two amplifiers, the main class AB amplifier (carrier) and the auxiliary class C amplifier (peak).Two λ/4 transmission lines are integrated for phase correction and impedance translation, along with active load impedance modulation.
Electronics 2023, 12, x FOR PEER REVIEW 3 of 22 The paper is structured as follows: In Section 2, a revision of the Doherty technique to improve efficiency was performed.The basic structure and advantages of the Doherty technique and how to calculate the output power, gain, linearity, and efficiency of that technique are discussed.In Section 3, all parts of the proposed DPA design are presented, including the design of the unequal Wilkinson power divider and the harmonic suppression network.The expected performance of DPA as a function of both frequency and input power is presented and discussed in detail in Section 4, in addition to the review and discussion of simulation results and comparison of this work with the literature.Finally, Section 5 summarizes the conclusions drawn from this research.

Doherty Power Amplifier
The Doherty power amplifier (DPA), conceived by W.H. Doherty in 1936 [27], is designed for highly efficient linear power amplification.In Figure 1, we present the schematic of our proposed DPA, emphasizing its key components.This configuration includes two amplifiers, the main class AB amplifier (carrier) and the auxiliary class C amplifier (peak).Two λ/4 transmission lines are integrated for phase correction and impedance translation, along with active load impedance modulation.In practical terms, the main amplifier efficiently handles low input power, achieving peak efficiency and voltage levels.However, when it reaches the breakpoint threshold, as depicted in Figure 2, the auxiliary amplifier dynamically adjusts the load and amplifies output power while maintaining high voltage levels and efficiency.According to theoretical considerations [10], the DE at the breakpoint is expected to be equivalent to the efficiency at saturation and remain consistently high across the entire Doherty region.However, the presence of parasitic components within the transistors and the knee voltage effect, which leads to a gradual and smoother activation of the auxiliary transistor, results in a decrease in the efficiency profile within the Doherty region.Consequently, the efficiency achievable in practical applications at the breakpoint is typically lower than the efficiency observed under the saturation point, as demonstrated in Figure 2.
The DPA's performance factors include output power, gain, linearity, and efficiency.Drain efficiency (DE or η) is defined as: where  and  are output DC power provided by the PA,  and  are output voltage and current at the fundamental frequency, and  ,  , and  ,  , are the DC power of the main and peak PA, respectively.Power-added efficiency (PAE) is another efficiency indicator defined as: In practical terms, the main amplifier efficiently handles low input power, achieving peak efficiency and voltage levels.However, when it reaches the breakpoint threshold, as depicted in Figure 2, the auxiliary amplifier dynamically adjusts the load and amplifies output power while maintaining high voltage levels and efficiency.According to theoretical considerations [10], the DE at the breakpoint is expected to be equivalent to the efficiency at saturation and remain consistently high across the entire Doherty region.However, the presence of parasitic components within the transistors and the knee voltage effect, which leads to a gradual and smoother activation of the auxiliary transistor, results in a decrease in the efficiency profile within the Doherty region.Consequently, the efficiency achievable in practical applications at the breakpoint is typically lower than the efficiency observed under the saturation point, as demonstrated in Figure 2.
Gain (G) is calculated as:

Design of Wilkinson Power Divider
Reference [23] indicates that the small-signal gain decreases by 3 dB when the auxiliary amplifier splits an input signal into two equal-phase output signals using a Wilkinson The DPA's performance factors include output power, gain, linearity, and efficiency.Drain efficiency (DE or η) is defined as: where P out and P DC are output DC power provided by the PA, V out and I out are output voltage and current at the fundamental frequency, and V dc,main I dc,main and V dc,peak I dc,peak are the DC power of the main and peak PA, respectively.Power-added efficiency (PAE) is another efficiency indicator defined as: Gain (G) is calculated as:

Design of Wilkinson Power Divider
Reference [23] indicates that the small-signal gain decreases by 3 dB when the auxiliary amplifier splits an input signal into two equal-phase output signals using a Wilkinson power divider (Figure 3).This power divider equally splits the input power (port 1) into two equal-phase output signals (port 2 and port 3), maintaining matched states and offering isolation between the output ports.The formulas below demonstrate how to calculate the Wilkinson power divider parameters [27][28][29][30][31][32][33][34][35][36][37][38][39][40][41]: Z 2 = Z 0 1 + P main P peak 0.5 where Z 0 represents the normalized impedance (typically 50 Ω), R w is the isolation resistance, and P main and P peak represent the output power of the main branch (port 2) and the auxiliary branch (port 3), respectively.
In our design, we implemented Wilkinson's power divider with an unequal split to send more power to the main amplifier, resulting in a significant gain increase while reducing the auxiliary amplifier's power demand, allowing it to operate at a less deep class-C level.By adjusting the division factor (Q) value, defined as Q = P main /P peak , the power distribution between ports 2 and 3 can be altered.Table 1 displays branch impedances ( ,  ,  , and  ) and isolation resistance ( ) with varying division factor (Q) values.The values were obtained through simulations with ADS software, adjusting the division factor to achieve the desired power division ratio.It is important to note that these values depend on the specific design and substrate properties, and may vary based on the actual power divider design.The optimal division factor (Q) for our proposed circuit was determined as 2.5 after considering critical factors, gain, and PAE, as shown in Figure 4.The diagram in Figure 5 illustrates the layout and the simulated performance of the unequal Wilkinson power divider.Return loss was below −17 dB over the entire band (3.3-3.8GHz).The isolated port was connected to allow for the insertion of an external resistor.Table 1 displays branch impedances (Z 1 , Z 2 , Z 3 , and Z 4 ) and isolation resistance (R w ) with varying division factor (Q) values.The values were obtained through simulations with ADS software, adjusting the division factor to achieve the desired power division ratio.It is important to note that these values depend on the specific design and substrate properties, and may vary based on the actual power divider design.The optimal division factor (Q) for our proposed circuit was determined as 2.5 after considering critical factors, gain, and PAE, as shown in Figure 4.  Table 1 displays branch impedances ( ,  ,  , and  ) and isolation resistance ( with varying division factor (Q) values.The values were obtained through simulations with ADS software, adjusting the division factor to achieve the desired power division ratio.It is important to note that these values depend on the specific design and substrate properties, and may vary based on the actual power divider design.The optimal division factor (Q) for our proposed circuit was determined as 2.5 after considering critical factors gain, and PAE, as shown in Figure 4.The diagram in Figure 5 illustrates the layout and the simulated performance of the unequal Wilkinson power divider.Return loss was below −17 dB over the entire band (3.3-3.8GHz).The isolated port was connected to allow for the insertion of an externa resistor.The diagram in Figure 5 illustrates the layout and the simulated performance of the unequal Wilkinson power divider.Return loss was below −17 dB over the entire band (3.3-3.8GHz).The isolated port was connected to allow for the insertion of an external resistor.

Load Modulation in DPAs
Load modulation in DPAs enhances efficiency and linearity by adjusting the carrier amplifier's load impedance, optimizing its efficiency and reducing heat generation.It also aligns the carrier amplifier's load with the peaking amplifier's output power, reducing distortion and enhancing signal quality.When combined with techniques like bias modulation and envelope tracking, it further improves DPA performance.Both amplifiers employ an output combiner with quarter-wavelength transmission lines, providing a 90-degree phase shift and contributing to load modulation.This modulation adjusts the impedance presented to the PA's output, varying with the current from the other device, as seen in Figure 6 [29].When the input power is low (in back-off conditions), only the carrier PA is active and the impedance presented to the peaking PA ( ) will be ∞.The impedance at the combination point ( ) is first transformed to 25 ohms using the 35.35-ohm impedance transformer as per Equation (9), and the impedance presented to the carrier PA ( ) is 100 ohms as per Equation (10).When the input power increases, the peaking PA becomes active.At this time, the output impedance presented to the carrier PA and the peaking PA are both 50 ohms as per Equation (10).In both conditions, considering the 35.35-ohm impedance transformer performance, the load impedances of the main and peaking amplifiers change based on given information and the value of impedance at the combination

Load Modulation in DPAs
Load modulation in DPAs enhances efficiency and linearity by adjusting the carrier amplifier's load impedance, optimizing its efficiency and reducing heat generation.It also aligns the carrier amplifier's load with the peaking amplifier's output power, reducing distortion and enhancing signal quality.When combined with techniques like bias modulation and envelope tracking, it further improves DPA performance.Both amplifiers employ an output combiner with quarter-wavelength transmission lines, providing a 90-degree phase shift and contributing to load modulation.This modulation adjusts the impedance presented to the PA's output, varying with the current from the other device, as seen in Figure 6 [29].

Load Modulation in DPAs
Load modulation in DPAs enhances efficiency and linearity by adjusting the carrier amplifier's load impedance, optimizing its efficiency and reducing heat generation.It also aligns the carrier amplifier's load with the peaking amplifier's output power, reducing distortion and enhancing signal quality.When combined with techniques like bias modulation and envelope tracking, it further improves DPA performance.Both amplifiers employ an output combiner with quarter-wavelength transmission lines, providing a 90-degree phase shift and contributing to load modulation.This modulation adjusts the impedance presented to the PA's output, varying with the current from the other device, as seen in Figure 6 [29].When the input power is low (in back-off conditions), only the carrier PA is active and the impedance presented to the peaking PA ( ) will be ∞.The impedance at the combination point ( ) is first transformed to 25 ohms using the 35.35-ohm impedance transformer as per Equation (9), and the impedance presented to the carrier PA ( ) is 100 ohms as per Equation (10).When the input power increases, the peaking PA becomes active.At this time, the output impedance presented to the carrier PA and the peaking PA are both 50 ohms as per Equation (10).In both conditions, considering the 35.35-ohm impedance transformer performance, the load impedances of the main and peaking amplifiers change based on given information and the value of impedance at the combination When the input power is low (in back-off conditions), only the carrier PA is active and the impedance presented to the peaking PA (Z P ) will be ∞.The impedance at the combination point Z Ć is first transformed to 25 ohms using the 35.35-ohm impedance transformer as per Equation (9), and the impedance presented to the carrier PA (Z C ) is 100 ohms as per Equation (10).When the input power increases, the peaking PA becomes active.At this time, the output impedance presented to the carrier PA and the peaking PA are both 50 ohms as per Equation (10).In both conditions, considering the 35.35-ohm impedance transformer performance, the load impedances of the main and peaking amplifiers change based on given information and the value of impedance at the combination point Z Ć lead to 25 Ω.This impedance would be transformed to the output impedance (R L = 50 Ω) using a 35.35Ω impedance transformer as depicted in Figure 6.

Design of Input-and Output-Matching Networks
The broadband DPA operating from 3.3 GHz to 3.8 GHz, utilizing two 10 W GaN transistors (CG2H40010F from Cree), was designed to validate our proposed approach.We performed load-pull simulations on the selected high-power-density device using a drain bias of 28 V at 3.5 GHz to determine the desired output power and gain, and by using the source and load impedance values of the device from its datasheet, as displayed in Figure 7.
Electronics 2023, 12, x FOR PEER REVIEW 7 of 22 point ( ) lead to 25 Ω.This impedance would be transformed to the output impedance ( = 50 Ω) using a 35.35Ω impedance transformer as depicted in Figure 6.

Design of Input-and Output-Matching Networks
The broadband DPA operating from 3.3 GHz to 3.8 GHz, utilizing two 10 W GaN transistors (CG2H40010F from Cree), was designed to validate our proposed approach.We performed load-pull simulations on the selected high-power-density device using a drain bias of 28 V at 3.5 GHz to determine the desired output power and gain, and by using the source and load impedance values of the device from its datasheet, as displayed in Figure 7. Designing DPA matching networks, including an input-matching network (IMN) and an output-matching network (OMN), is vital for optimizing performance.An IMN ensures efficient power transfer by matching DPA input impedance to the source, while an OMN matches the DPA load impedance.Keeping the PA's output reflection co-efficient below −10 dB is crucial, and ADS aids in determining actual input and output impedances.Load-pull simulations reveal power and PAE contours, e.g., CG2H40010F GaN HEMT's 3.5 GHz performance with 40.26 dBm output power and 60.28% PAE (Figure 8).The load-pull simulation revealed input and output impedances of 6.617 + j10.23 Ω and 13.28 + j1.518 Ω.The design employs distributed elements to match the power amplifier's input and output sections, fine-tuned across the bandwidth using the Smith chart utility tool in ADS.Optimized input and output networks were connected to the CG2H40010F, utilizing TLIN elements converted to MLIN.The final layouts with the optimized input-and output-matching networks for the main transistor are shown in Figure Designing DPA matching networks, including an input-matching network (IMN) and an output-matching network (OMN), is vital for optimizing performance.An IMN ensures efficient power transfer by matching DPA input impedance to the source, while an OMN matches the DPA load impedance.Keeping the PA's output reflection co-efficient below −10 dB is crucial, and ADS aids in determining actual input and output impedances.Load-pull simulations reveal power and PAE contours, e.g., CG2H40010F GaN HEMT's 3.5 GHz performance with 40.26 dBm output power and 60.28% PAE (Figure 8).
Electronics 2023, 12, x FOR PEER REVIEW 7 of 22 point ( ) lead to 25 Ω.This impedance would be transformed to the output impedance ( = 50 Ω) using a 35.35Ω impedance transformer as depicted in Figure 6.

Design of Input-and Output-Matching Networks
The broadband DPA operating from 3.3 GHz to 3.8 GHz, utilizing two 10 W GaN transistors (CG2H40010F from Cree), was designed to validate our proposed approach.We performed load-pull simulations on the selected high-power-density device using a drain bias of 28 V at 3.5 GHz to determine the desired output power and gain, and by using the source and load impedance values of the device from its datasheet, as displayed in Figure 7. Designing DPA matching networks, including an input-matching network (IMN) and an output-matching network (OMN), is vital for optimizing performance.An IMN ensures efficient power transfer by matching DPA input impedance to the source, while an OMN matches the DPA load impedance.Keeping the PA's output reflection co-efficient below −10 dB is crucial, and ADS aids in determining actual input and output impedances.Load-pull simulations reveal power and PAE contours, e.g., CG2H40010F GaN HEMT's 3.5 GHz performance with 40.26 dBm output power and 60.28% PAE (Figure 8).The load-pull simulation revealed input and output impedances of 6.617 + j10.23 Ω and 13.28 + j1.518 Ω.The design employs distributed elements to match the power amplifier's input and output sections, fine-tuned across the bandwidth using the Smith chart utility tool in ADS.Optimized input and output networks were connected to the CG2H40010F, utilizing TLIN elements converted to MLIN.The final layouts with the optimized input-and output-matching networks for the main transistor are shown in Figure The load-pull simulation revealed input and output impedances of 6.617 + j10.23 Ω and 13.28 + j1.518 Ω.The design employs distributed elements to match the power amplifier's input and output sections, fine-tuned across the bandwidth using the Smith chart utility tool in ADS.Optimized input and output networks were connected to the CG2H40010F, utilizing TLIN elements converted to MLIN.The final layouts with the optimized inputand output-matching networks for the main transistor are shown in Figure 9 and include the gate and drain biasing network.The procedure for designing input-and output-matching networks for the auxiliary transistor mirrors the main transistor's approach.Figure 10 presents the final designs, detailing microstrip line dimensions and gate/drain bias values for the auxiliary transistor.

Stability Analysis
Stability analysis plays a crucial role in DPA design, ensuring the amplifier's reliability under various conditions.The stability of a DPA is influenced by several factors, including impedance matching, load and source impedance, bias settings, and the characteristics of the power combiner.To function effectively as an RF power amplifier instead of an oscillator, a DPA must possess a stability factor (K) greater than 1 [30].One commonly used method for assessing unconditional stability, where K > 1, is Rollet's condition, which relies on the value of K.However, while the K-Δ test provides a mathematical evaluation of unconditional stability, it does not enable straightforward comparisons between different devices due to its reliance on two separate parameters.A newer criterion, utilizing a single parameter μ [31], has been introduced to gauge stability.When μ surpasses 1, the device is considered unconditionally stable, and higher μ values indicate greater stability.
According to the stability plot in Figure 11, the device is unconditionally stable through both the K-Δ Test and the μ-Test by adding a 3.3-ohm resistance in the gate pin

Stability Analysis
Stability analysis plays a crucial role in DPA design, ensuring the amplifier's reliability under various conditions.The stability of a DPA is influenced by several factors, including impedance matching, load and source impedance, bias settings, and the characteristics of the power combiner.To function effectively as an RF power amplifier instead of an oscillator, a DPA must possess a stability factor (K) greater than 1 [30].One commonly used method for assessing unconditional stability, where K > 1, is Rollet's condition, which relies on the value of K.However, while the K-Δ test provides a mathematical evaluation of unconditional stability, it does not enable straightforward comparisons between different devices due to its reliance on two separate parameters.A newer criterion, utilizing a single parameter μ [31], has been introduced to gauge stability.When μ surpasses 1, the device is considered unconditionally stable, and higher μ values indicate greater stability.
According to the stability plot in Figure 11, the device is unconditionally stable through both the K-Δ Test and the μ-Test by adding a 3.3-ohm resistance in the gate pin

Stability Analysis
Stability analysis plays a crucial role in DPA design, ensuring the amplifier's reliability under various conditions.The stability of a DPA is influenced by several factors, including impedance matching, load and source impedance, bias settings, and the characteristics of the power combiner.To function effectively as an RF power amplifier instead of an oscillator, a DPA must possess a stability factor (K) greater than 1 [30].One commonly used method for assessing unconditional stability, where K > 1, is Rollet's condition, which relies on the value of K.However, while the K-∆ test provides a mathematical evaluation of unconditional stability, it does not enable straightforward comparisons between different devices due to its reliance on two separate parameters.A newer criterion, utilizing a single parameter µ [31], has been introduced to gauge stability.When µ surpasses 1, the device is considered unconditionally stable, and higher µ values indicate greater stability.
According to the stability plot in Figure 11, the device is unconditionally stable through both the K-∆ Test and the µ-Test by adding a 3.3-ohm resistance in the gate pin of both transistors in the frequency range of 3 to 4 GHz.This finding makes the device appropriate for the DPA design proposed in the paper.

Design of Harmonic Suppression Network
DPA's post-harmonic suppression network aims to reduce the high-order harmonic content generated by the amplifier and thus increase the efficiency of our amplifier.This is achieved by designing the circuit such that the two active devices in the Doherty configuration, the main amplifier and the peaking amplifier, operate out of phase with each other.The design of a maximally flat (Binomial) low-pass filter, to be fabricated using microstrip lines, has a cutoff frequency of 4.5 GHz.By following the proposed filter specifications, it was determined that an order of 7 (N = 7) would suffice.Referencing [32], the prototype element values can be determined.The next step is to calculate the new filter component values from capacitors ( ) and inductors ( ) by means of Equations ( 11) and (12).
where  is the cutoff frequency;  and  are the component values for the original prototype; and  is the nominal characteristic impedance equal to 50 Ω.To increase its reliability for use in high-frequency RF circuits, the lumped-element filter can be transformed into a system of distributed elements, such as open-or short-circuited transmission line stubs.This conversion can be achieved through the use of Richards' transformation, which transforms lumped elements into transmission line sections.The filter elements are then physically separated by applying Kuroda's identities to the transmission line sections [32].Figure 12a presents the electrical transmission line schematic design of the harmonic suppression network, which has been carefully developed based on the previously discussed steps.The final layout of the network, shown in Figure 12b, displays the physical width and length of the design, including the integration of 35.35-ohm impedance transformers at the beginning of the network.To enhance the performance of the network, an additional series microstrip line has been added to ensure a 50-ohm connection to the output combiner, ensuring an appropriate width for welding the output port with the load.To ensure a smooth transition from the electrical microstrip lines shown in Figure 12a to the physical lines in Figure 12b, and prevent any junction discontinuity, a T-junction model has been added.To ensure that the performance of the network was not impacted by the additions made to it, an

Design of Harmonic Suppression Network
DPA's post-harmonic suppression network aims to reduce the high-order harmonic content generated by the amplifier and thus increase the efficiency of our amplifier.This is achieved by designing the circuit such that the two active devices in the Doherty configuration, the main amplifier and the peaking amplifier, operate out of phase with each other.The design of a maximally flat (Binomial) low-pass filter, to be fabricated using microstrip lines, has a cutoff frequency of 4.5 GHz.By following the proposed filter specifications, it was determined that an order of 7 (N = 7) would suffice.Referencing [32], the prototype element values can be determined.The next step is to calculate the new filter component values from capacitors (C k ) and inductors (L k ) by means of Equations ( 11) and (12).
where ω c is the cutoff frequency; L k and C k are the component values for the original prototype; and R 0 is the nominal characteristic impedance equal to 50 Ω.To increase its reliability for use in high-frequency RF circuits, the lumped-element filter can be transformed into a system of distributed elements, such as open-or short-circuited transmission line stubs.This conversion can be achieved through the use of Richards' transformation, which transforms lumped elements into transmission line sections.The filter elements are then physically separated by applying Kuroda's identities to the transmission line sections [32].Figure 12a presents the electrical transmission line schematic design of the harmonic suppression network, which has been carefully developed based on the previously discussed steps.The final layout of the network, shown in Figure 12b, displays the physical width and length of the design, including the integration of 35.35-ohm impedance transformers at the beginning of the network.To enhance the performance of the network, an additional series microstrip line has been added to ensure a 50-ohm connection to the output combiner, ensuring an appropriate width for welding the output port with the load.To ensure a smooth transition from the electrical microstrip lines shown in Figure 12a to the physical lines in Figure 12b, and prevent any junction discontinuity, a T-junction model has been added.To ensure that the performance of the network was not impacted by the additions made to it, an improvement was made to the network values using the Optimization Cockpit tool in ADS.The result of this optimization can be seen in the frequency response of the electromagnetic simulation results for the proposed network, which is displayed in Figure 13.
improvement was made to the network values using the Optimization Cockpit tool in ADS.The result of this optimization can be seen in the frequency response of the electromagnetic simulation results for the proposed network, which is displayed in Figure 13.

Implementation and Simulation Results of the N78 Band Sub-6 GHz DPA
The final circuit design of the DPA is shown in Figure 14 and is composed of several parts: an unequal Wilkinson power divider to split the input signal, a phase compensation network to correct the phase difference between the carrier and peaking branches, and inputmatching networks, consisting of two identical CG2H40010F devices.Additionally, the design The result of this optimization can be seen in the frequency response of the electromagnetic simulation results for the proposed network, which is displayed in Figure 13.

Implementation and Simulation Results of the N78 Band Sub-6 GHz DPA
The final circuit design of the DPA is shown in Figure 14 and is composed of several parts: an unequal Wilkinson power divider to split the input signal, a phase compensation network to correct the phase difference between the carrier and peaking branches, and inputmatching networks, consisting of two identical CG2H40010F devices.Additionally, the design

Implementation and Simulation Results of the N78 Band Sub-6 GHz DPA
The final circuit design of the DPA is shown in Figure 14 and is composed of several parts: an unequal Wilkinson power divider to split the input signal, a phase compensation network to correct the phase difference between the carrier and peaking branches, and input-matching networks, consisting of two identical CG2H40010F devices.Additionally, the design features output-matching networks, an impedance inverter network, and a harmonic suppression network with a 35.35-ohm impedance transformer.To enhance performance, bypass capacitors with a high Q factor of 500 were added to the DC biasing line for amplifiers C 1 , C 2 , C 3 , and C 4 , with capacitance values of 1 pF.The DC coupler comprises surface mount device (SMD) capacitors C 5 , C 6 , C 7 , and C 8 with capacitance values of 15 pF.The DPA was fabricated on a Rogers RT/duroid 5880 substrate, which has a relative dielectric constant (εr) of 2.2, a substrate thickness (H) of 31 mil, a loss tangent (Tan δ) of 0.0009, and copper conductors with conductivity (σ) of 5.8 × 10 3 and a thickness (T) of 0.035 mm.The main and auxiliary amplifiers are powered by the same drain bias voltage (V DS ) of 28 V, with the main gate bias voltage being set at −2.7 V and the auxiliary gate bias voltage set at −4 V.The scatter parameters of the designed DPA are displayed in Figure 15.The simulation results indicate that despite a slight shift towards lower frequencies, the DPA maintained a small-signal gain of approximately 14 dB within a 600 MHz bandwidth ranging from 3.20 GHz to 3.80 GHz, providing full coverage of the N78 frequency band.Additionally, input matching was achieved with better than 13 dB across the operating range from 3.20 GHz to 3.90 GHz.The output matching was approximately 13 dB in the higher portion of the operating band, ranging from 3.2 to 3.9 GHz, but slightly decreased towards the lower end of the band.features output-matching networks, an impedance inverter network, and a harmonic suppression network with a 35.35-ohm impedance transformer.To enhance performance, bypass capacitors with a high Q factor of 500 were added to the DC biasing line for amplifiers C1, C2, C3, and C4, with capacitance values of 1 pF.The DC coupler comprises surface mount device (SMD) capacitors C5, C6, C7, and C8 with capacitance values of 15 pF.The DPA was fabricated on a Rogers RT/duroid 5880 substrate, which has a relative dielectric constant (εr) of 2.2, a substrate thickness (H) of 31 mil, a loss tangent (Tan δ) of 0.0009, and copper conductors with conductivity (σ) of 5.8 × 10 3 and a thickness (T) of 0.035 mm.The main and auxiliary amplifiers are powered by the same drain bias voltage (VDS) of 28 V, with the main gate bias voltage being set at −2.7 V and the auxiliary gate bias voltage set at −4 V.The scatter parameters of the designed DPA are displayed in Figure 15.The simulation results indicate that despite a slight shift towards lower frequencies, the DPA maintained a small-signal gain of approximately 14 dB within a 600 MHz bandwidth ranging from 3.20 GHz to 3.80 GHz, providing full coverage of the N78 frequency band.Additionally, input matching was achieved with better than 13 dB across the operating range from 3.20 GHz to 3.90 GHz.The output matching was approximately 13 dB in the higher portion of the operating band, ranging from 3.2 to 3.9 GHz, but slightly decreased towards the lower end of the band.

Simulated DPA Performance
This section presents the results of the designed Doherty power amplifier, including curves of output power, power gain, and power-added efficiency (PAE).Figure 16 illustrates the simulated values of output power (Pout), amplifier gain, drain efficiency (DE), and power-added efficiency (PAE) plotted against the input power (Pin), which is scaled from 0 to 40 dBm.In Figure 16a, it can be observed that the large-signal gain during nominal operation is approximately 15.7 dB when the input power is at 10 dBm.To achieve a 3 dB compression point value (P3dB) for our design, the Pin value needs to be set at 29.2 dBm.Consequently, the output power is approximately 41.8 dBm at P3db when the Pin value is at 29.2 dBm.The simulated plot of both the drain efficiency and the power-added efficiency of the proposed DPA design is presented in Figure 16b, when getting 78.4% and 74.3% of the P3dB, respectively.Compared with the efficiency characteristics of a non-Doherty power amplifier (class AB) bias conditions, we obtain a PAE at the P3db point of 55% and 58% for DE, as shown in Figure 17.The corresponding intrinsic drain voltage current waveforms of the designed DPA are depicted in Figure 18.

Simulated DPA Performance
This section presents the results of the designed Doherty power amplifier, including curves of output power, power gain, and power-added efficiency (PAE).Figure 16 illustrates the simulated values of output power (Pout), amplifier gain, drain efficiency (DE), and power-added efficiency (PAE) plotted against the input power (Pin), which is scaled from 0 to 40 dBm.In Figure 16a, it can be observed that the large-signal gain during nominal operation is approximately 15.7 dB when the input power is at 10 dBm.To achieve a 3 dB compression point value (P3dB) for our design, the Pin value needs to be set at 29.2 dBm.Consequently, the output power is approximately 41.8 dBm at P3db when the Pin value is at 29.2 dBm.The simulated plot of both the drain efficiency and the power-added efficiency of the proposed DPA design is presented in Figure 16b, when getting 78.4% and 74.3% of the P3dB, respectively.Compared with the efficiency characteristics of a non-Doherty power amplifier (class AB) bias conditions, we obtain a PAE at the P3db point of 55% and 58% for DE, as shown in Figure 17.The corresponding intrinsic drain voltage and current waveforms of the designed DPA are depicted in Figure 18.

Simulated DPA Performance
This section presents the results of the designed Doherty power amplifier, including curves of output power, power gain, and power-added efficiency (PAE).Figure 16 illustrates the simulated values of output power (Pout), amplifier gain, drain efficiency (DE), and power-added efficiency (PAE) plotted against the input power (Pin), which is scaled from 0 to 40 dBm.In Figure 16a, it can be observed that the large-signal gain during nominal operation is approximately 15.7 dB when the input power is at 10 dBm.To achieve a 3 dB compression point value (P3dB) for our design, the Pin value needs to be set at 29.2 dBm.Consequently, the output power is approximately 41.8 dBm at P3db when the Pin value is at 29.2 dBm.The simulated plot of both the drain efficiency and the power-added efficiency of the proposed DPA design is presented in Figure 16b, when getting 78.4% and 74.3% of the P3dB, respectively.Compared with the efficiency characteristics of a non-Doherty power amplifier (class AB) bias conditions, we obtain a PAE at the P3db point of 55% and 58% for DE, as shown in Figure 17.The corresponding intrinsic drain voltage and current waveforms of the designed DPA are depicted in Figure 18.

Performance Comparison of Three DPA Designs
In this section, we present and analyze results for three DPA designs in Figure 19, all of whose design parts have been discussed previously.The first design, labeled as (EPD without HS), utilizes an equal Wilkinson power divider but lacks a harmonic suppression network.The results of this design can be seen in Figure 19 as the solid blue line with a square symbol.The second design, labeled as (UPD without HS), is another DPA that employs an unequal Wilkinson power divider and does not include a harmonic suppression network.In Figure 19, the results of this design are represented by the solid green line with a triangle symbol.Lastly, the third design, identified by the labeled (UPD with HS), features an unequal Wilkinson power divider along with a harmonic suppression network.The results of this design can be seen in Figure 19 as the solid red line with a circle symbol.
This paper proposes adopting the third design of the DPA, which incorporates a postharmonic suppression network on the output in addition to an unequal Wilkinson power divider on the input.The performance of the proposed amplifier in the third design was compared to the previous two designs, and the results are summarized in Table 2.The large-signal gain of the amplifier in the proposed design reaches 12 dB, representing a 15% improvement over the first design and a 4% improvement over the second design, as shown in Figure 19a.There is also an improvement in the output power of the amplifier, which reaches 41.85 dBm, an increase of 4.6% over the first design and 1.6% over the second design, as shown in Figure 19b.Although the improvement in gain and output power values is not substantial due to the harmonic suppression network being considered a load on the output of the amplifier, its impact is evident in the improved drain efficiency and power-added efficiency, which reached 75.4% and 70.6%, respectively, representing a 64.6% and 69.5% improvement over the first design, and a 33.2% and 34.2% improvement over the second design, as shown in Figure 19c,d.

Performance Comparison of Three DPA Designs
In this section, we present and analyze results for three DPA designs in Figure 19, all of whose design parts have been discussed previously.The first design, labeled as (EPD without HS), utilizes an equal Wilkinson power divider but lacks a harmonic suppression network.The results of this design can be seen in Figure 19 as the solid blue line with a square symbol.The second design, labeled as (UPD without HS), is another DPA that employs an unequal Wilkinson power divider and does not include a harmonic suppression network.In Figure 19, the results of this design are represented by the solid green line with a triangle symbol.Lastly, the third design, identified by the labeled (UPD with HS), features an unequal Wilkinson power divider along with a harmonic suppression network.The results of this design can be seen in Figure 19 as the solid red line with a circle symbol.
This paper proposes adopting the third design of the DPA, which incorporates a post-harmonic suppression network on the output in addition to an unequal Wilkinson power divider on the input.The performance of the proposed amplifier in the third design was compared to the previous two designs, and the results are summarized in Table 2.The large-signal gain of the amplifier in the proposed design reaches 12 dB, representing a 15% improvement over the first design and a 4% improvement over the second design, as shown in Figure 19a.There is also an improvement in the output power of the amplifier, which reaches 41.85 dBm, an increase of 4.6% over the first design and 1.6% over the second design, as shown in Figure 19b.Although the improvement in gain and output power values is not substantial due to the harmonic suppression network being considered a load on the output of the amplifier, its impact is evident in the improved drain efficiency and power-added efficiency, which reached 75.4% and 70.6%, respectively, representing a 64.6% and 69.5% improvement over the first design, and a 33.2% and 34.2% improvement over the second design, as shown in Figure 19c,d.

The Performance of the Unequal Wilkinson Power Divider
Figure 20 displays a photograph of a 2.5:1 Wilkinson power divider that underwent fabrication and subsequent connection to a vector network analyzer device.This connection allowed for the measurement of its circuit S-parameters, focusing on a central frequency of 3.5 GHz. Figure 21 presents a comparison between the measurement and simulation results, utilizing CST Studio Suite software version 2021, for the proposed unequal divider.The measurements revealed insertion loss values of approximately 2 dB for S21 and 7.2 dB for S31, both at 3.5 GHz.Additionally, the output port isolation (S23) exhibited performance better than 12 dB, indicating effective isolation between the two output ports.The measured return loss (S11) also surpassed 20.6 dB at 3.4 GHz.However, some inconsistencies between the simulation and measurement outcomes were observed in Figure 21.These disparities could be attributed to unforeseen variations that occurred during the fabrication and assembly processes.Furthermore, the decision to employ two 220 Ω resistors in parallel, necessitated by the unavailability of a single 110 Ω resistor in the Egyptian market, may have played a role in these observed discrepancies.

The Performance of the Unequal Wilkinson Power Divider
Figure 20 displays a photograph of a 2.5:1 Wilkinson power divider that underwent fabrication and subsequent connection to a vector network analyzer device.This connection allowed for the measurement of its circuit S-parameters, focusing on a central frequency of 3.5 GHz. Figure 21 presents a comparison between the measurement and simulation results, utilizing CST Studio Suite software version 2021, for the proposed unequal divider.The measurements revealed insertion loss values of approximately 2 dB for S21 and 7.2 dB for S31, both at 3.5 GHz.Additionally, the output port isolation (S23) exhibited performance better than 12 dB, indicating effective isolation between the two output ports.The measured return loss (S11) also surpassed 20.6 dB at 3.4 GHz.However, some inconsistencies between the simulation and measurement outcomes were observed in Figure 21.These disparities could be attributed to unforeseen variations that occurred during the fabrication and assembly processes.Furthermore, the decision to employ two 220 Ω resistors in parallel, necessitated by the unavailability of a single 110 Ω resistor in the Egyptian market, may have played a role in these observed discrepancies.

The Performance of the Harmonic Suppression Network
Figure 22 displays a photograph of the post-harmonic suppression network that was fabricated and combined with a 35.35-ohm impedance transformers microstrip line at the input port and a 50-ohm microstrip line at the network end to allow sufficient soldering space for the SMA coaxial connectors.The response of the proposed filter was measured using an R&S ® ZVB vector network analyzer from 0 to 16 GHz, and the results are shown in Figure 23.To make the measurement easy, the source/load impedances of the filter were set at 50 Ω, and the filter exhibited a seventh-order general Binomial low-pass response that was visible.The measured response (blue solid line) of the filter had a low-pass characteristic with a 3 dB cutoff frequency of 4.9 GHz.The insertion loss reached 10 dB at 5.5 GHz and 26.3 dB at 7 GHz.These measurements were in good agreement with the simulated results.
Electronics 2023, 12, x FOR PEER REVIEW

The Performance of the Harmonic Suppression Network
Figure 22 displays a photograph of the post-harmonic suppression network t fabricated and combined with a 35.35-ohm impedance transformers microstrip lin input port and a 50-ohm microstrip line at the network end to allow sufficient so space for the SMA coaxial connectors.The response of the proposed filter was m using an R&S ® ZVB vector network analyzer from 0 to 16 GHz, and the results ar in Figure 23.To make the measurement easy, the source/load impedances of the fil set at 50 Ω, and the filter exhibited a seventh-order general Binomial low-pass r that was visible.The measured response (blue solid line) of the filter had a low-pa acteristic with a 3 dB cutoff frequency of 4.9 GHz.The insertion loss reached 10 d GHz and 26.3 dB at 7 GHz.These measurements were in good agreement with th lated results.Figure 24 illustrates the effect of our proposed design (DPA with HS) on the tion output power of harmonics from the second to the fourth order in compariso harmonic content of a conventional DPA (DPA without HS) in terms of input pow results demonstrate that the suggested topology provides excellent harmonic sup with high efficiency versus input power.Although the Doherty amplifier is a balan plifier, our design considered the fundamental frequency.We incorporated a sugges monic suppression network at the output to prevent the occurrence of harmonics, clearly demonstrated in the harmonic balance simulation results shown in Figure impact of the post-harmonic suppression network is illustrated by comparing the h spectra at the output of the RF amplifier.Figure 25 displays the spectra of four ha for power, voltage, and current obtained from the harmonic balance (HB) simulati spectrum figure includes DC (0 Hz), fundamental (3.5 GHz), second (7 GHz), th GHz), and fourth (14 GHz) harmonic components.Notably, the values of the se fourth harmonics are all below −50 dBm, providing evidence of the effective sup achieved by the proposed harmonic suppression network.This successful suppress tributes to increased amplifier efficiency and improved linearity of the output signa findings are further supported by the simulated time-domain output voltage and waveforms for the proposed DPA, as illustrated in Figure 26. Figure 24 illustrates the effect of our proposed design (DPA with HS) on the attenuation output power of harmonics from the second to the fourth order in comparison to the harmonic content of a conventional DPA (DPA without HS) in terms of input power.The results demonstrate that the suggested topology provides excellent harmonic suppression with high efficiency versus input power.Although the Doherty amplifier is a balanced amplifier, our design considered the fundamental frequency.We incorporated a suggested harmonic suppression network at the output to prevent the occurrence of harmonics, which is clearly demonstrated in the harmonic balance simulation results shown in Figure 25.The impact of the post-harmonic suppression network is illustrated by comparing the harmonic spectra at the output of the RF amplifier.Figure 25 displays the spectra of four harmonics for power, voltage, and current obtained from the harmonic balance (HB) simulation.Each spectrum figure includes DC (0 Hz), fundamental (3.5 GHz), second (7 GHz), third (10.5 GHz), and fourth (14 GHz) harmonic components.Notably, the values of the second to fourth harmonics are all below −50 dBm, providing evidence of the effective suppression achieved by the proposed harmonic suppression network.This successful suppression contributes to increased amplifier efficiency and improved linearity of the output signal.These findings are further supported by the simulated time-domain output voltage and current waveforms for the proposed DPA, as illustrated in Figure 26.The proposed DPA components were assembled with the addition of two transmission lines for 50-ohm impedance at the input and output ports.Optimizing these transmission lines, converted from electrical lengths to physical dimensions, yielded the highest results via EM simulation (Figure 27).This simulation confirms the DPA's proper operation within the 3.3-3.8GHz frequency range, as seen in Figure 27.The parameters of gain, output power, DE, and PAE at the center frequency of 3.5 GHz are presented.Notably, maximum PAE and DE values reach around 75.2% and 80%, respectively, while the amplifier achieves a large-signal gain exceeding 12 dB and an output power of approximately 42 dBm.As previously discussed, the proposed DPA structure significantly enhances PAE, DE, and gain.These improvements were investigated by implementing an unequal Wilkinson power divider at the amplifier's input and introducing a harmonic suppression network at the output.The proposed DPA components were assembled with the addition of two transmission lines for 50-ohm impedance at the input and output ports.Optimizing these transmission lines, converted from electrical lengths to physical dimensions, yielded the highest results via EM simulation (Figure 27).This simulation confirms the DPA's proper operation within the 3.3-3.8GHz frequency range, as seen in Figure 27.The parameters of gain, output power, DE, and PAE at the center frequency of 3.5 GHz are presented.Notably, maximum PAE and DE values reach around 75.2% and 80%, respectively, while the amplifier achieves a large-signal gain exceeding 12 dB and an output power of approximately 42 dBm.As previously discussed, the proposed DPA structure significantly enhances PAE, DE, and gain.These improvements were investigated by implementing an unequal Wilkinson power divider at the amplifier's input and introducing a harmonic suppression network at the output.The proposed DPA components were assembled with the addition of two transmission lines for 50-ohm impedance at the input and output ports.Optimizing these transmission lines, converted from electrical lengths to physical dimensions, yielded the highest results via EM simulation (Figure 27).This simulation confirms the DPA's proper operation within the 3.3-3.8GHz frequency range, as seen in Figure 27.The parameters of gain, output power, DE, and PAE at the center frequency of 3.5 GHz are presented.Notably, maximum PAE and DE values reach around 75.2% and 80%, respectively, while the amplifier achieves a large-signal gain exceeding 12 dB and an output power of approximately 42 dBm.As previously discussed, the proposed DPA structure significantly enhances PAE, DE, and gain.These improvements were investigated by implementing an unequal Wilkinson power divider at the amplifier's input and introducing a harmonic suppression network at the output.
Table 3 offers a performance summary of the DPA designed in this study, comparing it with other studies focusing on Doherty amplifier design within the 6 GHz frequency band for 5G applications.Wherever feasible, we have used the same device for comparison, with the assessments relying on simulation results.Our proposed DPA, as discussed earlier, achieved notable PAE levels and demonstrated a broad bandwidth.This performance aligns with existing technologies in this frequency range, affirming the suitability of our straightforward and efficient broadband approach for 5G applications in the N78 band.

Figure 1 .
Figure 1.An illustration of the planned Doherty power amplifier.

Figure 1 .
Figure 1.An illustration of the planned Doherty power amplifier.

Figure 2 .
Figure 2. Efficiency plot for the Doherty amplifier against input power [9].

Figure 4 .
Figure 4.The gain and PAE of the proposed circuit with a sweep of division factor (Q).

Figure 4 .
Figure 4.The gain and PAE of the proposed circuit with a sweep of division factor (Q).

Figure 4 .
Figure 4.The gain and PAE of the proposed circuit with a sweep of division factor (Q).

Figure 6 .
Figure 6.The schematic diagram of a DPA with the principle of load modulation for adjustment output impedance of the amplifier.

Figure 6 .
Figure 6.The schematic diagram of a DPA with the principle of load modulation for adjustment output impedance of the amplifier.

Figure 6 .
Figure 6.The schematic diagram of a DPA with the principle of load modulation for adjustment output impedance of the amplifier.

Figure 8 .
Figure 8.(a) Setup simulations of load-pull analysis.(b) Load-pull results of PAE and output power contours.

Figure 8 .
Figure 8.(a) Setup simulations of load-pull analysis.(b) Load-pull results of PAE and output power contours.

Figure 8 .
Figure 8.(a) Setup simulations of load-pull analysis.(b) Load-pull results of PAE and output power contours.

Electronics 2023 ,Figure 9 .Figure 10 .
Figure 9.The layout of the (a) IMN of the main and (b) OMN of the main (dimensions in mm).

Figure 9 .Figure 9 .Figure 10 .
Figure 9.The layout of the (a) IMN of the main and (b) OMN of the main (dimensions in mm).

Figure 10 .
Figure 10.The layout of the (a) IMN of the peak and (b) OMN of the peak (dimensions in mm).

Electronics 2023 ,
12,  x FOR PEER REVIEW 9 of 22 of both transistors in the frequency range of 3 to 4 GHz.This finding makes the device appropriate for the DPA design proposed in the paper.

Figure 12 .
Figure 12.Harmonic suppression network design.(a) Ideal transmission line schematic.(b) Layout design with dimensions in mm.

Figure 13 .
Figure 13.Results of the electromagnetic simulation of S-parameters for the proposed harmonic suppression network.

Figure 12 .
Figure 12.Harmonic suppression network design.(a) Ideal transmission line schematic.(b) Layout design with dimensions in mm.

Figure 12 .
Figure 12.Harmonic suppression network design.(a) Ideal transmission line schematic.(b) Layout design with dimensions in mm.

Figure 13 .
Figure 13.Results of the electromagnetic simulation of S-parameters for the proposed harmonic suppression network.

Figure 13 .
Figure 13.Results of the electromagnetic simulation of S-parameters for the proposed harmonic suppression network.

Electronics 2023 ,
12,  x FOR PEER REVIEW 11 of 22 features output-matching networks, an impedance inverter network, and a harmonic suppression network with a 35.35-ohm impedance transformer.To enhance performance, bypass capacitors with a high Q factor of 500 were added to the DC biasing line for amplifiers C1, C2, C3, and C4, with capacitance values of 1 pF.The DC coupler comprises surface mount device (SMD) capacitors C5, C6, C7, and C8 with capacitance values of 15 pF.The DPA was fabricated on a Rogers RT/duroid 5880 substrate, which has a relative dielectric constant (εr) of 2.2, a substrate thickness (H) of 31 mil, a loss tangent (Tan δ) of 0.0009, and copper conductors with conductivity (σ) of 5.8 × 10 3 and a thickness (T) of 0.035 mm.The main and auxiliary amplifiers are powered by the same drain bias voltage (VDS) of 28 V, with the main gate bias voltage being set at −2.7 V and the auxiliary gate bias voltage set at −4 V.The scatter parameters of the designed DPA are displayed in Figure15.The simulation results indicate that despite a slight shift towards lower frequencies, the DPA maintained a small-signal gain of approximately 14 dB within a 600 MHz bandwidth ranging from 3.20 GHz to 3.80 GHz, providing full coverage of the N78 frequency band.Additionally, input matching was achieved with better than 13 dB across the operating range from 3.20 GHz to 3.90 GHz.The output matching was approximately 13 dB in the higher portion of the operating band, ranging from 3.2 to 3.9 GHz, but slightly decreased towards the lower end of the band.

Figure 14 .
Figure 14.Completely layout design of the proposed Doherty power amplifier.

Figure 15 .
Figure 15.The scattering parameters of the proposed DPA.

Figure 14 .
Figure 14.Completely layout design of the proposed Doherty power amplifier.

Figure 14 .
Figure 14.Completely layout design of the proposed Doherty power amplifier.

Figure 15 .
Figure 15.The scattering parameters of the proposed DPA.

Figure 15 .
Figure 15.The scattering parameters of the proposed DPA.

Figure 16 .
Figure 16.The results of the designed DPA.(a) Large-signal gain and output power.(b) PAE and DE, in terms of input power.

Figure 17 .
Figure 17.Drain efficiency and PAE versus input power for non-Doherty (class AB) bias conditions.

Figure 16 .
Figure 16.The results of the designed DPA.(a) Large-signal gain and output power.(b) PAE and DE, in terms of input power.

Figure 16 .
Figure 16.The results of the designed DPA.(a) Large-signal gain and output power.(b) PAE and DE, in terms of input power.

Figure 17 .
Figure 17.Drain efficiency and PAE versus input power for non-Doherty (class AB) bias conditions.Figure 17.Drain efficiency and PAE versus input power for non-Doherty (class AB) bias conditions.

Figure 17 .
Figure 17.Drain efficiency and PAE versus input power for non-Doherty (class AB) bias conditions.Figure 17.Drain efficiency and PAE versus input power for non-Doherty (class AB) bias conditions.

Figure 18 .
Figure 18.Simulated time-domain curve of intrinsic drain voltage and current of the designed DPA.

Figure 18 .
Figure 18.Simulated time-domain curve of intrinsic drain voltage and current of the designed DPA.

Figure 19 .
Figure 19.Performance comparison of the three DPA designs versus input power: (a) large-signal gain, (b) output power, (c) drain efficiency, and (d) power-added efficiency at saturation.

Figure 19 .
Figure 19.Performance comparison of the three DPA designs versus input power: (a) large-signal gain, (b) output power, (c) drain efficiency, and (d) power-added efficiency at saturation.

Figure 22 .
Figure 22.Photograph of the fabricated post-harmonic suppression network.

Figure 22 .
Figure 22.Photograph of the fabricated post-harmonic suppression network.

Figure 24 .
Figure 24.Comparison of power reduction at harmonic frequencies between the proposed design (DPA with HS) and the conventional design (DPA without HS).

Figure 24 .
Figure 24.Comparison of power reduction at harmonic frequencies between the proposed design (DPA with HS) and the conventional design (DPA without HS).

Figure 24 .
Figure 24.Comparison of power reduction at harmonic frequencies between the proposed design (DPA with HS) and the conventional design (DPA without HS).

Figure 25 .
Figure 25.Spectrum in dBm for four harmonics for (a) output power, (b) output voltage, and (c) output current.

Figure 26 .
Figure 26.Steady-state time-domain output voltage and current waveform for proposed DPA.

Figure 25 .Figure 25 .
Figure 25.Spectrum in dBm for four harmonics for (a) output power, (b) output voltage, and (c) output current.

Figure 26 .
Figure 26.Steady-state time-domain output voltage and current waveform for proposed DPA.

Figure 26 .
Figure 26.Steady-state time-domain output voltage and current waveform for proposed DPA.

Table 1 .
Branch Impedances and Isolation Resistance with Sweep of Division Factor (Q).

Table 1 .
Branch Impedances and Isolation Resistance with Sweep of Division Factor (Q).

Table 1 .
Branch Impedances and Isolation Resistance with Sweep of Division Factor (Q).

Table 2 .
Summary of the performance of the three DPA designs.

Table 2 .
Summary of the performance of the three DPA designs.