An Auto Adjustable Transimpedance Readout System for Wearable Healthcare Devices

: The objective of this work was to design a versatile readout circuit for patch-type wearable devices consisting of a Transimpedance Ampliﬁer (TIA). The TIA performs Current to Voltage (I–V) conversion, the most widely used technique for amperometry and impedance measurement for various types of electrochemical sensors. The proposed readout circuit employs a digitally controllable feedback resistor ( R f ) technique in the TIA to improve accuracy, which can be utilized in a variety of electrochemical sensors within a current range of 0.1 µ A–100 µ A. It is designed to accommodate multiple sensors simultaneously to track multiple target analytes for high accuracy and versatile usage. The readout circuit consists of low power operational ampliﬁer (op–amp) and digital circuit blocks, is designed and fabricated with Magna 0.18 µ m Complementary Metal Oxide Semiconductor (CMOS) technology, which provides low power consumption and a high degree of integration. The design has a small size of 0.282 mm 2 and low power consumption of 0.38 mW with a 3.3 V power supply, which are desirable factors in wearable device applications.


Introduction
Wearable devices have emerged as powerful tools for environmental examination, healthcare devices, and motion recognition, despite some challenges such as miniaturization and low power while ensuring accuracy, that limit their widespread applicability as continuous monitoring systems of target information [1][2][3]. Especially with the current trend in an acceleration of global population aging, one-third of the population has been reported to be over 60 years of age in most regions by 2050, resulting in a high demand for healthcare wearable devices [4]. Since the immune response declines with age, the elderly might suffer from many more health risks, which requires healthcare workforces [5]. The wearable devices could be used to address some of the challenges related to detecting and managing adverse health conditions in aging populations, and to reducing ubiquitous healthcare issues [6,7]. As the demand for wearable devices for healthcare continues to rise, it has generated a booming market, and the companies are now seeing the opportunities of supplying wearable healthcare technologies to their consumers as beneficial. So far, wristwatches, gloves, patches, headbands, eyeglasses, and necklaces have been reported as types of wearable devices [8][9][10][11][12][13][14][15][16]. The wristwatch is the most affordable and widely invented wearable device type since it can provide good wearing comfort and obtain information from the skin. At the same time, it does not require flexibility other than the wristband part, which indicates that commercial-off-the-shelf (COTS) can be utilized as components to build readout circuits for interpreting sensors' information. As a result, we can find watch type of commercial products easily available in the market, such as the Apple Watch (Apple Inc., Cupertino, CA, USA), Fitbit (Fitbit, San Francisco, CA, USA), Samsung Galaxy Watch (Samsung Electronics, Suwon, Korea), and so on. Those mentioned

Design of Readout Circuit
Several high-performance current measurement circuit topologies are discussed in [26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41]. One of the common architectures for low current measurements is based on an integrator followed by a differentiator [34][35][36]. This structure provides a high gain and linear response at the cost of a low dynamic range of about 5 decades and takes a long time to accumulate the small current into a measurable voltage signal. Moreover, the integrator is prone to saturation and requires either additional DC current offset compensation or an active reset switch. Another well-known architecture is a logarithmic I-V converter, which works on the principle of compression of the input signal and utilizes an exponential device as a feedback element in the Transimpedance Amplifier (TIA) [27][28][29]. Although the logarithmic amplifier can provide a very wide dynamic range, it often comprises linearity of the output response. Furthermore, it is accompanied by a significant temperature sensitivity and nonlinearity that are difficult to address without the use of an additional temperature compensation circuit. Few other current measurement circuits rely on capacitive TIA (C-TIA) to perform current-to-frequency (I-F) conversion [33]; timed integrators with a switched capacitor network or correlated double sampler [37][38][39][40][41]; variable gain amplifiers with external voltage control or digital gain control [26,31,32]; and use of large feedback resistor realized as an onchip active pseudo resistor or off-chip external resistor. In the case where a pseudo resistor is realized using a transistor, the resistance is inversely proportional to the input current, which leads to a variable current gain and bandwidth that is undesirable. Among all these architectures, the simple and straightforward approach is a shunt feedback amplifier, based on a voltage inverting amplifier with a feedback resistor (R f ), also called the resistive TIA (R-TIA) [35,[42][43][44] but suffers from a relatively low dynamic range. Here, the R f directly affects the dynamic range of the TIA, and if it is employed to measure low current, the R f must be large enough to obtain high gain. Thus, there is a trade-off between achieving high dynamic range and performing low current measurement, which can be resolved using a variable R f . In this paper, an I-V converter with a digitally controlled programmable gain is proposed to obtain different gain settings to vary the transimpedance gain as a function of the input signal range. The programmable current gain setting enables to achieve a higher overall input dynamic range. Figure 1 illustrates a conventional R-TIA which consists of an operational amplifier (op-amp) with a R f . In this configuration, a single R f is connected between an inverting input and output pin of the op-amp [45].
tegrator is prone to saturation and requires either additional DC current offset compensation or an active reset switch. Another well-known architecture is a logarithmic I-V converter, which works on the principle of compression of the input signal and utilizes an exponential device as a feedback element in the Transimpedance Amplifier (TIA) [27][28][29]. Although the logarithmic amplifier can provide a very wide dynamic range, it often comprises linearity of the output response. Furthermore, it is accompanied by a significant temperature sensitivity and nonlinearity that are difficult to address without the use of an additional temperature compensation circuit. Few other current measurement circuits rely on capacitive TIA (C-TIA) to perform current-to-frequency (I-F) conversion [33]; timed integrators with a switched capacitor network or correlated double sampler [37][38][39][40][41]; variable gain amplifiers with external voltage control or digital gain control [26,31,32]; and use of large feedback resistor realized as an on-chip active pseudo resistor or off-chip external resistor. In the case where a pseudo resistor is realized using a transistor, the resistance is inversely proportional to the input current, which leads to a variable current gain and bandwidth that is undesirable. Among all these architectures, the simple and straightforward approach is a shunt feedback amplifier, based on a voltage inverting amplifier with a feedback resistor ( ), also called the resistive TIA (R-TIA) [35,[42][43][44] but suffers from a relatively low dynamic range. Here, the directly affects the dynamic range of the TIA, and if it is employed to measure low current, the must be large enough to obtain high gain. Thus, there is a trade-off between achieving high dynamic range and performing low current measurement, which can be resolved using a variable . In this paper, an I-V converter with a digitally controlled programmable gain is proposed to obtain different gain settings to vary the transimpedance gain as a function of the input signal range. The programmable current gain setting enables to achieve a higher overall input dynamic range. Figure 1 illustrates a conventional R-TIA which consists of an operational amplifier (op-amp) with a . In this configuration, a single is connected between an inverting input and output pin of the op-amp [45]. The voltage output ( ) of this configuration can be obtained as where indicates a sensor current output, is a reference voltage for biasing the op−amp, and is voltage obtained at the TIA output. Thus, by measuring the , the unknown value of can be calculated by Equation (1). It is important to select the appropriate value of the to obtain an accurate sensor output in the R-TIA configuration, and a digitizing process is essential to process sensor output. If the value of the is too large, the will be clipped due to the op-amp output swing limitation, while if the value of the is too small, the is not sufficiently large enough to be detected by an Analog-to-Digital Converter (ADC), which is also related to the resolution of the ADC. For instance, when the is fixed to 10 KΩ, to differentiate between 1 µA and 0.91 µA, the ADC should be able to interpret the 0.9 µV difference based on Equation (1) which The voltage output (V out ) of this configuration can be obtained as where I sen indicates a sensor current output, V re f is a reference voltage for biasing the op-amp, and V out is voltage obtained at the TIA output. Thus, by measuring the V out , the unknown value of I sen can be calculated by Equation (1). It is important to select the appropriate value of the R f to obtain an accurate sensor output in the R-TIA configuration, and a digitizing process is essential to process sensor output. If the value of the R f is too large, the V out will be clipped due to the op-amp output swing limitation, while if the value of the R f is too small, the V out is not sufficiently large enough to be detected by an Analog-to-Digital Converter (ADC), which is also related to the resolution of the ADC. For instance, when the R f is fixed to 10 KΩ, to differentiate between 1 µA and 0.91 µA, the ADC should be able to interpret the 0.9 µV difference based on Equation (1) which is challengeable. Meanwhile, if the R f is set to 100 KΩ, the op-amp output is clipped when I sen is 100 µA, due to the op-amp's output swing limitation. Thus, the R-TIA with digitally adjustable R f controlled by a Microcontroller Unit (MCU) is developed in this work to resolve the discussed issues. Based on the V out range, the R f value will be altered by the MCU automatically to avoid the clipping problem and the situation that the V out difference is going below the ADC's detectable voltage. The readout circuit is designed to accommodate five sensors with a current range from 0.1 µA to 100 µA in a single platform. The target error rate is less than 1% while ensuring minimized size and power consumption. The proposed design is implemented using Magna 0.18 µm CMOS technology to provide an optimal performance between the power consumption and the speed. The technology uses 3.3 V as a power supply, provides a resistor with 2% tolerance, and offers a pad with a size of 60 µm × 60 µm for external connection.

Design of Digitally Adjustable TIA
A block diagram of the proposed readout circuit is shown in Figure 2, where the I sen indicates each sensor's current output. The circuit consists of an analog multiplexer (AMUX), digitally adjustable TIA, and inverting amplifier. At the input of the circuit, a 5 × 1 AMUX is implemented to interface with five sensors in a single chip. The heart of the proposed readout circuit is a digitally adjustable R-TIA, which is embarked for accurate and wide-ranged I-V conversion. It is comprised of an op-amp and a digitally controlled feedback stage for varying the R f to cover a wide sensor current range. The feedback stage includes an 8 × 1 AMUX and a resistor array containing eight different resistors. Since the R-TIA output is inverted, an additional inverting amplifier is embedded at the last stage to obtain the positive V out . An external MCU, "FreeSoC2 development board" (Cypress Semiconductors, San Jose, CA, USA) is utilized to control the selection bits (S 0~S5 ) of the AMUXs by general purpose input/output (GPIO) pins. The V out is converted to digital form using an internal 16-bit sigma-delta ADC integrated into the MCU. is challengeable. Meanwhile, if the is set to 100 KΩ, the op-amp output is clipped when is 100 µA, due to the op−amp's output swing limitation. Thus, the R-TIA with digitally adjustable controlled by a Microcontroller Unit (MCU) is developed in this work to resolve the discussed issues. Based on the range, the value will be altered by the MCU automatically to avoid the clipping problem and the situation that the difference is going below the ADC's detectable voltage. The readout circuit is designed to accommodate five sensors with a current range from 0.1 µA to 100 µA in a single platform. The target error rate is less than 1% while ensuring minimized size and power consumption. The proposed design is implemented using Magna 0.18 µm CMOS technology to provide an optimal performance between the power consumption and the speed. The technology uses 3.3 V as a power supply, provides a resistor with 2% tolerance, and offers a pad with a size of 60 µm × 60 µm for external connection.

Design of Digitally Adjustable TIA
A block diagram of the proposed readout circuit is shown in Figure 2, where the indicates each sensor's current output. The circuit consists of an analog multiplexer (AMUX), digitally adjustable TIA, and inverting amplifier. At the input of the circuit, a 5 × 1 AMUX is implemented to interface with five sensors in a single chip. The heart of the proposed readout circuit is a digitally adjustable R-TIA, which is embarked for accurate and wide-ranged I-V conversion. It is comprised of an op-amp and a digitally controlled feedback stage for varying the to cover a wide sensor current range. The feedback stage includes an 8 × 1 AMUX and a resistor array containing eight different resistors. Since the R-TIA output is inverted, an additional inverting amplifier is embedded at the last stage to obtain the positive . An external MCU, "FreeSoC2 development board" (Cypress Semiconductors, San Jose, CA, USA) is utilized to control the selection bits ( ~ ) of the AMUXs by general purpose input/output (GPIO) pins. The is converted to digital form using an internal 16-bit sigma-delta ADC integrated into the MCU.

OP−AMP Design
A two-stage op-amp comprising of a bias stage, differential amplifier stage, and common source amplifier stage is designed, as shown in Figure 3. The two-stage op-amp topology usually has the advantage of high gain, high linearity, high output swing, low noise, and good bandwidth. The differential gain stage is introduced, where forms differential pair with and a current mirror ( , ), as the first stage of the op−amp. The minimum transistor length used in the design is 1 μm and the differential transistor pair ( , ) width is chosen as 32 μm. A differential input signal applied across the two

OP-AMP Design
A two-stage op-amp comprising of a bias stage, differential amplifier stage, and common source amplifier stage is designed, as shown in Figure 3. The two-stage op-amp topology usually has the advantage of high gain, high linearity, high output swing, low noise, and good bandwidth. The differential gain stage is introduced, where M 1 forms differential pair with M 2 and a current mirror (M 7 , M 8 ), as the first stage of the op-amp. The minimum transistor length used in the design is 1 µm and the differential transistor pair (M 1 , M 2 ) width is chosen as 32 µm. A differential input signal applied across the two input terminals (V − , V + ) will be amplified according to the gain of the differential stage. By utilizing current mirror active load transistors (M 7 , M 8 ), it can have a very large output impedance. The second stage is consisted of M 5 and M 6 transistors with size of 220 µm and 120 µm, respectively, which is a common source amplifier for high output swing as the final stage amplifier [42,46]. The transistor pair (M 3 , M 4 ) is designed as 42 µm and all the remaining transistor widths are selected as 15 µm. The cascode current source technique has been implemented to reduce the voltage variations across current source transistors, thus, it can provide accurate current [47]. The first stage gain of the designed op-amp can be represented using Equation (2).
By utilizing current mirror active load transistors ( , ), it can have a ver impedance. The second stage is consisted of and transistors with s and 120 μm, respectively, which is a common source amplifier for high ou the final stage amplifier [42,46]. The transistor pair ( , ) is designed as the remaining transistor widths are selected as 15 μm. The cascode curren nique has been implemented to reduce the voltage variations across curren sistors, thus, it can provide accurate current [47]. The first stage gain of the amp can be represented using Equation (2). The second stage gain can be expressed as per Equation (3).
By combining Equations (2) and (3), the total gain of the designed op described as × || ) || ) Figure 4 shows the op-amp gain and phase plot during the simulatio the op−amp, of 1.65 V is given to . The op-amp achieves a 97.5 dB g degrees phase margin as depicted in Figure 4. The second stage gain can be expressed as per Equation (3).
By combining Equations (2) and (3), the total gain of the designed op-amp can be described as Figure 4 shows the op-amp gain and phase plot during the simulation. For biasing the op-amp, V re f of 1.65 V is given to M 2 . The op-amp achieves a 97.5 dB gain and 64.05 degrees phase margin as depicted in Figure 4.

Feedback Stage Design
The feedback stage is made up of an 8 × 1 AMUX and resistor array, which includes 10 KΩ, 50 KΩ, 100 KΩ, 200 KΩ, 400 KΩ, 600 KΩ, 800 KΩ, and 1 MΩ resistors. The AMUX is connected in a series with the resistor array to vary the R f by controlling the selection bits of the AMUX, as shown in Figure 5. Each of the I in in Figure 5 indicates the sensor output current (I sen ) that passed through the R f in the resistor array. Depending on the current range of the sensor, the R f value will be altered to avoid the op-amp output swing limitation or accuracy issue due to the ADC resolution. Table 1 shows the sensor current range and the matched value of R f , as per the AMUX selection bits (S 2 , S 1 , S 0 ).

Feedback Stage Design
The feedback stage is made up of an 8 × 1 AMUX and resistor array, which in 10 KΩ, 50 KΩ, 100 KΩ, 200 KΩ, 400 KΩ, 600 KΩ, 800 KΩ, and 1 MΩ resistors. The A is connected in a series with the resistor array to vary the by controlling the se bits of the AMUX, as shown in Figure 5. Each of the in Figure 5 indicates the output current( ) that passed through the in the resistor array. Depending current range of the sensor, the value will be altered to avoid the op-amp swing limitation or accuracy issue due to the ADC resolution. Table 1 shows the current range and the matched value of , as per the AMUX selection bits (S , S

Feedback Stage Design
The feedback stage is made up of an 8 × 1 AMUX and resistor array, which includes 10 KΩ, 50 KΩ, 100 KΩ, 200 KΩ, 400 KΩ, 600 KΩ, 800 KΩ, and 1 MΩ resistors. The AMUX is connected in a series with the resistor array to vary the by controlling the selection bits of the AMUX, as shown in Figure 5. Each of the in Figure 5 indicates the sensor output current( ) that passed through the in the resistor array. Depending on the current range of the sensor, the value will be altered to avoid the op-amp output swing limitation or accuracy issue due to the ADC resolution. Table 1 shows the sensor current range and the matched value of , as per the AMUX selection bits (S , S , S ).    The AMUX is a combinational logic circuit designed to switch one of the several analog input lines through to a single common output line and is controlled by the selection bits. The designed AMUX is composed of: (a) Combinational logic acting as a decoder for the selection bits; and (b) Transmission Gates (TG) for transferring signal from input to output. The combinational logic for decoder is realized with NOT gates and three input NAND gates. The TG, also called as analog switch, can selectively block or pass a signal from its input to output. The TG is comprised of a p-channel metal-oxide semiconductor (PMOS) transistor and a n-channel metal-oxide semiconductor (NMOS) transistor pair. The utilized gates' schematics are illustrated in Figure 6. The control gate of TG is biased by the control signal in a complementary manner, so both transistors are either on or off. The decoder output (d o~d7 ) is connected to the control signal of the NMOS transistor, and the inverted decoder output (d 0~d7 ) is connected to the control signal of the PMOS transistor. An output expression (Out) of the AMUX is represented in Equation (5) and the full schematic of the AMUX is presented in Figure 7.
The AMUX is a combinational logic circuit designed to switch one of the several analog input lines through to a single common output line and is controlled by the selection bits. The designed AMUX is composed of: (a) Combinational logic acting as a decoder for the selection bits; and (b) Transmission Gates (TG) for transferring signal from input to output. The combinational logic for decoder is realized with NOT gates and three input NAND gates. The TG, also called as analog switch, can selectively block or pass a signal from its input to output. The TG is comprised of a p-channel metal-oxide semiconductor (PMOS) transistor and a n-channel metal-oxide semiconductor (NMOS) transistor pair. The utilized gates' schematics are illustrated in Figure 6. The control gate of TG is biased by the control signal in a complementary manner, so both transistors are either on or off. The decoder output ( ~ ) is connected to the control signal of the NMOS transistor, and the inverted decoder output ( ~ ) is connected to the control signal of the PMOS transistor. An output expression (Out) of the AMUX is represented in Equation (5) and the full schematic of the AMUX is presented in Figure 7.

Simulation Results
The proposed readout circuit shown in Figure 2 is designed in CMOS 0.18 µm technology utilizing the "Cadence" tool (Cadence Design Systems, San Jose, CA, USA). Figure   Figure 7. Schematic of an analog multiplexer (AMUX).

Simulation Results
The proposed readout circuit shown in Figure 2 is designed in CMOS 0.18 µm technology utilizing the "Cadence" tool (Cadence Design Systems, San Jose, CA, USA). Figure 8a shows the layout of the complete chip, and Figure 8b illustrates the layout of the proposed architecture, which is the circuit marked as 'A' in Figure 8a. The designed circuit occupies an area of 1030 × 620 µm 2 , including the pads and 580 × 487 µm 2 , excluding the pads. Figure 9 shows the photo of the fabricated chip. In order to verify the proposed circuit, post simulation of the R-TIA has been conducted. As an example, the simulations were plotted in Figure 10 where R f is 10 KΩ, 100 KΩ, and 1 MΩ, respectively, which cover the minimum and the maximum target range. The Y-axis of the graph in Figure 10 indicates V out in unit of volts, while the X-axis represents I sen in units of µA. The I sen ranges used for simulations are selected based on Table 1 Thus, the designed TIA shows a phase margin higher than 45 • with all R f values in Table 1 indicating the stability of the TIA.

IC Test Results
The fabricated chip is packaged with a quad flock package in order to test the chip, and the chip socket is soldered onto an adapter board. The chip is then inserted inside the

IC Test Results
The fabricated chip is packaged with a quad flock package in order to test the chip, and the chip socket is soldered onto an adapter board. The chip is then inserted inside the socket and tested. Figure 11 illustrates the block diagram of the experimental test setup. An "Agilent power supply" (Keysight Technologies, Santa Rosa, CA, USA) is connected to the V DD pin (3.3 V) and the V re f pin (1.65 V) to power the circuit. To measure the V out , a 16-bit sigma-delta ADC embedded in the "FreeSoC2 development board" is utilized. A 16-bit ADC should be able to differentiate 50 µV difference when V DD is 3.3 V. However, the last two or three bits are generally not trustable due to the error from non-ideal characteristics of the ADC, environmental condition, and offset voltage [48]. Thus, a 16-bit ADC can differentiate 400 µV difference in general. In this work, an algorithm has been developed in the MCU firmware, which can alter the automatically, depending on the range. Figure 12 explains the firmware flowchart of the algorithm. Initially, the values are stored in the MCU memory. Once the MCU is on, it selects the AMUX selection bits ( , , ) as (1, 1, 1), which indicates that is 1 MΩ and starts to read the ADC voltage. To avoid the clipping issue due to the op-amp output swing limitations, if the ADC value is larger than 3.2 V, it alters the with a smaller value until the reaches 10 KΩ. If not, the MCU calculates the value using Equation (1). With this developed firmware, the of the R-TIA can be changed automatically depending on the range, so that the proposed circuit can cover a wide current range of the sensor. In this work, an algorithm has been developed in the MCU firmware, which can alter the R f automatically, depending on the I sen range. Figure 12 explains the firmware flowchart of the algorithm. Initially, the R f values are stored in the MCU memory. Once the MCU is on, it selects the AMUX selection bits (S 2 , S 1 , S 0 ) as (1, 1, 1), which indicates that R f is 1 MΩ and starts to read the ADC voltage. To avoid the clipping issue due to the op-amp output swing limitations, if the ADC value is larger than 3.2 V, it alters the R f with a smaller value until the R f reaches 10 KΩ. If not, the MCU calculates the I sen value using Equation (1). With this developed firmware, the R f of the R-TIA can be changed automatically depending on the I sen range, so that the proposed circuit can cover a wide current range of the sensor.
The comparison of the post simulation results and the measurement results during the IC test experiment are recorded in Figure 13, which shows a linear V out versus I sen from 0.1 µA to 100 µA for different values of R f . The error in Figure 13 was calculated by below Equation (6) where the V measured is the measured voltage at the ADC and V post simulation is the voltage obtained from post simulation. Figure 13 demonstrates an adequately similar output with a slight offset because of the R f error, due to the process resistance tolerance of 2 %, which is fairly linear and can be corrected using the offset correction in the MCU. Thus, the proposed circuit designed in IC is verified that it can cover a wide sensor current range from 0.1 µA to 100 µA. The error rate comparison between the conventional R-TIA with the fixed R f and proposed R-TIA with digitally adjustable R f is conducted and presented in Table 2. For comparison, the R f of the conventional R-TIA is fixed to 10 KΩ, while the R f in the proposed design is altered based on the I sen range. The measured I sen in Table 2 are extracted from calculation based on Equation (1). In the case where I sen is 100 µA, since both methods are using the same R f value, they exhibit a similar error rate. However, when the I sen is getting smaller, the proposed TIA shows a much better error rate than the conventional R-TIA, as illustrated in the comparison results in Table 2. In this work, an algorithm has been developed in the MCU firmware, which can alter the automatically, depending on the range. Figure 12 explains the firmware flowchart of the algorithm. Initially, the values are stored in the MCU memory. Once the MCU is on, it selects the AMUX selection bits ( , , ) as (1, 1, 1), which indicates that is 1 MΩ and starts to read the ADC voltage. To avoid the clipping issue due to the op-amp output swing limitations, if the ADC value is larger than 3.2 V, it alters the with a smaller value until the reaches 10 KΩ. If not, the MCU calculates the value using Equation (1). With this developed firmware, the of the R-TIA can be changed automatically depending on the range, so that the proposed circuit can cover a wide current range of the sensor.
where the is the measured voltage at the ADC and is the voltage obtained from post simulation. Figure 13 demonstrates an adequately similar output with a slight offset because of the error, due to the process resistance tolerance of 2 %, which is fairly linear and can be corrected using the offset correction in the MCU. Thus, the proposed circuit designed in IC is verified that it can cover a wide sensor current range from 0.1 µA to 100 µA. The error rate comparison between the conventional R-TIA with the fixed and proposed R-TIA with digitally adjustable is conducted and presented in Table 2. For comparison, the of the conventional R-TIA is fixed to 10 KΩ, while the in the proposed design is altered based on the range. The measured in Table 2 are extracted from calculation based on Equation (1). In the case where is 100 µA, since both methods are using the same value, they exhibit a similar error rate. However, when the is getting smaller, the proposed TIA shows a much better error rate than the conventional R-TIA, as illustrated in the comparison results in Table 2.   A comparison of the proposed readout with existing variable gain TIA architectures is presented in Table 3. Although a wide dynamic range is achieved by the TIA in several architectures, these solutions cannot achieve a linear output across the entire dynamic range. In contrast, the presented TIA showed good linearity throughout the targeted dynamic range, providing a relatively acceptable range. Furthermore, the proposed readout circuit is accomplished by a low power consumption of 0.38 mW and a small area of 0.282 mm 2 , which are important factors for wearable patch type healthcare devices.

Conclusions
In this work, the readout circuit consisting of a digitally adjustable R-TIA is designed and fabricated in a 0.18 µm CMOS process for various sensors that have current output. The proposed readout circuit is designed to adopt multiple electrochemical sensors for multifunctional wearable healthcare devices. The auto-adjustable R-TIA is developed to cover a wide range of I sen by algorithm implemented in the MCU, which is altering the R f value based on the current range. The R-TIA consists of the op-amp and feedback stage. As the R-TIA internal block, the two-stage op-amp is designed that is comprised of a bias stage, differential amplifier stage, and common source amplifier stage; it achieved a 97.5 dB gain and 64.05 degrees phase margin. To make the R f adjustable, a resistor array with an 8 × 1 AMUX is embedded in the R-TIA circuit. The total area of the proposed readout circuit is 1030 µm × 620 µm, including the pads, and its power consumption is 0.38 mW with a power supply of 3.3 V. The measurement result shows that the proposed circuit can cover a wide range of sensor current from 0.1 µA to 100 µA and has an error rate less than 1%.

Data Availability Statement:
The datasets generated from the current study are available from the corresponding author on reasonable request.

Conflicts of Interest:
The authors declare no conflict of interest.