A Novel Single-Stage Common-Ground Transformerless Buck–Boost Inverter

: In this article, a novel single-stage transformerless buck–boost inverter is introduced. The proposed inverter can share a common ground between the DC input side and the grid; this leads to having a zero-leakage current. The proposed inverter also provides the buck and boost voltage capabilities. Additionally, the power switches are operated at high frequency in the half-cycle of the sinusoidal wave, so the efﬁciency of the proposed inverter can be improved. Operating analysis, design consideration, comparison, and simulation study are presented. Finally, a 500 W laboratory prototype is also built to conﬁrm the correctness and feasibility of the proposed inverter.


Introduction
In recent years, the nearly exhausted fossil fuels and environmental deterioration have promoted the development of renewable energy sources such as wind power, photovoltaic (PV), fuel cells, and ocean waves [1][2][3][4]. Among these renewable energy sources, the PV market has several advantages, which include being inexhaustible, as well as its easy availability and pollution-free operation. Moreover, the main technological evolution for the PV system is the inverter. The inverter can be divided into two types with transformer topologies [5][6][7] or transformerless topologies [8][9][10]. Although transformer-based inverters can provide galvanic isolation and protection, they have undesirable properties such as high cost and weight, with additional losses [9,10]. On the other hand, transformerless inverters have reduced costs and sizes, and improved efficiency, but the isolation between the PV panel and the inverter system leads to the occurrence of leakage current. This leakage current causes a rise in harmonic distortion, in both output voltage and current, which also results in electromagnetic interference between the PV system and grid. To eliminate leakage current, the DC current injection from the inverter should also be reduced, as presented in the standards IEEE 1547 and IEC 61727 [11,12]. Moreover, the transformerless inverter topologies can be classified into two groups-namely, two-stage configurations and single-stage configurations. In two-stage configurations, the power processing is divided into two stages. A DC-DC boost converter is added between the inverter side and DC input power supply side, which boosts a low-voltage input to the high voltage required for the second stage [13][14][15]. The next stage is an inverter that converts DC voltage to AC voltage to connect with the grid. Two-stage transformerless inverter topologies can have some disadvantages, including low efficiency, increased cost, and complexity control in a two-stage configuration. In contrast, single-stage configurations have all the functions of boosting ability and maximum power extraction, as well as DC-AC conversion. Compared with two-stage configurations, single-stage configurations have more benefits, including compactness, lower device count, lower costs, and greater efficiency [16]. From this point of view, single-stage inverters are reported in the literature, and their comprehensive review is given in [17][18][19][20][21][22][23][24][25][26][27]. Common-ground transformerless inverter topologies were introduced in [21][22][23][24][25][28][29][30], which directly connect the ground of the grid to the negative of the DC input source. The common-mode voltage is equal to zero, and it also protects against any high-frequency content. Therefore, there is no common-mode leakage current in the presented topologies.
In order to improve the boosting capability and provide common ground with singlestage configuration, single-stage, common-ground transformerless inverters have been used in [23] without a continuous input current. However, the power switches are operated at high frequency. This leads to an increase in the switching loss of the inverter. Similarly, a buck-boost inverter in [24] with five switches is proposed to achieve the common-ground condition and wide buck-boost voltage operation. However, three switches are operated at a high switching frequency in the half-line period. The single-phase transformerless gridconnected PV inverter introduced in [25,26] also focuses on a doubly grounded inverter with single-stage conversion and uses fewer components. Nevertheless, the disadvantage of this inverter is also the high switching frequency of its power switches. To further improve the voltage gain, a novel step-up transformerless inverter is presented in [27]. This inverter can provide the common ground between the output and input sides with a single stage. However, it requires more switches, which increases the size and cost of the inverter package.
In this article, a novel single-stage common-ground transformerless buck-boost inverter (CGBBI) is proposed to eliminate leakage current elimination and achieve voltage boosting capability. Moreover, the PWM control method of the proposed inverter can reduce the high switching loss on semiconductor devices. The remainder of this article is organized as follows: First, the inverter configuration, PWM control method, and operating principle of the proposed inverter are presented in Section 2. Design guidelines of the devices are given in Section 3. A comparative study is provided in Section 4, drawing on other existing common-ground buck-boost inverter topologies. Simulation and experimental results are presented in Section 5 to evaluate the accurate performance of the proposed inverter. Finally, the conclusions of the study are drawn in Section 6.

Derivation of Proposed CGBBI
The proposed CGBBI topology is shown in Figure 1. The major characteristic of the proposed CGBBI topology is to have a common point between the output side and the negative terminal of the input DC power supply, which avoids the leakage current [9]. The proposed CGBBI topology includes five power switches S 1 -S 5 , three diodes D 1 -D 3 , two inductors L 1 -L 2 , two capacitors C 1 -C 2 , and one output filter inductor L f . It can be seen that the proposed CGBBI topology is composed of one buck-boost module, one boost module, and one power switch operating at low frequency. The buck-boost module comprises three power switches S 1 -S 3 , two diodes D 1 -D 2 , and a pair of L 1 and C 1 . Similarly, the boost module has one power switch S 4 , one diode D 3 , one inductor L 2 , and one capacitor C 2 . Figure 2 presents the PWM control method for the proposed CGBBI topology. When output voltage v o is higher than 0, switch S 3 is turned on, and S 4 and S 5 are turned off. However, switches S 1 and S 2 are turned on/off alternately at high frequency. When the output voltage v o is negative, three switches S 1 , S 2 , and S 3 are turned off, while S 5 is turned on. In this case, only switch S 4 is operated at high frequency during this negative half-line cycle.

PWM Control Method for the Proposed CGBBI Topology
Boost module Figure 1. Proposed single-stage common-ground buck-boost inverter. Figure 2 presents the PWM control method for the proposed CGBBI topology. When output voltage vo is higher than 0, switch S3 is turned on, and S4 and S5 are turned off. However, switches S1 and S2 are turned on/off alternately at high frequency. When the output voltage vo is negative, three switches S1, S2, and S3 are turned off, while S5 is turned on. In this case, only switch S4 is operated at high frequency during this negative half-line cycle.    Figure 2 presents the PWM control method for the proposed CGBBI topology. When output voltage vo is higher than 0, switch S3 is turned on, and S4 and S5 are turned off. However, switches S1 and S2 are turned on/off alternately at high frequency. When the output voltage vo is negative, three switches S1, S2, and S3 are turned off, while S5 is turned on. In this case, only switch S4 is operated at high frequency during this negative half-line cycle.

Operating of the Proposed CGBBI Topology
Interval 1 ([0, t 1 ] or [t 2 , t 3 ]): This interval appears when the voltage V in is higher than v o . In this case, only the buck-boost module is operated. Switch S 3 is turned on, while S 2 , S 4 , and S 5 are turned off. It can be seen that only switch S 1 is turned on and off at high frequency. Voltage v C1 is equal to v o . In terms of the inductor current, i L1 approximates the output current, while i L2 is zero.
Mode 1 (Figure 3a): Switch S 1 is turned off, and diodes D 1 -D 2 are forward biased. Inductor L 1 is connected to the capacitor C 1 and load, to which it charges energy. In this mode, capacitor C 1 provides energy to the load and maintains the constant output voltage across the load. We have inductor current iL1 increases linearly. The equations in this mode can be derived as follows: By applying voltage-second balance condition to an inductor L1, the relationship between vo and Vin can be obtained as where d1 is the duty ratio of S1. Mode 2 ( Figure 3b): Switch S 1 is turned on, diode D 1 is reverse biased and D 2 is forward biased. Inductor L 1 is charged by an input voltage V in , capacitor C 1 , and the load. The inductor current i L1 increases linearly. The equations in this mode can be derived as follows: By applying voltage-second balance condition to an inductor L 1 , the relationship between v o and V in can be obtained as where d 1 is the duty ratio of S 1 . Interval 2 ([t 1 , t 2 ]): This interval appears when the input voltage V in is lower than v o . In this case, only the buck-boost module operates. Switch S 1 is turned on, while S 4 and S 5 are kept off. Only switch S 2 is turned on and off at high frequency. Voltage v C1 is equal to v o , while inductor current i L1 is larger than output current, and inductor current i L2 is zero.
Mode 1 (Figure 4a): Switch S 2 in the buck-boost converter is turned on. Consequently, diodes D 1 and D 2 are reverse biasED. The voltage in inductor L 1 equals the input voltage V in . Inductor current i L1 increases linearly, and capacitor C 1 charges the load. The related equations are as follows: Mode 2 ( Figure 4b): Switch S2 is turned off, diode D1 is reverse biased, and D2 is forward biased. The power supply and inductor L1 charge energy to filter the capacitor and the load, so capacitor C1 is charged, and inductor current iL1 decreases linearly. We have The relationship between vo and Vin can be obtained from (4) and (5).
where d2 is the duty ratio of S2. Mode 2 ( Figure 4b): Switch S 2 is turned off, diode D 1 is reverse biased, and D 2 is forward biased. The power supply and inductor L 1 charge energy to filter the capacitor and the load, so capacitor C 1 is charged, and inductor current i L1 decreases linearly. We have The relationship between v o and V in can be obtained from (4) and (5).
The output voltage is negative, and it can be observed that only the boost module operates in this interval. Switch S 5 is turned on and switches S 1 , S 2 , and S 3 are turned off. In this case, only switch S 4 is controlled at high frequency. Voltage v C1 is equal to output voltage v o . Capacitor voltage v C2 is the total voltage of input voltage and output voltage, while inductor current i L1 is equal to 0, and inductor current i L2 is higher than the output current.
Mode 1 (Figure 5a): Switch S 4 is turned on, and diode D 3 is reverse biased in this mode. Inductor L 2 is charged from the input voltage, and the inductor current i L2 increases linearly. The capacitor C 2 transfers power to the load. The equations of this mode can be found as follows: The resulting duty cycles for the PWM modulation are visualized in Figure 2 and are calculated based on (12).
From (3), (6), (9), (12), the corresponding duty cycles for the PWM control method are defined in (13) and (14) as follows: According to (13) and (14), the maximum values of the corresponding duty cycles can be expressed as In order to determine the switching state in the PWM control method, shown in Figure 2, interval 2 is executed when the output voltage is higher than the input voltage. The values of t1 and t2 are calculated as follows: Mode 2 ( Figure 5b): Switch S 4 is turned off, and diode D 3 is forward biased. Inductor L 2 transfers energy to capacitor C 2 through diode D 3 . In this mode, the energy of inductor L 2 is also transferred to capacitor C 1 and the load through S 5 and D 3 , so the inductor current i L2 decreases linearly. We have (7) and (8) where d 4 is the duty ratio of S 4 .
When v o > 0, the voltage in capacitors C 1 and C 2 can be given as When v o < 0, the voltage in capacitors C 1 and C 2 can be rewritten as where V o is the peak value of output voltage, and ω is the angular frequency.
The relationship between the input voltage and the peak value of output voltage can be determined as follows: where M is the modulation index. The resulting duty cycles for the PWM modulation are visualized in Figure 2 and are calculated based on (12).
From (3), (6), (9), (12), the corresponding duty cycles for the PWM control method are defined in (13) and (14) as follows: According to (13) and (14), the maximum values of the corresponding duty cycles can be expressed as In order to determine the switching state in the PWM control method, shown in Figure 2, interval 2 is executed when the output voltage is higher than the input voltage. The values of t 1 and t 2 are calculated as follows:
where I o is the peak value of output current. According to (17), (18), and (12), the peak value of inductors L 1 and L 2 currents can be given by (19) and (20).
The inductors can be designed by using the equation of their current ripple, using (17), (18), and (15), while the peak-to-peak current ripple of inductors L 1 and L 2 can be defined by (21) and (22).
where f s denotes the switching frequency. According to (19)- (22), the inductance values of L 1 and L 2 can be calculated using (23) and (24) as follows: where x% is the inductors L 1 and L 2 ripple. Based on the maximum value of the current through the inductors L 1 , L 2 in (19) and (20). The stored energy of the inductor is given by The required area product of the inductor, as cited in [31,32], is where K u , B m , and J m are the core window of the fill factor, the amplitude of a magnetic flux density in the core, and the amplitude in current density of the winding conductor, respectively.

Selection of the Capacitors
Using the equations given in (15), the peak-to-peak voltage ripple of capacitors C 1 and C 2 can be defined as According to (27) and (28), the capacitance values of C 1 and C 2 are calculated as follows: where y% is the capacitors C 1 and C 2 ripple.

Selection of Switching Devices
The voltage stress across the switches and the diodes are given in (31)-(34).
The current stresses of switches S 1 -S 5 reach the maximum when the output current has its peak value (I o ), as given by (32)-(34).

Power Loss of Power Switches
The total power loss of the switches is equal to the sum of the conduction losses and switching losses, given by P S_tot = P S_con + P S_sw (35) Si.rms (36) where R dsi , t ri , and t fi are the on-state drain-source resistance, the turn-on and turn-off delay times of each MOSFET, respectively. The average and RMS current values through the switches are calculated as

Power Loss of Diodes
The power loss in the diodes includes conduction loss and reverse recovery loss. The power loss of the diodes is calculated as where V Fi , R Di , and Q rri are the forward voltage, the ON-state resistance, and the reverse recovery charge of each diode, respectively. The average and RMS current values through the switches are calculated as

Power Loss of Inductors
The power loss in the inductors includes the core loss and copper loss. The inductor loss is defined as P L = 2·k·B β · f α s ·A e ·l e + r L I 2 L1.rms + I 2

L2.rms
where B is the AC magnetic flux; f s is the frequency; A e is the core cross-sectional area; l e is the core mean magnetic path length; I L1.rms and I L2.rms are RMS currents of the inductors; r L is wire resistance. k, α, and β can be found in the manufacturer's datasheet. RMS values I L1.rms and I L2.rms can be calculated as

Power Loss of Capacitors
The power loss of capacitors is calculated as where r C1 and r C2 are the equivalent series resistance (ESR) of the C 1 and C 2 capacitors, respectively; I C1.rms and I C2.rms are the RMS capacitor currents and are calculated as

Comparison with Other Common-Ground Transformerless Inverters
Currently, the research literature is often focused on extending the buck-boost ability with higher efficiency, reducing the number of devices, and decreasing voltage stress across semiconductor devices. To show the potential capability of the proposed CGBBI topology, a comparative analysis between the proposed CGBBI topology and other common-ground transformerless inverters is presented in Table 1. It can be seen that the number of devices in the inverters proposed by [21,23] is lower than that of the inverters developed by [22,24,25], as well as the proposed CGBBI of this study. Moreover, the total number of devices in the proposed CGBBI is lower than that of the inverter in [22,24]. Having considered voltage stress across the power switches, the inverter developed by [22] and our proposed CGBBI have total switch voltage stress of 2V in + 4V o , which is lower than that of the inverter in [21,[23][24][25]. As is clear from Table 1, the number of high-frequency switches in each period in the proposed CGBBI topology is the least when compared with other inverters. When comparing diode voltage stress values, it is revealed that the inverter used in [25] and the proposed CGBBI have lower voltage stress values than the inverters in [22,24]. Compared with the inverters in [28,29], the proposed CGBBI requires a smaller number of power switches than that in [28,29] and the number of high-frequency switches in each period in the inverters developed by [28,29] is higher than that of the proposed CGBBI. In addition, the number of devices in the inverter used in [30] is equal to that of the proposed CGBBI. However, the total voltage stress of semiconductor devices in the proposed CGBBI is smaller than that in the inverter [30]. Considering the comparison in terms of component count, the voltage stress on semiconductor devices, and the number of high-frequency switches, the proposed CGBBI topology is a better solution than other common-ground buck-boost inverters mentioned in the literature. Table 1. Comparison between the proposed CGBBI topology and other common-ground transformerless inverters.

Simulation Results
The operating analysis of the proposed CGBBI topology was verified in the PSIM simulation version 9.1 [33]. The specifications for simulation are shown in Table 2. The drain-to-source on-resistance and body-diode threshold voltage of the MOSFETs S 1 , S 4 , and S 2 , S 3 , S 5 were set to 25.5 mΩ, 45 mΩ, and 8 mΩ, respectively. The forward voltage of diodes D 1 to D 3 was set to 1.12 V, 0.7 V, and 1.4 V, respectively. Figures 6 and 7 Figures 6 and 7. Moreover, the THD values of the output voltage waveforms were measured at 1.2% and 0.5% for the input voltage of 60 V and 240 V, respectively. It can be observed that the simulation results well agreed with the theoretical analysis. The conduction and switching losses of the proposed CGBBI, together with the simulation results, are shown in Table 3. It can be seen that the simulation results are close to the power loss analysis.

Experimental Results
A 500 W prototype circuit was fabricated and tested to verify the performance of the proposed CGBBI topology. The specifications for testing are also shown in Table 2. Figure 8 presents the experimental waveforms of the proposed CGBBI topology when the inverter operated in boost mode. The maximum value of the output voltage was boosted to 155 V from an input voltage of 60 V, which corresponds to M = 2.58. Figure 8a shows the input voltage, capacitor C 2 voltage, and output voltage for the load value of 24 Ω and filter inductor of 0.5 mH. The capacitor voltage V C2 was half-sinusoidal with DC offset V in in the positive half of the output cycle. Therefore, the peak voltage across the capacitor C 2 was approximately 220 V. In the negative half of the output cycle, the voltage across the capacitor C 1 was equal to the input voltage. The RMS value and THD of the output voltage waveform were 109 V and 1.6%, respectively. Figure 8b shows the voltage stress on switches S 1 , S 2 , and the current of inductor L 1 . Figure 8c shows the voltage stress on switches S 4 , S 5 , and the current of inductor L 2 . The peak currents of inductors L 1 and L 2 were about 16 A and 23 A, respectively. The high-frequency ripple of inductors L 1 and L 2 current were about 2.5 A and 3 A, respectively. Figure 8d shows the voltage stress on diode D 1 , the voltage stress on switch diodes S 3 -D 2 , and voltage stress on diode D 3 . Similarly, the proposed CGBBI topology was tested with an input voltage of 240 V, as shown in Figure 9. It can be seen that the experimental results are verified with the simulation and the theoretical analyses.   Moreover, the efficiency of the proposed CGBBI topology was measured at V in = 60 V and V in = 240 V. In this case, the output power of the inverter changed from 25 W to 500 W. When V in = 240 V, the proposed CGBBI topology achieved the highest efficiency of 96.1%. When the input voltage decreased to 60 V, the efficiency of the proposed CGBBI topology also achieved the highest efficiency of 95% at 350 W. From Figure 10, the EU efficiency of the proposed CGBBI topology can be obtained at 95.24%. The parameters for the power losses calculation are presented in Table 4. Figure 11 depicts the power loss distribution of the proposed CGBBI when V in = 60 V and 240 V, v o = 110 Vrms, and P o = 500 W. diode D1, the voltage stress on switch diodes S3-D2, and voltage stress on diode D3. Similarly, the proposed CGBBI topology was tested with an input voltage of 240 V, as shown in Figure 9. It can be seen that the experimental results are verified with the simulation and the theoretical analyses.  Moreover, the efficiency of the proposed CGBBI topology was measured at Vin = 60 V and Vin = 240 V. In this case, the output power of the inverter changed from 25 W to 500 W. When Vin = 240 V, the proposed CGBBI topology achieved the highest efficiency of 96.1%. When the input voltage decreased to 60 V, the efficiency of the proposed CGBBI topology also achieved the highest efficiency of 95% at 350 W. From Figure 10, the EU efficiency of the proposed CGBBI topology can be obtained at 95.24%. The parameters for

Conclusions
In this article, a common-ground buck-boost inverter topology was introduced, and its theoretical analysis was discussed in detail. In the proposed inverter, there is no common-mode leakage current because the ground of the output side is directly connected to the negative of the DC input power source. The proposed common-ground buck-boost inverter topology also provides buck-boost capability by controlling the duty cycle of power switches. In addition, few power switches operated with high-switching fre-

Conclusions
In this article, a common-ground buck-boost inverter topology was introduced, and its theoretical analysis was discussed in detail. In the proposed inverter, there is no common-mode leakage current because the ground of the output side is directly connected to the negative of the DC input power source. The proposed common-ground buck-boost inverter topology also provides buck-boost capability by controlling the duty cycle of power switches. In addition, few power switches operated with high-switching fre-

Conclusions
In this article, a common-ground buck-boost inverter topology was introduced, and its theoretical analysis was discussed in detail. In the proposed inverter, there is no commonmode leakage current because the ground of the output side is directly connected to the negative of the DC input power source. The proposed common-ground buck-boost inverter topology also provides buck-boost capability by controlling the duty cycle of power switches. In addition, few power switches operated with high-switching frequency, so the efficiency of the proposed inverter can be improved. Furthermore, the simulation and experimental verification were presented with a 500 W prototype inverter. The results highlighted that the proposed inverter can steadily operate and have good performance.