Fabrication and Characterization of Micrometer Scale Graphene Structures for Large-Scale Ultra-Thin Electronics

Graphene offers many useful properties that can revolutionize modern electronic devices. Specifically, it provides high charge carrier mobility in a mechanically robust, atomically thin form factor. Many of these properties are observed in graphene which is prepared from exfoliated graphite and processed with electron beam lithography. These processes are both time intensive and cost- prohibitive for the large-scale production necessary for use in consumer electronics. This work details the processing and characterization of commercially available graphene from chemical vapor deposition (CVD) on SiO2/Si and on hBN-layered SiO2/Si wafers using conventional photolithography on the 4″ wafer standard. The findings indicate that the CVD graphene films are resilient after processing even for lengths up to 1 mm. Electrical characterization via resistance measurements and the Hall Effect at room temperature clearly indicates the influence of the substrate material on the graphene’s electrical properties. At these length scales, graphene on SiO2 resembles that of a lightly doped semiconductor in terms of its carrier density (7.8 × 1015 cm−2), yet its carrier mobility (2.6 cm2/Vs) resembles that of a metal. Graphene on hBN/SiO2 has a carrier density of 8.2 × 1012 cm−2 and carrier mobility of 2.68 × 103 cm2/Vs—comparable to existing high-mobility semiconducting materials. CVD graphene and conventional photolithography does provide a cost-effective means for producing large form-factor graphene devices for low to moderate mobility applications and eventually for large-scale monolithic graphene electronics.


Introduction
The possibility of a room temperature high mobility semiconducting material as thin as a single atom was just a theoretical construct until the discovery of graphene in the early 2000s [1,2]. Since then, an entire field of research has been dedicated towards the study and application of graphene devices. Of particular interest is graphene's extraordinary carrier mobility, especially when prepared from exfoliated graphite in conjunction with nanoscale processing techniques. Mobilities as high as 2 × 10 5 cm 2 /Vs [3,4] have been reported. As phenomenal as these results are, for graphene to be utilized in modern electronics, graphene in a form that provides the uniformity and repeatability for production of high density, high number device arrays are necessary.
Graphene derived from chemical vapor deposition (CVD) is a promising source for graphene electronics due to its scalability to areas as large as common standard wafer sizes (4", 8", 12") and larger. Current CVD graphene methods also allow graphene to be transferred to any substrate [5][6][7][8][9], thus permitting non-conventional electronics applications. The scalability of CVD graphene inherently has a cost advantage compared to exfoliated graphene and the technology is mature enough so that CVD graphene wafers can now be readily purchased [10].
Early research in graphene, both exfoliated and CVD derived, was conducted using SiO 2 insulator on Si wafers as the de facto standard, due to the ubiquity and maturity of these materials. Such research has shown that SiO 2 greatly reduces graphene's carrier mobility [11], limiting to 4 × 10 4 cm 2 /Vs. The inclusion of hexagonal Boron Nitride (hBN), a lattice-compatible insulator, with graphene yields much higher mobilities [12][13][14][15]. Just as in the early research on graphene, hBN was obtained from the exfoliation of BN crystals. Methods for CVD on hBN have been developed that, like CVD graphene, are applicable to any substrate [16,17]. The technology for CVD hBN is mature enough that hBN wafers and graphene on hBN wafers can be purchased commercially [10].
This work details the fabrication, characterization, and measurement of identical Hall bar geometries in CVD graphene on both SiO 2 /Si and hBN/SiO 2 /Si substrates using the 4" wafer standard patterned with conventional photolithography. Previous research has shown the utility of large scale graphene in electro-optic devices due to its thin and nearly transparent nature [7,[18][19][20][21][22][23][24][25]. It is the intent of this effort to show that CVD graphene processed with conventional photolithography can be a cost-effective approach towards the realization of graphene electronics due to its inherent scalability and repeatability. The repeatable nature of photolithography also allows for the comparison of the electrical properties of otherwise identical graphene devices on SiO 2 and hBN. Such a comparison would be useful when making a cost to performance decision with respect to the dielectric of choice. This is demonstrated by designing mask patterns containing several devices as small as 5 µm and as large as 1 mm with rectangular and curved geometries and fabricating them on each of the dielectric materials. The wafers are inspected for pattern fidelity via optical microscopy and initial electrical viability via Raman scattering before being diced and packaged for electrical and Hall effect characterization. Electrical characterization was performed on identical 1 mm long Hall bar devices on both dielectric materials to determine if, even at these lengths, they are conductive, and if so, what is their respective carrier mobility and density.

Materials and Methods
To demonstrate the process compatibility of the CVD graphene wafers, an assortment of rectangular and semicircular geometries with sizes ranging from 5 µm × 50 µm to 100 µm × 1000 µm were designed as shown in Figure 1. Successful processing of the smallest devices would demonstrate the pattern transfer resolution from the mask to the substrate [26]. Successful processing of the largest devices would test the limits of electrical continuity at millimeter scale. Semicircular device geometries were also chosen to demonstrate patterning fidelity as curved geometries may process differently than rectangular geometries, especially during development and liftoff. Lastly, device arrays were designed to test process repeatability and device yield over a 1 cm 2 area. The most extensive testing was performed on the large 100 µm × 1000 µm devices on both SiO 2 /Si and hBN/SiO 2 /Si substrates in which electric field response and Hall effect measurements were performed. In addition, Raman scattering and visual inspection under a microscope were performed. With these measurements, the suitability of graphene for larger scale electrical devices and interfaces can be determined.

Fabrication
Device fabrication begins with the commercially obtained CVD graphene wafers in the form of 1 graphene/SiO 2 (90 nm)/Si 4" p-doped and 1 graphene/hBN/SiO 2 (285 nm)/Si 4" p-doped. Before processing, the wafers were inspected using optical microscopy for graphene coverage, irregularities, and defects. A pair of 5" masks containing the device patterns, including Hall Bars of assorted sizes and semicircular device geometries, was used for both wafers.
The first mask was used to pattern the graphene into the desired device geometries. A layer of SPR-955-0.9 photoresist was spin-coated onto each wafer followed by the preexposure bake. The respective wafers were then exposed to the mask pattern and then a post-exposure bake. The wafers were next developed in a CD-26 developer solution and then subjected to an O 2 plasma reactive ion etch (RIE) to remove the unmasked graphene.

Fabrication
Device fabrication begins with the commercially obtained CVD graphene wafers in the form of 1 graphene/SiO2 (90 nm)/Si 4" p-doped and 1 graphene/hBN/ SiO2 (285 nm)/Si 4" p-doped. Before processing, the wafers were inspected using optical microscopy for graphene coverage, irregularities, and defects. A pair of 5" masks containing the device patterns, including Hall Bars of assorted sizes and semicircular device geometries, was used for both wafers.
The first mask was used to pattern the graphene into the desired device geometries. A layer of SPR-955-0.9 photoresist was spin-coated onto each wafer followed by the preexposure bake. The respective wafers were then exposed to the mask pattern and then a post-exposure bake. The wafers were next developed in a CD-26 developer solution and then subjected to an O2 plasma reactive ion etch (RIE) to remove the unmasked graphene. After the RIE, the wafers were rinsed with acetone/isopropanol to remove the remaining photoresist, leaving just the patterned graphene layer.
The second mask was used to pattern the metallic contacts that interface with the graphene devices via liftoff technique. As in the first mask, a layer of SPR-955-0.9 was spin coated onto each wafer followed by a pre-exposure bake. The wafers were then exposed to the mask pattern followed by a post-exposure bake. The wafers were then developed in a CD-26 developer solution and placed in an Angstrom COVAP metal evaporator where a 5 nm adhesion layer of Cr followed by a 50 nm layer of Au were deposited. The wafers were then placed in an acetone bath and subjected to sonication for the liftoff process. At the conclusion of the liftoff process, the wafers were rinsed in deionized water and dried with compressed air. The wafers were then visually inspected and diced along 1 cm square grid lines. Diced areas that passed visual inspection-continuous graphene geometry, continuous metal contact-were then wire-bonded to a 28 terminal ceramic dual inline package (CDIP28). An overview of the wafer processing is shown in Figure 2. The second mask was used to pattern the metallic contacts that interface with the graphene devices via liftoff technique. As in the first mask, a layer of SPR-955-0.9 was spin coated onto each wafer followed by a pre-exposure bake. The wafers were then exposed to the mask pattern followed by a post-exposure bake. The wafers were then developed in a CD-26 developer solution and placed in an Angstrom COVAP metal evaporator where a 5 nm adhesion layer of Cr followed by a 50 nm layer of Au were deposited. The wafers were then placed in an acetone bath and subjected to sonication for the liftoff process. At the conclusion of the liftoff process, the wafers were rinsed in deionized water and dried with compressed air. The wafers were then visually inspected and diced along 1 cm square grid lines. Diced areas that passed visual inspection-continuous graphene geometry, continuous metal contact-were then wire-bonded to a 28 terminal ceramic dual inline package (CDIP28). An overview of the wafer processing is shown in Figure 2.

Raman Spectrum
Prior to patterning, Raman spectroscopy ( Figure 3) was performed in order to establish a quality baseline before and after the fabrication processes. This procedure verified the survival of the graphene to the O2 plasma and acetone cleaning as well as photoresist

Raman Spectrum
Prior to patterning, Raman spectroscopy ( Figure 3) was performed in order to establish a quality baseline before and after the fabrication processes. This procedure verified the survival of the graphene to the O 2 plasma and acetone cleaning as well as photoresist contamination. A Renishaw inVia Raman microscope with a 514 nm wavelength laser was used at 50% power. Spectrum data was acquired in 10 s sweeps for 300 accumulations. The measurements show strong presence of the identifying G and 2D peaks and minimal presence of the disorder peaks D, D', and D+G. For quality graphene, the 2D/G and D/G ratios should be greater than 2 and near zero, respectively [27]. For the processed samples, the 2D/G and D/G ratios were calculated to be 4.709 and 0.103 for graphene on SiO 2 before etching and 4.336 and 0.159 after etching. These measurements indicate that while there is a change in quality after etching, it is not significant enough to expect adverse electrical performance.

Raman Spectrum
Prior to patterning, Raman spectroscopy ( Figure 3) was performed in order to establish a quality baseline before and after the fabrication processes. This procedure verified the survival of the graphene to the O2 plasma and acetone cleaning as well as photoresist contamination. A Renishaw inVia Raman microscope with a 514 nm wavelength laser was used at 50% power. Spectrum data was acquired in 10 s sweeps for 300 accumulations. The measurements show strong presence of the identifying G and 2D peaks and minimal presence of the disorder peaks D, D', and D+G. For quality graphene, the 2D/G and D/G ratios should be greater than 2 and near zero, respectively [27]. For the processed samples, the 2D/G and D/G ratios were calculated to be 4.709 and 0.103 for graphene on SiO2 before etching and 4.336 and 0.159 after etching. These measurements indicate that while there is a change in quality after etching, it is not significant enough to expect adverse electrical performance.

Patterning Fidelity
A wide variety of geometries were patterned to determine the fidelity and robustness of the graphene patterning process at scale (Figure 4). The mask design was organized in a grid with 1 cm × 1 cm divisions allowing for redundant cells and redundant devices in the case of process defects, cleaving errors, or mishandling. The device sizes ranged from 5 µm to 100 µm in width and 50 µm to 1000 µm in length in both rectangular and semicircular geometries. Abrupt geometry changes in the form of constrictions in both rectangular and semicircular geometries were explored.
A visual inspection of the wafers indicates that the mask patterns are transferred to the graphene with high fidelity for feature sizes as small as 5 µm. This is evident as the semicircular features maintain their curvature along the inner and outer edges as well as the sharp corners present in the constricted geometries. The device patterns remain continuous for the largest features up to 1000 µm and the device arrays demonstrate the repeatability device fidelity over large areas approaching 1 cm 2 . High magnification also reveals artifacts of the CVD graphene process [8,10] such as grain boundaries shown as dark lines across the device, and bilayer formations shown as dark spots.
A wide variety of geometries were patterned to determine the fidelity and robustness of the graphene patterning process at scale (Figure 4). The mask design was organized in a grid with 1 cm × 1 cm divisions allowing for redundant cells and redundant devices in the case of process defects, cleaving errors, or mishandling. The device sizes ranged from 5 μm to 100 μm in width and 50 μm to 1000 μm in length in both rectangular and semicircular geometries. Abrupt geometry changes in the form of constrictions in both rectangular and semicircular geometries were explored. A visual inspection of the wafers indicates that the mask patterns are transferred to the graphene with high fidelity for feature sizes as small as 5 μm. This is evident as the semicircular features maintain their curvature along the inner and outer edges as well as the sharp corners present in the constricted geometries. The device patterns remain continuous for the largest features up to 1000 μm and the device arrays demonstrate the repeatability device fidelity over large areas approaching 1 cm 2 . High magnification also reveals artifacts of the CVD graphene process [8,10] such as grain boundaries shown as dark lines across the device, and bilayer formations shown as dark spots.

Results
Having demonstrated that the graphene can be patterned with conventional photolithography over a large area with features ranging from 5 μm to 1000 μm device, electrical properties were then measured. For the remainder of this report, the 100 μm × 1000 μm Hall bars on both substrates will be examined.

Electrical Resistance Measurements
Initial electrical characterization by 2-point and 4-point probe was performed on a Keysight B1500A semiconductor device analyzer at room temperature with no applied backgate voltage. Sheet resistance of the 100 μm × 1000 μm Hall Bar on both SiO2 and hBN were within (450 ± 5) Ω/sq. This is within the manufacturer's specification of 430 ± 50 Ω/sq [10]. Contact resistance for the longitudinal pair was 7.7 kΩ for graphene on SiO2

Results
Having demonstrated that the graphene can be patterned with conventional photolithography over a large area with features ranging from 5 µm to 1000 µm device, electrical properties were then measured. For the remainder of this report, the 100 µm × 1000 µm Hall bars on both substrates will be examined.

Electrical Resistance Measurements
Initial electrical characterization by 2-point and 4-point probe was performed on a Keysight B1500A semiconductor device analyzer at room temperature with no applied backgate voltage. Sheet resistance of the 100 µm × 1000 µm Hall Bar on both SiO 2 and hBN were within (450 ± 5) Ω/sq. This is within the manufacturer's specification of 430 ± 50 Ω/sq [10]. Contact resistance for the longitudinal pair was 7.7 kΩ for graphene on SiO 2 and 5.5 kΩ for graphene on hBN/SiO 2 . The resistance measurements indicate that Ohmic contact was achieved at the graphene/metal interface.
Next, the location of the charge neutrality point (CNP) [28] for each device was determined by applying a constant DC bias of 1 V along the length of the Hall Bar and applying a backgate voltage sweep from 0 V to 100 V and back. The backgate sweeps ( Figure 5) indicate that there is hysteresis [29] and the CNP location is direction dependent. For the graphene on SiO 2 device, the CNP is located at 40 V in the forward direction and 50 V is the backward direction. For the graphene on hBN/SiO 2 device the CNP is located at 55 V in the forward direction and 75 V in the backward direction.
From the backgate sweeps, the carrier density and charge density can be estimated with field effect methods [30], specifically with what is called a transfer length method (TLM). Based on this method the mobility, µ TLM can be determined with the following expression: where e is the electron charge, ρ is the device's sheet resistance, and n TLM is the carrier density based on the following expression: Electronics 2022, 11, x FOR PEER REVIEW 6 of 10 and 5.5 kΩ for graphene on hBN/SiO2. The resistance measurements indicate that Ohmic contact was achieved at the graphene/metal interface. Next, the location of the charge neutrality point (CNP) [28] for each device was determined by applying a constant DC bias of 1 V along the length of the Hall Bar and applying a backgate voltage sweep from 0 V to 100 V and back. The backgate sweeps ( Figure  5) indicate that there is hysteresis [29] and the CNP location is direction dependent. For the graphene on SiO2 device, the CNP is located at 40 V in the forward direction and 50 V is the backward direction. For the graphene on hBN/SiO2 device the CNP is located at 55 V in the forward direction and 75 V in the backward direction. From the backgate sweeps, the carrier density and charge density can be estimated with field effect methods [30], specifically with what is called a transfer length method (TLM). Based on this method the mobility, μTLM can be determined with the following expression: where e is the electron charge, ρ is the device's sheet resistance, and nTLM is the carrier density based on the following expression: This expression for carrier density is valid for the case where the gate voltage (Vg) is far away from the CNP. Lastly, the gate capacitance (Cg) is given by: where ε0 is the permittivity of free space, ε is the relative permittivity, and toxide is the thickness of the SiO2 layer. For graphene on SiO2, the transfer length method yields a carrier density nTLM of 2.79 × 10 12 cm −2 and a carrier mobility μTLM of 5.20 × 10 3 cm 2 /Vs. For graphene on hBN, transfer length method yields a carrier density nTLM of 3.84 × 10 12 cm −2 and a carrier mobility μTLM of 3.78 × 10 3 cm 2 /Vs. While the mobility and density are feasibly determined with the back gate sweep data and field effect methods, these results are more useful as upper estimates. For more accurate determination of mobility and density, Hall effect measurements are required. This expression for carrier density is valid for the case where the gate voltage (V g ) is far away from the CNP. Lastly, the gate capacitance (C g ) is given by: where ε 0 is the permittivity of free space, ε is the relative permittivity, and t oxide is the thickness of the SiO 2 layer. For graphene on SiO 2 , the transfer length method yields a carrier density n TLM of 2.79 × 10 12 cm −2 and a carrier mobility µ TLM of 5.20 × 10 3 cm 2 /Vs. For graphene on hBN, transfer length method yields a carrier density n TLM of 3.84 × 10 12 cm −2 and a carrier mobility µ TLM of 3.78 × 10 3 cm 2 /Vs. While the mobility and density are feasibly determined with the back gate sweep data and field effect methods, these results are more useful as upper estimates. For more accurate determination of mobility and density, Hall effect measurements are required.

Hall Effect Measurements
Hall effect measurements were then performed on both devices with a Leybold Hall Effect apparatus at room temperature with no backgate applied. The devices were subject to a magnetic field from 20 mT to 136 mT ( Figure 6). Measurements for the graphene on SiO 2 were performed at two currents: 0.028 A and 0.2 A. Similarly, the graphene on hBN/SiO 2 measurements were performed at 0.0285 A and 0.2 A. The Hall effect coefficients were calculated to be 1.435 × 10 −11 m 3 /C for graphene on SiO 2 and 1.365 × 10 −8 m 3 /C for graphene on hBN/SiO 2 .
Using the measured Hall coefficients, the carrier density of the devices was calculated with the relation: where R H is the Hall coefficient [31]. For graphene on SiO 2 , the carrier density is 4.35 × 10 29 m −3 (7.8 × 10 15 cm −2 ), while graphene on hBN/SiO 2 has a carrier density of 4.6 × 10 26 m −3 (8.2 × 10 12 cm −2 ). The carrier mobility can then be determined with the relation: where ρ is the resistivity. The carrier mobilities are 3.5 cm 2 /Vs and 3 × 10 3 cm 2 /Vs for graphene on SiO 2 and graphene on hBN/SiO 2 . Accounting for the minimum conductivity of graphene, a modified mobility expression [3] is as follows: where σ is the device conductivity and σ 0 is the device minimum conductivity. With the corrections, the mobilities are now 2.6 cm 2 /Vs and 2.68 × 10 3 cm 2 /Vs graphene on SiO 2 and graphene on hBN/SiO 2 , respectively. A summary of the mobility and density for both substrates and methods is provided in Table 1.

Hall Effect Measurements
Hall effect measurements were then performed on both devices with a Leybold Hall Effect apparatus at room temperature with no backgate applied. The devices were subject to a magnetic field from 20 mT to 136 mT ( Figure 6). Measurements for the graphene on SiO2 were performed at two currents: 0.028 A and 0.2 A. Similarly, the graphene on hBN/SiO2 measurements were performed at 0.0285 A and 0.2 A. The Hall effect coefficients were calculated to be 1.435 × 10 −11 m 3 /C for graphene on SiO2 and 1.365 × 10 −8 m 3 /C for graphene on hBN/SiO2. Using the measured Hall coefficients, the carrier density of the devices was calculated with the relation: where RH is the Hall coefficient [31]. For graphene on SiO2, the carrier density is 4.35 × 10 29 m −3 (7.8 × 10 15 cm −2 ), while graphene on hBN/SiO2 has a carrier density of 4.6 × 10 26 m −3 (8.2 × 10 12 cm −2 ). The carrier mobility can then be determined with the relation: where ρ is the resistivity. The carrier mobilities are 3.5 cm 2 /Vs and 3 × 10 3 cm 2 /Vs for graphene on SiO2 and graphene on hBN/SiO2. Accounting for the minimum conductivity of graphene, a modified mobility expression [3] is as follows: where σ is the device conductivity and σ0 is the device minimum conductivity. With the corrections, the mobilities are now 2.6 cm 2 /Vs and 2.68 × 10 3 cm 2 /Vs graphene on SiO2 and graphene on hBN/SiO2, respectively. A summary of the mobility and density for both substrates and methods is provided in Table 1.   In addition to mobility and carrier density, another metric for graphene devices is the minimum device conductivity (Figure 7). Having determined the charge neutrality point and the maximum device resistance, the minimum device conductivity in terms of the conductance quantum is calculated using [32]: where h is Planck's constant. Graphene on SiO 2 has a minimum conductivity of 1 2 G 0 , while graphene on hBN/SiO 2 has a minimum conductivity of 1 4 G 0 . conductance quantum is calculated using [32]: where h is Planck's constant. Graphene on SiO2 has a minimum conductivity of 1 2 0 , while graphene on hBN/SiO2 has a minimum conductivity of

Discussion
While the fabricated devices are designed to be identical, the electrical and Hall Effect characterizations indicate that the graphene is highly affected by the insulating material it resides on. Starting with the resistance and CNP sweeps, graphene on SiO2 has a very broad shape, perhaps even bimodal, while graphene on hBN is well shaped and nearly Gaussian. For both wafer types, a positive CNP gate voltage is indicative of hole-dominant transport. This is expected since the Si substrate is p-doped. The broadening of the resistance curve on SiO2 is due to the presence of p-type impurities [28], since the majority carrier is expected to switch from holes to electrons past the CNP.
While the field effect method (TLM) yielded mobilities and densities that were all within the same order of magnitude for both dielectric materials, Hall effect measurements show that graphene on hBN/SiO2 is 3 orders of magnitude more responsive to an applied magnetic field. This 3 orders of magnitude difference persists in the carrier density difference and the carrier mobility difference. Graphene on SiO2 behaves like a lightly doped semiconductor in terms of its carrier density (7.8 × 10 15 cm −2 ), but more like a metal in terms of its mobility. The low mobility of graphene on SiO2 is mostly attributed to phonon scattering [11]. The results from transfer length method were unable to capture the effects of the unintended dopants in the device which were clear in the backgate sweep and in the Hall effect measurement. This reaffirms the literature [30], where such a method is best used as an upper estimate and best applicable for intrinsic graphene.
Graphene on hBN/SiO2 agrees with other works in terms [31] of the Hall response, carrier density (8.2 × 10 12 cm −2 ), and mobility. Both TLM and Hall effect results for mobility and carrier density agree to the same order of magnitude, with TLM providing a lower carrier density and subsequently a higher mobility. At this length scale, the graphene on hBN/SiO2 mobility of 2.68 × 10 3 cm 2 /Vs is comparable to that of GaAs [33]-a common high mobility semiconducting material. Positive Hall coefficients indicate that both

Discussion
While the fabricated devices are designed to be identical, the electrical and Hall Effect characterizations indicate that the graphene is highly affected by the insulating material it resides on. Starting with the resistance and CNP sweeps, graphene on SiO 2 has a very broad shape, perhaps even bimodal, while graphene on hBN is well shaped and nearly Gaussian. For both wafer types, a positive CNP gate voltage is indicative of hole-dominant transport. This is expected since the Si substrate is p-doped. The broadening of the resistance curve on SiO 2 is due to the presence of p-type impurities [28], since the majority carrier is expected to switch from holes to electrons past the CNP.
While the field effect method (TLM) yielded mobilities and densities that were all within the same order of magnitude for both dielectric materials, Hall effect measurements show that graphene on hBN/SiO 2 is 3 orders of magnitude more responsive to an applied magnetic field. This 3 orders of magnitude difference persists in the carrier density difference and the carrier mobility difference. Graphene on SiO 2 behaves like a lightly doped semiconductor in terms of its carrier density (7.8 × 10 15 cm −2 ), but more like a metal in terms of its mobility. The low mobility of graphene on SiO 2 is mostly attributed to phonon scattering [11]. The results from transfer length method were unable to capture the effects of the unintended dopants in the device which were clear in the backgate sweep and in the Hall effect measurement. This reaffirms the literature [30], where such a method is best used as an upper estimate and best applicable for intrinsic graphene.
Graphene on hBN/SiO 2 agrees with other works in terms [31] of the Hall response, carrier density (8.2 × 10 12 cm −2 ), and mobility. Both TLM and Hall effect results for mobility and carrier density agree to the same order of magnitude, with TLM providing a lower carrier density and subsequently a higher mobility. At this length scale, the graphene on hBN/SiO 2 mobility of 2.68 × 10 3 cm 2 /Vs is comparable to that of GaAs [33]-a common high mobility semiconducting material. Positive Hall coefficients indicate that both devices are hole-dominant transport. This is expected as both graphene devices reside on p-doped Si, reaffirming the findings with the backgate sweeps.
Interestingly, graphene on SiO 2 did have a higher minimum conductance (1/2 G 0 ) than graphene on hBN/SiO 2 (1/4 G 0 ). This is due to the presence of impurities providing charge carriers despite the applied back gate depleting the device of intrinsic carriers from the graphene. In both cases the minimum conductance is a fraction of G 0 , suggesting that ballistic transport does not occur in either of these devices [11,34]. This result is also expected since the device length of 1000 µm exceeds the manufacturer's specification of 10 µm grain size. Charge carriers in these devices will inevitably encounter scattering as they traverse the grain boundaries. This work demonstrates the possibility of creating large-scale repeatable device patterns with conventional photolithography on commercially obtained CVD graphene wafers residing on either SiO 2 or hBN/SiO 2 . From optical microscopy, it was shown that the pattern fidelity is high enough for semicircular shapes to maintain their curvature and abrupt geometry changes are produced without noticeable deviation and that device elements as small as 5 µm and as large as 1 mm can be accommodated. Electrical and Hall effect tests on identical 1 mm devices on both substrates showed continuity and conductivity. Even at this length, graphene on hBN/SiO 2 had mobilities on the order of 10 3 cm 2 /Vs which is comparable to GaAs. Based on these results, CVD graphene on hBN/SiO 2 is most suitable where high carrier mobility is crucial while CVD graphene on SiO 2 is most suitable where an atomically thin electronic device is desired, but cost is also a deciding factor. The compatibility of CVD graphene with the repeatable and scalable nature of photolithography shows promise as a foundation for micron scale graphene electronic devices and a cost effective alternative to electron beam lithography.