A Wideband Reconﬁgurable CMOS VGA Based on an Asymmetric Capacitor Technique with a Low Phase Variation

: This paper presents a wideband digitally controlled variable gain ampliﬁer (VGA) with a reconﬁgurable gain tuning range and gain step in a 65 nm CMOS process. A unique asymmetric capacitor-based reconﬁgurable technique is proposed to extend the gain tuning range and realize gain step reconﬁguration. An active neutralization topology based on a stackless transistor is utilized to compensate for the additional phase shift introduced by the gain tuning. Moreover, a current-type digital-to-analog converter (DAC) is also integrated for easier precise gain control. With the asymmetric capacitor varying from 1000 fF to 200 fF with a step of 400 fF, the proposed VGA achieves a 12.2/9.2/6.1 dB gain tuning range with a 0.4/0.3/0.2 dB gain resolution, respectively. At the maximum gain tuning range mode, the measured minimum root-mean-square (RMS) phase error is 1.7 ◦ at 23.4 GHz. At the ﬁnest gain step control mode, the RMS phase error measured across 20–30 GHz is lower than 1.9 ◦ . The tested result also shows the proposed VGA achieves a peak gain of 13 dB with a 3 dB bandwidth of 21.4–29 GHz, and the output 1 dB compression point (OP 1dB ) is up to 8.6 dBm at 25 GHz.


Introduction
For the fifth-generation (5G) new radio (NR) phased array beamformers, the variable gain amplifier (VGA) is the key building block, which has attracted increasing attention from industrial and academic fields. The VGA is designed to serve both purposes. Firstly, it can effectively compensate for the different losses caused by the phase shifter during phase shifting [1,2]. Secondly, enough amplitude weighting can be provided for a phased array to achieve high sidelobe suppression [3][4][5][6][7][8][9]. For millimeter-wave (mm-wave) phase shifters (PSs), the 6 dB gain tuning range of the VGA is sufficient enough to cover the loss variation [2]. However, it is more desirable for the VGA to have a high gain resolution and low phase variation, to avoid introducing extra gain errors and degrading the phase resolution of PSs. For phased array systems, sidelobe suppression is very important, which directly determines the signal quality of the entire link. In order to achieve less than −30 dB sidelobe suppression, for a 16-element phased array, a range of gain tuning of about 12 dB is required, according to Taylor's method [10]. Based on the two applications mentioned above, a new generation VGAs should have reconfigurable characteristics of gain tuning range and gain step to simultaneously serve both purposes, which can greatly increase the flexibility of phased array systems. To the authors' best knowledge, so far, the VGA with reconfigurable gain tuning range and gain step size has not yet been reported.
Moreover, a VGA with low additional phase shift during gain tuning is also very important, which can greatly simplify the complexity of phased array calibration procedures [9]. To this end, various phase-invariant VGAs have been proposed [11][12][13][14][15], such as the study by [12], which achieves a 7.5 dB gain tuning range with <3.5 • root-mean-square (RMS) procedures [9]. To this end, various phase-invariant VGAs have been proposed [11][12][13][14][15], such as the study by [12], which achieves a 7.5 dB gain tuning range with <3.5° root-meansquare (RMS) phase error across 27-42 GHz by introducing interstage inductance. However, the designs mentioned above all adopt multiple-stack transistor structures, which suffer from more complex circuit topologies and higher supply voltage values, compared with stackless topologies under the same technology node and the normal supply voltage recommended by the vendor.
To address these issues, a new technique named as asymmetric capacitor-based reconfigurable technique is proposed to extend the gain tuning range and reconfigure the gain step. Based on a stackless transistor structure, an active neutralization technique is adopted to minimize the additional phase shift during gain tuning. Furthermore, for achieving accurate gain control to reduce gain error, the chip also integrates a high-resolution digital-to-analog converter (DAC).

Design and Analysis of VGA
Unlike the widely used current-steering ( Figure 1a) and Gilbert-cell-based ( Figure  1b) VGA structures [16][17][18][19][20][21], the proposed reconfigurable digitally controlled VGA used a stackless common source (CS) topology, as plotted in Figure 1c, which has advantages such as a simpler circuit structure and lower power supply. Figure 2a presents the full circuit schematic of the proposed reconfigurable VGA, and in both stages, a differential CS structure was used. Among them, the input stage is a variable gain stage to achieve gain tuning, and the output stage is a fixed gain stage to realize high output power. Furthermore, in order to more easily achieve accurate gain control and high robustness against the process and supply voltage and temperature variations (PVT) [16][17][18][19][20], the designed VGA used a digital control method. The control voltages Va and Vb were generated by a 7-bit current-type DAC control circuit [22]. Additionally, to achieve wideband matching and compact layout, transformer-based high-order matching networks were employed.

Asymmetric Capacitor-Based Reconfigurable Technique
The core idea behind the proposed asymmetric capacitor-based reconfigurable technique was to connect asymmetric capacitors Cx and Cy in series on the gate nodes of transistors (M1-M4), respectively, as shown in Figure 2a. It should be pointed out that since the value of Cx is different from Cy, it is called asymmetric capacitors. Adjusting the values of asymmetrical capacitors provides another dimension of gain control, and hence, reconfigurable gain tuning range and gain step can be achieved. Figure 2b depicts the structure of the applied asymmetric capacitors. To achieve three configurations, the adjustable capacitor Cx was designed to be composed of three capacitors and two switching transistors, which are controlled by the bias voltage of Ctr1 and Ctr2. In addition, to ensure the reconfigurable effect, it is necessary to ensure that the designed capacitances of the asymmetric capacitors are as close as possible to the desired theoretical value. Based on this, both of the asymmetric capacitors used in this study were metal insulator metal (MIM) topology, because of its high resistance to process deviation. Meanwhile, Cx and Cy used similar capacitor arrays.
To investigate the reconfigurable mechanism, the core of the variable gain stage is shown separately, and its simplified schematic diagram is shown in Figure 3a. For further and more intuitive theoretical analysis, the corresponding half-side small-signal equivalent circuit is also established, as shown in Figure 3b. Based on Figure 3b, the voltage gain can be calculated by where gm refers to the transconductances of transistors M1 and M4; the Cgd and Cds describe the parasitic gate-to-drain capacitor and drain-to-source capacitor, respectively; the ro represents channel output resistance; the ZL is used to characterize the load impedance. In addition, A1 and A2 are obtained by Figure 2. (a) Schematic of the proposed reconfigurable digitally controlled VGA and (b) diagram of the structure of the asymmetric capacitors C x and C y , where C x is an adjustable capacitor and C y is a fixed capacitor.

Asymmetric Capacitor-Based Reconfigurable Technique
The core idea behind the proposed asymmetric capacitor-based reconfigurable technique was to connect asymmetric capacitors C x and C y in series on the gate nodes of transistors (M 1 -M 4 ), respectively, as shown in Figure 2a. It should be pointed out that since the value of C x is different from C y , it is called asymmetric capacitors. Adjusting the values of asymmetrical capacitors provides another dimension of gain control, and hence, reconfigurable gain tuning range and gain step can be achieved. Figure 2b depicts the structure of the applied asymmetric capacitors. To achieve three configurations, the adjustable capacitor C x was designed to be composed of three capacitors and two switching transistors, which are controlled by the bias voltage of Ctr1 and Ctr2. In addition, to ensure the reconfigurable effect, it is necessary to ensure that the designed capacitances of the asymmetric capacitors are as close as possible to the desired theoretical value. Based on this, both of the asymmetric capacitors used in this study were metal insulator metal (MIM) topology, because of its high resistance to process deviation. Meanwhile, C x and C y used similar capacitor arrays.
To investigate the reconfigurable mechanism, the core of the variable gain stage is shown separately, and its simplified schematic diagram is shown in Figure 3a. For further and more intuitive theoretical analysis, the corresponding half-side small-signal equivalent circuit is also established, as shown in Figure 3b. Based on Figure 3b, the voltage gain can be calculated by where g m refers to the transconductances of transistors M 1 and M 4 ; the C gd and C ds describe the parasitic gate-to-drain capacitor and drain-to-source capacitor, respectively; the r o represents channel output resistance; the Z L is used to characterize the load impedance. In addition, A 1 and A 2 are obtained by (2) where g m1 and g m4 are biased by V a and V b , respectively, which are generated by a 7-bit DAC. According to (1), it can be observed that the voltage gain is proportional to the difference between V a and V b ; that is, the greater the difference between the two, the higher the gain. Based on this, to achieve the gain tuning of the VGA, V a should not be equal to V b . Furthermore, when setting V a less than V b , from (1), the maximum gain tuning range ∆G max can be derived as where g m,min and g m,max are the transconductances of transistors biased in minimum and maximum control voltages. It should be pointed out that since the amplifier gain is in decibels, the voltage gain should be converted into decibels, after which the logarithmic operation is performed. Based on this, the normal difference operation becomes division when placed in the logarithmic operation. Therefore, the final derivation of the gain tuning range appears as a ratio. In addition, it is worth mentioning that the C gd is not ignored but neutralized based on the proposed topology in deriving Equations (1)-(4). The detailed proofs of Equations(1)-(4) are presented in Appendix A.  Then, based on (4), the gain resolution G r of the VGA can be calculated as where n is the control bits of the DAC. According to (4) and (5), the proposed asymmetric capacitor-based reconfigurable technique provides a new method to configure ∆G max and G r by adjusting the coefficients A 1 and A 2 . Meanwhile, in order to keep the maximum gain of the VGA, it is needed to set A 2 ≈ 1. As shown in Figure 4a,b, the conventional methods are only obtained ∆G max and G r by controlling transconductance g m of the transistors, whereas the proposed technique achieves another dimension for ∆G max and G r control. When A 1 is varied from 1 to 0, ∆G max and G r will be reconfigured. When the asymmetric capacitors C x and C y are designed to be greater than 1000 fF across 20-30 GHz, it can be calculated from (2) and (3) that the values of the coefficients A 1 and A 2 are approximately equal to one. Conversely, when they are smaller than 1000 fF, the values of A 1 and A 2 will be less than one. Thus, the gain tuning range and gain step can be reconfigured, which is adjusted to capacitors C x and C y .    From what has been discussed above, the capacitance of C x was adjusted by 2-bit switched-capacitor array, which could achieve 200/600/1000-fF; the C y was designed to be a fixed value with a capacitance close to 1000 fF, so that the coefficient A 2 was approximately equal to one, as shown in Figure 3a. By configuring different C x values, the simulated small-signal gains versus frequency are plotted in Figure 4c. Among them, in order to observe the reconfigurable effect more intuitively, only the maximum and minimum gain states are shown in the results. At the minimum gain control mode, the gain of the VGA changes greatly as C x increases from 200 fF to 1000 fF, while the gain is almost the same at the maximum gain control mode. As a result, the reconfigurable gain tuning range and gain step can be realized. The simulation results shown in Figure 4c agree well with the theoretical analysis.

Phase Compensation Technique
For mm-wave VGAs, low additional phase shift during gain tuning is also a very important performance metric [9]. As mentioned before, many scholars have conducted extensive research to realize low phase variation during gain tuning. For VGAs with CS topologies, the parasitic capacitor C gd has been discussed in detail [23] as the most important factor causing the phase variation. In order to eliminate C gd , a method is widely used in amplifier design that introduces a positive feedback capacitor, which is called the capacitive cross-coupled neutralization (CCCN) technique [24]. This technique has the advantages of simple structure and obvious neutralization effect. However, its disadvantage is also obvious, that is, only good neutralization can be achieved in a narrow frequency band, as the positive feedback capacitor changes with frequency. This greatly limits the design of this technique in wideband VGA circuit design. To overcome this problem, the active neutralization technique in the previous study [23] was employed. The core idea of this technique is to replace the positive feedback capacitor in the conventional CCCN technique with an active transistor. Since the auxiliary transistors (M 3 and M 4 ) and the main transistors (M 1 and M 2 ) have the same size, the C gd of the two can be guaranteed to be the same with frequency changes, thus achieving good neutralization in the wide frequency band. Figure 5 plots the simulated maximum phase variation in the classic and proposed active neutralization-based CS VGAs across 20-30 GHz under the same gain adjustment range. Both simulations were conducted based on the same circuit configuration. Across 20-30 GHz, the maximum deviation of the phase variation in the proposed VGA with active neutralization technique was below 0.3 • during gain tuning. In contrast, the maximum phase variation results for the two classic CS VGAs were relatively large. Among them, one VGA with conventional CCCN technique exhibited the maximum phase variation of 1.6 • , while another VGA without any neutralization techniques showed 8.6 • phase variation at 30 GHz. These results fully illustrate two points: (1) the proposed VGA with active neutralization technique can effectively eliminate C gd and achieve low phase variation; (2) good phase compensation can be realized in the wide frequency band, which is very suitable for broadband VGA design.

Measurement Results
The proposed reconfigurable digitally controlled CS VGA was fabricated in a 65 nm CMOS process, and its die micrograph is presented in Figure 6. In the case of not including PAD, the core area of this chip was 0.758 mm × 0.23 mm. The two-stage VGA had a total power consumption of 98 mW with a 1 V supply, and the selection of 1 V supply voltage followed the vendor's recommendation under the corresponding process node. It is worth mentioning that, to achieve active neutralization, the auxiliary pairs in the proposed structure were on, which consumed slightly extra power to maintain the same gain. Even so, the total power consumption of the variable gain stage with the DAC was only 29 mW (including auxiliary pairs). The VGA presented in this paper consumed relatively high power consumption, which is because it achieved large output power. If a system does not need such high output power, the bias voltage of the output stage can be decreased, and the total dc power consumption of the proposed VGA would be reduced accordingly.

Measurement Results
The proposed reconfigurable digitally controlled CS VGA was fabricated in a 65 nm CMOS process, and its die micrograph is presented in Figure 6. In the case of not including PAD, the core area of this chip was 0.758 mm × 0.23 mm. The two-stage VGA had a total power consumption of 98 mW with a 1 V supply, and the selection of 1 V supply voltage followed the vendor's recommendation under the corresponding process node. It is worth mentioning that, to achieve active neutralization, the auxiliary pairs in the proposed structure were on, which consumed slightly extra power to maintain the same gain. Even so, the total power consumption of the variable gain stage with the DAC was only 29 mW (including auxiliary pairs). The VGA presented in this paper consumed relatively high power consumption, which is because it achieved large output power. If a system does not need such high output power, the bias voltage of the output stage can be decreased, and the total dc power consumption of the proposed VGA would be reduced accordingly.
mentioning that, to achieve active neutralization, the auxiliary pairs in the proposed structure were on, which consumed slightly extra power to maintain the same gain. Even so, the total power consumption of the variable gain stage with the DAC was only 29 mW (including auxiliary pairs). The VGA presented in this paper consumed relatively high power consumption, which is because it achieved large output power. If a system does not need such high output power, the bias voltage of the output stage can be decreased, and the total dc power consumption of the proposed VGA would be reduced accordingly. The VGA gain was controlled by Va and Vb, which were generated by the designed seven-bit DAC. The measured 32 states of gains under different control modes are shown in Figures 7a, 8a and 9a, respectively. It can be observed that the proposed VGA achieved a 12.2/9.2/6.1 dB gain tuning range, respectively, when the bias voltage of Ctr1 and Ctr2 were configured from 11 to 10 and then to 00 (Cx varying from 1000 to 200 fF, stepping 400 The VGA gain was controlled by V a and V b , which were generated by the designed seven-bit DAC. The measured 32 states of gains under different control modes are shown in Figures 7a, 8a and 9a, respectively. It can be observed that the proposed VGA achieved a 12.2/9.2/6.1 dB gain tuning range, respectively, when the bias voltage of Ctr1 and Ctr2 were configured from 11 to 10 and then to 00 (C x varying from 1000 to 200 fF, stepping 400 fF). Implementation of a 6.1 dB gain tuning range was aimed to insert loss compensation of PSs in phased array systems. Implementation of a 12.2 dB gain tuning range was intended for gain tuning in each element to suppress the sidelobes. As for the intermediate state, it was a compromise that was reserved according to actual design requirements. Meanwhile, the peak gain remained basically constant with the changes in C x . The measured 3 dB bandwidth was as wide as 7.6 GHz, from 21.4 to 29 GHz, with an approximately 13 dB peak gain.

DAC
Electronics 2022, 11, x FOR PEER REVIEW 8 o fF). Implementation of a 6.1 dB gain tuning range was aimed to insert loss compensat of PSs in phased array systems. Implementation of a 12.2 dB gain tuning range was tended for gain tuning in each element to suppress the sidelobes. As for the intermed state, it was a compromise that was reserved according to actual design requireme Meanwhile, the peak gain remained basically constant with the changes in Cx. The me ured 3 dB bandwidth was as wide as 7.6 GHz, from 21.4 to 29 GHz, with an approximat 13 dB peak gain.
To further achieve the ultrahigh average sidelobe suppression ratio of the beamfo ing to ensure beamforming quality and chain data rate, the VGA was suggested to achi a gain step of less than 0.5 dB [10]. As for insertion loss compensation of PSs, higher g steps were also required, to avoid introducing extra gain errors. Based on the above c siderations, the proposed VGA was designed to have a 0.4/0.3/0.2 dB gain resolution, spectively. Achieving such a high-precision gain step control, it was necessary to des a high-precision DAC. According to (5) and the measured gain tuning range, the calcu tion results of the three gain resolutions are as follows:  . Implementation of a 6.1 dB gain tuning range was aimed to insert loss compensat of PSs in phased array systems. Implementation of a 12.2 dB gain tuning range was tended for gain tuning in each element to suppress the sidelobes. As for the intermed state, it was a compromise that was reserved according to actual design requireme Meanwhile, the peak gain remained basically constant with the changes in Cx. The me ured 3 dB bandwidth was as wide as 7.6 GHz, from 21.4 to 29 GHz, with an approxima 13 dB peak gain.
To further achieve the ultrahigh average sidelobe suppression ratio of the beamfo ing to ensure beamforming quality and chain data rate, the VGA was suggested to achi a gain step of less than 0.5 dB [10]. As for insertion loss compensation of PSs, higher g steps were also required, to avoid introducing extra gain errors. Based on the above c siderations, the proposed VGA was designed to have a 0.4/0.3/0.2 dB gain resolution, spectively. Achieving such a high-precision gain step control, it was necessary to des a high-precision DAC. According to (5) and the measured gain tuning range, the calcu tion results of the three gain resolutions are as follows:  Furthermore, the three configurations for the min, mean, and max gain step ver the six-bit binary control word overall frequency band are plotted in Figures 7b, 8b a 9b, respectively. The proposed VGA basically realized three reconfigurable gain step 0.4/0.3/0.2 dB, respectively. Then, the measured input return loss (S11) and output ret loss (S22) of the VGA for the different configurations are plotted in Figures 7c, 8c and respectively. It can be seen from the results that changing the capacitance of Cx will sligh affect the offset of S11, which, due to the Cx, will slightly change the imaginary part of source impedance. Since the output stage was a fixed gain stage, S22 basically remain unchanged versus 32 control words. In addition, it is worth mentioning that, to achi wideband matching and compact layout, the transformer-based high-order matching n works were adopted. By adjusting the coupling coefficient k of the primary and second coils, the values of resonance frequency (ωL and ωH) could be adjusted, thereby realiz the adjustment of the bandwidth [25]. Figure 10 presents the measured small-signal ga versus 32 gain modes at 25.4 GHz, which verifies that the proposed VGA achieves rec figurable gain tuning range and gain resolution, in addition to realizing linear gain c trol. The RMS phase error was used to characterize the phase variation in the VGA. T specific formula for calculating RMS phase error is expressed as To further achieve the ultrahigh average sidelobe suppression ratio of the beamforming to ensure beamforming quality and chain data rate, the VGA was suggested to achieve a gain step of less than 0.5 dB [10]. As for insertion loss compensation of PSs, higher gain steps were also required, to avoid introducing extra gain errors. Based on the above considerations, the proposed VGA was designed to have a 0.4/0.3/0.2 dB gain resolution, respectively. Achieving such a high-precision gain step control, it was necessary to design a high-precision DAC. According to (5) and the measured gain tuning range, the calculation results of the three gain resolutions are as follows: Furthermore, the three configurations for the min, mean, and max gain step versus the six-bit binary control word overall frequency band are plotted in Figures 7b, 8b and 9b, respectively. The proposed VGA basically realized three reconfigurable gain steps of 0.4/0.3/0.2 dB, respectively. Then, the measured input return loss (S11) and output return loss (S22) of the VGA for the different configurations are plotted in Figures 7c, 8c and 9c, respectively. It can be seen from the results that changing the capacitance of C x will slightly affect the offset of S11, which, due to the C x , will slightly change the imaginary part of the source impedance. Since the output stage was a fixed gain stage, S22 basically remained unchanged versus 32 control words. In addition, it is worth mentioning that, to achieve wideband matching and compact layout, the transformer-based high-order matching networks were adopted. By adjusting the coupling coefficient k of the primary and secondary coils, the values of resonance frequency (ω L and ω H ) could be adjusted, thereby realizing the adjustment of the bandwidth [25]. Figure 10 presents the measured small-signal gains versus 32 gain modes at 25.4 GHz, which verifies that the proposed VGA achieves reconfigurable gain tuning range and gain resolution, in addition to realizing linear gain control.
The RMS phase error was used to characterize the phase variation in the VGA. The specific formula for calculating RMS phase error is expressed as where θ i is the phase at the i state, and θ ave is the average of the phases of all states. In this paper, the phase was extracted from the argument of S21. The RMS phase errors for all gain states were measured by taking the maximum gain state as a reference, and they are shown in Figure 11a. At the maximum gain tuning range mode, the measured RMS  Figure 11b.
the six-bit binary control word overall frequency band are plotted in Figures 7b, 8b and 9b, respectively. The proposed VGA basically realized three reconfigurable gain steps of 0.4/0.3/0.2 dB, respectively. Then, the measured input return loss (S11) and output return loss (S22) of the VGA for the different configurations are plotted in Figures 7c, 8c and 9c, respectively. It can be seen from the results that changing the capacitance of Cx will slightly affect the offset of S11, which, due to the Cx, will slightly change the imaginary part of the source impedance. Since the output stage was a fixed gain stage, S22 basically remained unchanged versus 32 control words. In addition, it is worth mentioning that, to achieve wideband matching and compact layout, the transformer-based high-order matching networks were adopted. By adjusting the coupling coefficient k of the primary and secondary coils, the values of resonance frequency (ωL and ωH) could be adjusted, thereby realizing the adjustment of the bandwidth [25]. Figure 10 presents the measured small-signal gains versus 32 gain modes at 25.4 GHz, which verifies that the proposed VGA achieves reconfigurable gain tuning range and gain resolution, in addition to realizing linear gain control. The RMS phase error was used to characterize the phase variation in the VGA. The specific formula for calculating RMS phase error is expressed as where ϴi is the phase at the i state, and ϴave is the average of the phases of all states. In this paper, the phase was extracted from the argument of S21. The RMS phase errors for all gain states were measured by taking the maximum gain state as a reference, and they are shown in Figure 11a. At the maximum gain tuning range mode, the measured RMS phase error was 1.7° at 23.4 GHz. Across 20-30 GHz, the measured RMS phase error was less than 5.5°. At the medium gain tuning range mode (0.3 dB gain step), the measured minimum RMS phase error was 0.5° at 25.2 GHz. Across 20-30 GHz, the measured RMS phase error was less than 2.4°. At the finest gain step control condition, the RMS phase error measured across 20-30 GHz was lower than 1.9°. At 30 GHz, a minimum phase error of 0.22° was achieved. Meanwhile, under the maximum gain state, the OP1dB was up to 8.6 dBm at 25 GHz, as plotted in Figure 11b.  Table 1 summarizes the performance of this research and compares it to prior studies. The proposed VGA is the only one that can reconstruct gain tuning range and gain resolution, which will greatly increase the flexibility of phased array systems. Additionally, it is the only one that adopts stackless transistor topology, thus achieving the lowest supply voltage, compared with other state-of-the-art multiple-stack transistor structures.   Table 1 summarizes the performance of this research and compares it to prior studies. The proposed VGA is the only one that can reconstruct gain tuning range and gain resolution, which will greatly increase the flexibility of phased array systems. Additionally, it is the only one that adopts stackless transistor topology, thus achieving the lowest supply voltage, compared with other state-of-the-art multiple-stack transistor structures.

Conclusions
A 21.4-29 GHz reconfigurable digitally controlled VGA based on stackless CS structure with novel asymmetric capacitor-based reconfigurable and active neutralization phase compensation techniques was introduced. The proposed VGA achieved a 12.2/9.2/6.1 dB gain tuning range with a 0.4/0.3/0.2 dB gain step while maintaining the peak gain constant. At the finest gain step mode, the measured RMS phase error was <1.9 • across 20-30 GHz. At 30 GHz, a minimum phase error of 0.22 • was achieved. At the maximum gain state, it achieved a measured 13 dB peak gain and 8.6 dBm OP 1dB . The measurement characteristics demonstrate the proposed VGA is suitable for 5G mm-wave NR phased array beamformers that require reconfigurable gain tuning range and gain step with low phase variation.

Data Availability Statement:
The study did not report any data.

Conflicts of Interest:
The authors declare no conflict of interest.

Appendix A
Derivations of Equations (1)-(4) Figure A1 shows a small-signal equivalent circuit of a common source (CS) amplifier with parasitic elements when the effect of asymmetric capacitors is considered.
According to Kirchhoff's current law (KCL) and Kirchhoff's voltage law (KVL), the following equations can be obtained: across 20-30 GHz. At 30 GHz, a minimum phase error of 0.22° was achieved. At the maximum gain state, it achieved a measured 13 dB peak gain and 8.6 dBm OP1dB. The measurement characteristics demonstrate the proposed VGA is suitable for 5G mm-wave NR phased array beamformers that require reconfigurable gain tuning range and gain step with low phase variation. The study did not report any data.

Conflicts of Interest:
The authors declare no conflict of interest.

Appendix A
Derivations of Equations (1)-(4) Figure A1 shows a small-signal equivalent circuit of a common source (CS) amplifier with parasitic elements when the effect of asymmetric capacitors is considered.
According to Kirchhoff's current law (KCL) and Kirchhoff's voltage law (KVL), the following equations can be obtained: Figure A1. Small-signal equivalent circuit with asymmetric capacitor C x . Figure A2 shows the small-signal equivalent circuit of a CS amplifier with parasitic elements when the effect of asymmetric capacitors is not considered.
Electronics 2022, 11, x FOR PEER REVIEW 12 of 17   Figure A2 shows the small-signal equivalent circuit of a CS amplifier with parasitic elements when the effect of asymmetric capacitors is not considered.
According to Kirchhoff's current law (KCL) and Kirchhoff's voltage law (KVL), it can be derived that According to Kirchhoff's current law (KCL) and Kirchhoff's voltage law (KVL), it can be derived that In order to facilitate the operation, let Av = V out /V in . Then, Equation (A6) can be simplified to In order to facilitate the operation, let: Then, Equation (A5) can be simplified to Equation (A11) can be simplified to: Based on Equations (A12) and (A13), A 1 is given by Similarly, A 2 is given by According to Equations (A14) and (A15), Equation (A5) can be written as Qualitatively analyzing Equation (A16), compared with the conventional symmetrical capacitor structure, the A 1 coefficient is generated by the voltage divider of the asymmetrical capacitor C x . Therefore, if the capacitance of C x is large (equivalent to short-circuit without voltage divider), A 1 is approximately equal to 1; on the contrary, if the capacitance of C x is small, and there is a certain voltage divider, A 1 will be less than 1. Figure A3a shows the half-side small-signal equivalent circuit of the proposed variable gain stage with asymmetric capacitors. Since it is a half-side circuit, V in becomes onehalf. According to the above derivation, coefficients A 1 and A 2 are introduced due to the influence of the asymmetric capacitor. Therefore, in order to express the derivation of Equation (1) more clearly and concisely, we first use the symmetrical capacitor structure to derive Equation (1). Based on Equation (A16), for the asymmetric capacitor structure, coefficients A 1 and A 2 should simply be added later to the numerator. Figure A3b presents the half-side small-signal equivalent circuit of the variable gain stage without asymmetric capacitors. According to Kirchhoff's current law (KCL) and Kirchhoff's voltage law (KVL), it can be derived that Since 1 2 V in + = − 1 2 V in −, the left side of Equation (A18) can be simplified to Equations (A19) and (A20), respectively.