Broadband Class-J GaN Doherty Power Ampliﬁer

: This paper presents a broadband 3–3.7GHz class-J Doherty power ampliﬁer exploiting second harmonic tuning in the output network. Furthermore, the output impedance inverter is eliminated and its effect is embedded in the main device’s output matching network, thus trading off among bandwidth, efﬁciency, and gain. The proposed ampliﬁer adopts two 10W packaged GaN transistors, and it achieves in measurement 60–74%, and 46–50% drain efﬁciency at saturation and 6dB output back-off, respectively, with a saturated output power of 43–44.2dBm and a small-signal gain of 10–13dB. The proposed DPA exhibits a simulated adjacent channel power ratio less than − 30dBc at 36dBm average output power, when a 16-QAM modulation with 5 MHz bandwidth is applied to the 3.5GHz carrier.


Introduction
Due to the increasingly growing demand for wireless communication systems with high quality and high data rates, the radio frequency (RF) transceiver is being pushed to operate at higher frequencies and wider bandwidths, and with modulation schemes characterized by high Peak-to-Average Power Ratios (PAPRs). The power amplifier (PA) strongly affects the performance of the transmitter [1][2][3], and thus it should operate as efficiently as possible over wide bandwidths, maintaining a sufficient level of linearity, which is especially challenging for 5G systems, based on Orthogonal Frequency Division Modulation (OFDM). OFDM signals have a varying envelope and high PAPR of the order of 10 dB to 12 dB for aggregated multicarrier signals [4], thus making the design of a PA that operates efficiently over wide dynamic and frequency ranges a critical challenge [5][6][7][8][9]. Crest Factor Reduction or Selected Mapping techniques [10,11] are normally adopted to reduce the PAPR of these signals to the 6 dB to 8 dB range, hence mitigating the negative effects of very high PAPR on the PA efficiency.
Nonetheless, in conventional PA architectures, the efficiency drops significantly when output power decreases with respect to its maximum value, where the efficiency is also maximum. This being a major drawback for non-constant envelope modulations, the efficiency enhancement in back-off has been addressed resorting to various techniques. These belong to two main categories, namely those based on supply modulation, such as envelope elimination restoration [12,13] and envelope tracking [14][15][16], and those exploiting load modulation [17]. The Doherty architecture [18][19][20], the Chireix outphasing [21][22][23], and the Load Modulated Power Amplifier (LMBA) [24,25] belong to the latter category. Among these PA architectures, the Doherty PA (DPA) has had a significant success thanks to its simplicity and ease of implementation in single-RF-input form, with a comparatively good intrinsic linearity [26]. Dual input DPAs have indeed also been explored [27][28][29], demonstrating superior performance compared to their single-input counterparts, but their appeal for real-field applications remains questionable due to the higher system complexity and cost.
One of the main challenges in the design of DPAs is achieving very wide bandwidths, which is hindered by several factors [30,31], among which it is worth mentioning the quarter wavelength transmission line that is used as an impedance inverting network (IIN) between the main device and the common node, the reactive parasitic effects of the active devices, and the possible presence of offset lines or narrowband post-matching networks.
Moreover, in order to enhance PA performance, harmonic tuning techniques have been considered so far [32][33][34], but most of them suffer from bandwidth limitations. The class-J PA shows wide bandwidth compared to other harmonic-tuned PAs [35][36][37], while its sensitivity to harmonics of the matching network is lower than class F [38,39].
In this paper, a wideband class-J DPA with high efficiency and linearity is designed using the CGH40010F GaN HEMT from Wolfspeed, targeting operation around 3.5 GHz, which is of interest for sub-6 GHz 5G applications.
The novelty of the proposed DPA is twofold: on one hand, the removal of the IIN on the main path and the embedding of the impedance inversion in the output matching network (OMN) improves the bandwidth, and on the other hand, the exploitation of the effect of the second harmonic allows us to keep gain and efficiency high over a 700 MHz bandwidth. The implemented class-J DPA achieves, in continuous wave (CW) measurement conditions, saturated and 6 dB output power back-off (OBO) efficiency of 60-74% and 46-50%, respectively, with an associated saturated output power of 43-44.2 dBm over the 3-3.7 GHz frequency range.
The structure of the paper is the following. In Section 2, the theory underlying the Doherty and class-J operation is discussed, and it is then applied to the proposed PA design in Section 3. Section 4 reports the simulation results, including linearity assessment. The measurement results are shown in Section 5, and finally, conclusions are drawn in Section 6.

Theoretical Analysis
This section reviews the theoretical foundations of the Doherty and class-J amplifiers, explaining how these concepts are exploited for the design of the proposed class-J DPA.

Doherty PA
The block diagram of a conventional class AB-C DPA is shown in Figure 1a, where the transistors are replaced by a simplified model composed of an ideal current generator and an output LC network, representing the reactive parasitic effects in the band of interest. In this work, two CGH40010F packages GaN HEMTs are adopted, whose parasitic elements are considered to be C P = 1.27 pF and L P = 0.73 nH [40]. The ideal scattering parameters of the cascade of the output parasitics of the device and its output matching network (OMN) are expressed as follows [41]: where φ is the phase of S 21 , and the network is assumed lossless. Therefore, the load reflection coefficients at the intrinsic drain terminal of the main device can be expressed as [41]: where Γ M1 is the reflection coefficient before the IIN (a quarter wavelength line with characteristic impedance equal to R opt ) and it is expressed as: where R opt represents the intrinsic optimum load of the class-AB main device, and Z M1 is derived as follows: The parameter x is the ratio between auxiliary and main current (x = I A /I M ), and the common node impedance is assumed to be equal to R opt /2. Substituting (3) and (4) into (2) leads to As shown in (5), Γ M AB is a function of x and θ. The presence of the IIN and the fact that the impedance at the common node of the Doherty combiner changes with frequency, limit the bandwidth of the DPA [42]. A possible solution to mitigate this issue is to remove the λ/4 line acting as IIN and designing the OMN of the main device so as to perform the impedance inversion required by the Doherty load modulation [32].
Furthermore, a conventional class AB-C DPA only considers the load at the fundamental frequency f 0 , and assumes a short-circuit termination at all higher harmonics. Since properly terminating the higher harmonics can significantly improve performance, in this design the OMNs have been designed to operate the devices in class J.

Class-J PA
The waveforms of the intrinsic drain current (i D ) and drain-source voltage (v DS ) of a class-J amplifier are described by the following equations [38]: where I max is the maximum current of the transistor, V K is its knee voltage, V DD is its supply voltage, and α is the empirical coefficient representing the reactive component of a class-J load, and it assumes values between −1 and +1.
By using Equations (6) and (7), the intrinsic impedance of the main device at saturation, at fundamental and second harmonic, can be derived as: In back-off, the drain current is expressed as follows [43]: where γ is the ratio between output power at saturation and at the selected OBO point (γ=P out,sat /P out,OBO ). Therefore, adopting (7) and (10), the main OBO impedance at the fundamental frequency can be calculated as: The matching network design considering a variable load at both fundamental and second harmonic would be extremely difficult. Besides, in this case, the second harmonic impedance has a limited variation with power and is therefore assumed to be constant. The constant second harmonic impedance is expressed as follows: As shown in Equations (8), (9), (11) and (12), the fundamental impedance should have a resistive and a reactive component, the second harmonic impedance should be purely reactive, and the higher harmonics are assumed to be shorted at the transistor intrinsic drain plane.

Class-J DPA Design Strategy
In order to achieve class-J operation for the main and auxiliary devices, their OMNs, which share the same structure, are designed in a modular way: in particular, each OMN is composed of three parts, as shown in Figure 1b. A second harmonic matching network (OMN 2nd), terminated by a second harmonic short (SC 2nd), synthesizes the proper impedance at the second harmonic, then the matching network OMN 1st sets the proper load at the fundamental frequency without affecting the second harmonic. Based on Equations (3) and (8), the intrinsic main reflection coefficient at fundamental for the class-J DPA can be written as: Based on Equation (13), the obtained class-J reflection coefficient is as a function of x, α, and φ, thus gives more degrees of freedom to design the output matching network with respect to the classical class-AB case. Figure 2 shows the impedance of class-J at the fundamental and second harmonics for R opt = 50 Ω. The real part of the fundamental impedance at OBO and saturation is constant, whereas the imaginary part changes from −kR opt to +kR opt , where k equals 1 and 2 at saturation and at OBO, respectively. According to Equations (6) and (7), the output power at fundamental frequency and the drain efficiency of our class-J PA are: Thus, P out J and DE J are independent of α. The dependency of the reflection coefficient Γ M J on α hence provides a degree of freedom to design the OMN, without compromising power and efficiency. In particular, in this work the value α = 0.5, yielding to an optimum load for class-J operation R opt,J = 1.25R opt , larger than the load resistance 2R L .
Differently from a conventional DPA, which adopts a quarter-wavelength transmission line as IIN, the OMN of the proposed DPA embeds the impedance inversion too, which widens the bandwidth. In this work, a low pass matching network is used, shown in Figure 3. The capacitor C 1 is representative of the parasitic drain capacitance, and the inductance L 4 is exploited as drain bias feed. The Chebyshev theory [44] is used to calculate all elements of the OMN. The optimum bandwidth is achieved when the impedance ratios are: where R 1 and R 2 are calculated as: According to (16), the values of L and C of each of the three ladder networks, are given by: where Q 1 , Q 2 , and Q 3 are defined as: Since C 1 is related to the parasitic of the transistor and has a constant value, Q 1 and R opt must be selected accordingly. The values of the OMN's elements obtained from Equations (16)- (19) are illustrated in Table 1 for R L = 25 Ω and R opt,J = 62.5 Ω. Since the implementation of the OMN with lumped capacitors and inductors is not applicable at the frequencies of interest, due to the low-quality factor of the Surface Mount Device (SMD) inductors, the equivalent distributed form, using microstrip lines is extracted. The capacitors are replaced by open-circuited stubs, while inductors are replaced by transmission lines. In this work, a Rogers RO4350B substrate ( r = 3.66, substrate height and metal thickness of 0.8 mm and 35 µm, respectively) is used. The length of the transmission lines and stubs is calculated as [44]: where Z l and Z c are the characteristic impedance of the line for the inductor and capacitor and β is the propagation constant. The final output matching networks for the main and the auxiliary devices are shown in Figure 4a. Figure 4b shows the simulated internal output impedance of the main and auxiliary transistor, for the fundamental and second harmonic at saturation and at 6 dB OBO. As can be noted, the second harmonic impedance is constant in both cases, while the fundamental impedance is properly modulated by the power level. The simulated drain current and drain-source voltage waveforms at saturation are demonstrated in Figure 5 at 3.5 GHz, confirming that the designed DPA generates the expected class-J-mode waveforms with quasi-half-sinusoidal current and voltage.
At the input, a parallel resistor-capacitor network (R = 60 Ω, C = 3.3 pF) is inserted in series to the gate of each transistor for in-and out-of-band stabilization. The wideband input matching network (IMN) minimizes the input mismatch. Finally, an uneven 90 • hybrid splitter feeds the input power to the main and auxiliary PAs with splitting ratio of P Aux /P Main = 1.5.

Simulation Results
The DPA performance is evaluated in simulation in the frequency range 3-3.7 GHz, under the following operating conditions: V GM = −2.95 V, V GA = −6 V, V DD = 28 V, with a quiescent drain current of 112 mA. Figure 6 shows the CW simulation results of the drain efficiency and gain over the operating bandwidth. A two-tone analysis is also performed at 3.5 GHz to evaluate the linearity of the DPA. The third and fifth order intermodulation distortion (IMD3 and IMD5), shown in Figure 7a versus output power, remain better than −20 dBc and −31 dBc, respectively, for P out < 43 dBm. In order to assess the system-level behavior, the DPA is simulated using a 16-QAM modulated signal and 6 dB PAPR. The input and output power spectrum at the center frequency of 3.5 GHz and with 5 MHz bandwidth are shown in Figure 7b. At an average output power of 36 dBm, the simulated ACPR is −30 dBc, and which is comparable to the results shown in [8,45].  Figure 8 shows the photograph of the proposed class-J Doherty PA. The amplifier has been characterized from 3 GHz to 3.7 GHz, in the following operating condition:

Measurement Results
The scattering parameters of the DPA are illustrated in Figure 9, showing a flat gain of around 12 dB over the target 700 MHz bandwidth, with S 11 and S 22 better than −10 dB, confirming also a good agreement between simulation and measurement.  The large-signal CW measurement results versus output power are shown in Figure 10. Power gain, drain efficiency, and output power versus frequency at saturation and at 6 dB OBO are illustrated in Figure 11. The drain efficiency is in the 60-74% range at saturation, while at 6 dB OBO, it is between 46% and 50%. The saturated output power is in the 43-44.2 dBm range.  The proposed class-J DPA is compared with other works in Table 2. The performance obtained is well in line with the state of the art in the target frequency range, thus demonstrating that the developed amplifier is suitable for 5G applications in the S-band.

Conclusions
In this paper, a wideband 20 W class-J Doherty PA with high efficiency and linearity is proposed for 5G applications, operating in the 3-3.7 GHz frequency range. Unlike conventional DPAs, the quarter-wavelength transmission line has been eliminated, embedding the impedance inversion in the output matching network, which also includes harmonic tuning to enable class-J operation. The saturated output power achieved in measurement is from 43 dBm to 44.2 dBm, while the drain efficiency at saturation and at 6 dB OBO are 46-50% and 60-74%, respectively. Author Contributions: Formal analysis, A.N. and M.E.; methodology, A.N., M.E. and S.T.; resources, A.N., M.E., S.T. and A.P.; supervision, S.T., M.P., V.C. and C.R.; validation, S.T. and A.P.; writing-original draft, A.N. and M.E.; writing-review and editing, S.T., A.P., M.P., V.C. and C.R. All authors have read and agreed to the published version of the manuscript.