From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits

In this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are designed using either 32 nm or Tunnel-FET (TFET) technology. Commercial PDK has been used for the 32 nm technology, while lookup tables (LUT) resulting from a physics model have been applied for the TFET. To consider the parasitic effects for the circuit performances, the 32 nm-based circuits have been laid out, while a parasitic model has been included in the TFET LUT for circuit implementation. In this work, the post-layout simulations, including parasitic, demonstrate for conventional CCDD circuits that TFET technology has a larger dynamic range (DR) (>60%) and better 1 V-sensitivity than the 32 nm planar technology has. Note that, in this case, the figure of merit defined by the Voltage Conversion Efficiency (VCE) and Power Conversion Efficiency (PCE) remains somewhat similar. On the other hand, topology proposing better VCE at the cost of low PCE shows lower performance than expected in 32 nm than in reported data for larger technology nodes (e.g., 180 nm). The TFET-based circuit shows a PCE of 70%, VCE of 82% with an 8 dB DR (>60%), and the best 1 V-sensitivity in this work. Because of the low-bias condition and the good reverse current blocking (unidirectional channel), the TFET offers new perspectives for RF-DC rectifier/multiplier topology, which are usually limited with planar technology.


Introduction
CMOS rectifier circuits are gaining interest for many system implementations. Indeed, the Internet of Things (IoT) requires more and more compact systems, resulting in the integration of the same monolithic chip (generally) sensors, memory, microprocessor, BT port, and power supply blocks. Such system integration is made possible by applying the System-on-Chip (SoC) strategy which is essentially employed for smart object conception. Today, IoTs or smart objects are now part of an important electronic market motivated by the relatively new Moore than More (MtM) paradigm [1].
Many applications, such as RFID wireless sensors for biomedical devices have allowed extensive research on a specific rectifier: the RF-DC power converter. Lately, engineers have concentrated their efforts on the possibility of wireless IoT implementation, namely independent of a centralized power source. To reach this goal, the concept of harvesting energy has been recently introduced to empower the electronic system [2]. Additionally, Radio Frequency Energy Harvesting (RFEH) [3][4][5] devices enable the powering of a chip with RF waves from the environment of the system. Indeed, a 50 Ω-antenna harvests an RF signal and transmits it to a rectifier by means of a matching impedance network [3,4]. Then, the rectifier or RF-DC converter provides a micropower DC signal to a Power Management Unit (PMU) to supply the chip ( Figure 1) [5,6]. The most challenging step remains the rectifying stage that must produce DC with a low power supply. Many different circuit Many different circuit topologies and technologies should be explored to propose solutions for the future needs of RFEH systems. As IoTs are mostly supply-voltage-based systems, we are focusing on multiplier rectifier circuits. Full-Wave Rectifier Multipliers (FWRM) can be integrated with the VLSI process using CMOS technology [5,7,8]. FWRM implementation can be done using many topologies [9,10]. Most of them are commonly based on the Cross-Coupled Drive Differential (CCDD) bridge structure [7,8,10]. To obtain the best circuit performance for a given frequency and amplitude signal, it is important to correctly size the circuit devices, namely the MOSFET gate dimensions, capacitances, and loads. In our previous studies, we developed a method to size the circuit for a given load and given frequency signal. We applied this method to different technologies such as planar 90 nm and 32 nm and no-planar technologies: FinFET and TFET [11]. Additionally, we also found out that the choice of a well-optimized topology could significantly influence the metric performance [12,13]. However, all these studies never went through post-layout simulations or considered parasitic components for a realistic assessment of the performance.
In the present work, we aim to establish the best topology and technology for RFEH applications. To reach this objective, we based our study on results obtained in our previous works. We also use mainly two specific figures of merit (FOM), which are defined as Power Conversion Efficiency (PCE) and Voltage Conversion Efficiency (VCE). Therefore, we have selected from our previous studies the two most interesting technologies: 32 nm planar and TFET [12,13]. The first one is an advanced node for conventional planar technology, while the second is an emergent technology providing an exceptional swing (<<60 mV/dec) and is supposedly ideal for low power applications [14][15][16][17]. For this study, we also decided to focus on two topology arrangements [10]: the VTH-compensated cascaded CCDD bridge rectifier [18] and multiplier CCDD [19]. For these specific technological solutions, we have implemented the layout (32 nm) or applied parasitic component model (TFET) and compared these circuits to assess a realistic performance and FOM of such FWRM circuits. This study is divided as follows. First, we describe the different topologies, the 32 nm iPDK, and, above all, the TFET physics-based models for circuit simulations [20,21]. For the latter, we have included a physics approach that considers the parasitic components [22] for a fair comparison for the post-layout simulation results. Then, the topologies are optimized using the same method from our previous work [13], and the simulations are carried out using the circuit TCAD simulator Synopsys. Finally, the results are compared, and FOM have been applied to assess the circuit and obtain a metric of performance in each case. We conclude on the effect of the 32 nm and TFET technologies on the different studied topologies. To obtain the best circuit performance for a given frequency and amplitude signal, it is important to correctly size the circuit devices, namely the MOSFET gate dimensions, capacitances, and loads. In our previous studies, we developed a method to size the circuit for a given load and given frequency signal. We applied this method to different technologies such as planar 90 nm and 32 nm and no-planar technologies: FinFET and TFET [11]. Additionally, we also found out that the choice of a well-optimized topology could significantly influence the metric performance [12,13]. However, all these studies never went through post-layout simulations or considered parasitic components for a realistic assessment of the performance.
In the present work, we aim to establish the best topology and technology for RFEH applications. To reach this objective, we based our study on results obtained in our previous works. We also use mainly two specific figures of merit (FOM), which are defined as Power Conversion Efficiency (PCE) and Voltage Conversion Efficiency (VCE). Therefore, we have selected from our previous studies the two most interesting technologies: 32 nm planar and TFET [12,13]. The first one is an advanced node for conventional planar technology, while the second is an emergent technology providing an exceptional swing (<<60 mV/dec) and is supposedly ideal for low power applications [14][15][16][17]. For this study, we also decided to focus on two topology arrangements [10]: the V TH -compensated cascaded CCDD bridge rectifier [18] and multiplier CCDD [19]. For these specific technological solutions, we have implemented the layout (32 nm) or applied parasitic component model (TFET) and compared these circuits to assess a realistic performance and FOM of such FWRM circuits. This study is divided as follows. First, we describe the different topologies, the 32 nm iPDK, and, above all, the TFET physics-based models for circuit simulations [20,21]. For the latter, we have included a physics approach that considers the parasitic components [22] for a fair comparison for the post-layout simulation results. Then, the topologies are optimized using the same method from our previous work [13], and the simulations are carried out using the circuit TCAD simulator Synopsys. Finally, the results are compared, and FOM have been applied to assess the circuit and obtain a metric of performance in each case. We conclude on the effect of the 32 nm and TFET technologies on the different studied topologies.

Technology
The planar technology is well known and would benefit a reliable and affordable technology library. Furthermore, for the 32-nm MOSFET, we are using the 28/32 nm iPDK developed by TSMC. In addition to electrical HSPICE-based simulation, we had the possibility of drawing the layout of our circuit. The latter gives a realistic behavior of the circuit thanks to post-layout simulations. We also considered non-planar TFET technologies for more advanced nodes. However, TFET is not a commercial technology, as the 32 nm is. Therefore, there is no PDK, and we cannot propose a layout. However, it is a proposed physics model for the TFET that enables the simulation of the circuit with parasitic components similar to a real layout. in this way, we emulated a TFET "virtual layout" to make a fair comparison with the post-layout simulation of the 32 nm. As a result, the electrical behavior of the TFET was provided by the lookup tables (LUT). Then, these LUTs were imported into the Cdesigner environment of Synopsys by means of Verilog-A description languages-enabling circuit simulations.
These LUTs were built based on I-V and C-V characteristics obtained from a physicsbased model applied to the TCAD-Sentaurus simulator. The considered TFETs were Nanowire (NW) structures made of III-V materials [20,21] and described in Figure 2a. For this kind of TFET, the use of III-V materials has many advantages for the ON state current. Indeed, the heterojunction increases the tunnel effect (energy bands distortion) to maximize the charge carrier injection density. Then, the charge carrier benefits further from a relatively high mobility by means of the effective mass of the AlGaSb (p-type) and InAs (n-type) in the channel conduction.

Technology
The planar technology is well known and would benefit a reliable and affordable technology library. Furthermore, for the 32-nm MOSFET, we are using the 28/32 nm iPDK developed by TSMC. In addition to electrical HSPICE-based simulation, we had the possibility of drawing the layout of our circuit. The latter gives a realistic behavior of the circuit thanks to post-layout simulations. We also considered non-planar TFET technologies for more advanced nodes. However, TFET is not a commercial technology, as the 32 nm is. Therefore, there is no PDK, and we cannot propose a layout. However, it is a proposed physics model for the TFET that enables the simulation of the circuit with parasitic components similar to a real layout. in this way, we emulated a TFET "virtual layout" to make a fair comparison with the post-layout simulation of the 32 nm. As a result, the electrical behavior of the TFET was provided by the lookup tables (LUT). Then, these LUTs were imported into the Cdesigner environment of Synopsys by means of Verilog-A description languages-enabling circuit simulations.
These LUTs were built based on I-V and C-V characteristics obtained from a physicsbased model applied to the TCAD-Sentaurus simulator. The considered TFETs were Nanowire (NW) structures made of III-V materials [20,21] and described in Figure 2a. For this kind of TFET, the use of III-V materials has many advantages for the ON state current. Indeed, the heterojunction increases the tunnel effect (energy bands distortion) to maximize the charge carrier injection density. Then, the charge carrier benefits further from a relatively high mobility by means of the effective mass of the AlGaSb (p-type) and InAs (n-type) in the channel conduction. However, and as for 32 nm planar technologies, lower ION was observed for the ptype transistor, Figure 2b. This is explained by a lower doping of the p-TFET source (5× lower) to avoid degeneracy and keep a steep enough subthreshold slope (Sub-S); InAs counts with about 10× lower DOS in the conduction band. Finally, the n-TFET has a lower Sub-S than p-TFET for VGS < 0.1 V, as in Figure 2b, explained by Band-to-Band-Tunneling phenomena (direct gap of InAs) producing stronger ambipolarity [23]. Note that gradual doping at the drain was considered to reduce this effect and to produce a good enough However, and as for 32 nm planar technologies, lower I ON was observed for the p-type transistor, Figure 2b. This is explained by a lower doping of the p-TFET source (5× lower) to avoid degeneracy and keep a steep enough subthreshold slope (Sub-S); InAs counts with about 10× lower DOS in the conduction band. Finally, the n-TFET has a lower Sub-S than p-TFET for V GS < 0.1 V, as in Figure 2b, explained by Band-to-Band-Tunneling phenomena (direct gap of InAs) producing stronger ambipolarity [23]. Note that gradual doping at the drain was considered to reduce this effect and to produce a good enough I ON /I OFF ratio. Regarding the 32 nm technology, the main difference between the p-and n-type is mainly explained by a lower hole mobility (2-3× lower). As a result, the TFET produces a much larger current than the 32 nm MOSFET in the subthreshold regime, namely in the range of V GS = 0.1-04 V [24], while this one in the inversion regime or above the threshold voltage (V TH ) produces a larger current. Regarding the parasitic components, the 32 nm iPDK includes these when the circuit is laid out, so for more realistic results, we carried out post-layout simulations. In the case of the TFET, the leakage current (I OFF ) and extrinsic parasitic capacitive components were calibrated and included in the simulation by means of the extrinsic model for the TFET developed in [22].

Topology
It is obvious but essential to highlight the fact that the rectifier circuit must consume the lowest energy and display the highest power efficiency during the working cycle and the OFF/ON(ON/OFF) state transitions [18]. As for the RF-DC power converter, the signal level can be very low (hundredth of mV). The range of the wireless powering system is mainly determined by the rectifier sensitivity. This one is defined as the minimum input RF power to obtain enough output DC voltage to supply the chip or circuit [10]. This sensitivity must be achieved at the highest PCE possible.
In addition, for the CMOS rectifier, the limiting parameter is the control of the V TH . As a matter of fact, if this one is too high, a large part of the signal is consumed by the transistor, while if it is too low, the reverse current (OFF state) overwhelms the charging process, which results in PCE being lower than expected. Among the different existing topologies [18,19,25], the Cross-Coupled Differential Drive (CCDD) [8,11] might be the best strategy for RF signal rectification. In the CCDD, the peak-to-peak RF signal is applied as a differential input at the gate/source transistor, providing a DC common mode as static bias to overcome the V TH and a differential mode for an active control of the rectification. Therefore, this topology provides a low sensitivity by a dynamic gate bias control [26].
We also expected good PCE because during the charging time, the transistor works in the triode regime with low overdrive. However, this last effect is mitigated by a reverse current of the p-type transistors connected at the load once the output voltage is larger than the RF input. A way to reduce this reverse current is, for instance, to make use of the body-biased technique. In this case, the n-/p-type body bias enables, in addition, a dynamic control of the V TH [13,19,27] so that both the large charging current and the small reverse current are obtained without any depression on the load charging current. Note that this technique is worthwhile for low input power since it limits the dynamic range, hence this technique involving a subthreshold regime operation of the transistor [10].
Furthermore, to gain a larger DC rectified voltage, a Voltage Multiplier (VM) should be considered. In this type of circuit, the part of the energy carried by the current is transferred to the voltage by means of capacitive components [28]. Mostly, a VM is made of cascaded FWR [4,7,17], as shown in Figure 3a. However, the cascading rectifier has a detrimental effect on the V TH control [16,20]. Indeed, after each stage, the bias control through the DC common mode at the gate transistor is degraded by overdrive increase. In our previous study, we obtained that VMs with the best PCE and VCE were the ones using two-stage FWR composed of a conventional CCDD as a first stage and a body-biased CCDD as a second stage to consolidate the bias control of the transistor; see Figure 3b.
Another strategy to overcome this difficulty consists of producing an auxiliary bias to level up the gate bias for the second stage [16]. This can be carried out by means of a dynamic change of the common mode (DC) using a level shift of the RF signal input of the DC component from the first stage through the capacitor Cr in Figure 3c. This topology has also the advantage of offering a good drive capability, which offers several choices for the load. All the aforementioned topologies were employed for the present study. For all considered cases, the results are benchmarked with the conventional topology of the CCDD (no body bias, no level shift) in Figure 3a and are labelled as CDC. Topology in Figure 3b are only used for the 32 nm technology node since this topology requires a body bias, which is not physically possible for TFET technology; this topology is labelled as CDB. Finally, the topology in Figure 3c is labelled as CDN, and it was implemented with the two proposed technologies: 32 nm and TFET. In all designs in Figure 3, CF or Cr is the fly capacitance, and CL is the load capacitance. The latter is involved in the smoothing of the signal or ripple reduction. Therefore, if well-sized, it does not discharge during the signal cycles to enable a DC output.
We used mainly two figures of merit (FOMs). First, there was Power Conversion Efficiency (PCE), measuring the output power (Pout) and w.r.t. the input power (Pin) and defined by (2) (a) All the aforementioned topologies were employed for the present study. For all considered cases, the results are benchmarked with the conventional topology of the CCDD (no body bias, no level shift) in Figure 3a and are labelled as CDC. Topology in Figure 3b are only used for the 32 nm technology node since this topology requires a body bias, which is not physically possible for TFET technology; this topology is labelled as CDB. Finally, the topology in Figure 3c is labelled as CDN, and it was implemented with the two proposed technologies: 32 nm and TFET. In all designs in Figure 3, CF or Cr is the fly capacitance, and CL is the load capacitance. The latter is involved in the smoothing of the signal or ripple reduction. Therefore, if well-sized, it does not discharge during the signal cycles to enable a DC output.
We used mainly two figures of merit (FOMs). First, there was Power Conversion Efficiency (PCE), measuring the output power (P out ) and w.r.t. the input power (P in ) and defined by (2) Second, there was Voltage Conversion Efficiency (VCE), measuring the obtained output voltage (v out ) and w.r.t. the ideal DC output (v out_id ) and defined by (2): For a pure single-tone sine signal we obtained that v out_id = 2 π . v in_MAX where v in_MAX is the maximum or amplitude of the input signal. It is worth noting that the voltage conversion ratio is n = 2 based on the circuit topologies used in this work. Note that the ripple factor was negligible since the CL was optimized to properly smooth the output signal; more details will be given in the next section. As explained previously, it is important that a rectifier/VM consume the lowest power of the harvesting system, and this is measured by the PCE. However, good PCE (>60%) is reached for the largest range of input power, and this is assessed by the Dynamic Range (DR) [4]. Indeed, the DR is limited by the reverse leakage phenomenon for high input power (P in ), and this explains the PCE degradation for such P in [29]. Finally, we also considered that these previous requirements had to comply with a good sensitivity defining the threshold P in for V out = 1 V and, therefore, had to be the lowest possible. For all tests, the input value was a pure sinusoidal signal set at f = 950 MHz varying from 0.1 to 0.8 to match with UHD RFID [17] and biomedical application [2,10]. Note that for the 32 nm technology node, we extended the RF input amplitude up to 1.2 V.

Design Optimization and Sizing
The procedure to optimize and design the circuits was based on the method described in [30]. However, in our case, the capacitance and transistor were sized to maximize the PCE in perspective to yield no power losses [13,14]. For each considered technology, the topology was optimized by fixing the load resistance at 50 kΩ and the channel length of the transistors (N-and P-type) to the same value, in the same circuit. For each topology, we applied also the next constraint: the width of all NFET transistors had to be identical in the same stage and the same for the PFET. The optimization procedure was based on the sweep of each capacitor, namely CF or Cr then CL, for a given fixed width transistor value until we reached simultaneously the maximum PCE and VCE and the lowest ripple factor. Then, to obtain the capacitance values, the width of the transistor was swept until we reached the maximum VCE on one side and the maximum PCE on the other side. This procedure enabled us to design symmetrical topologies with good control of the channel resistance. Note that the latter is primordial for the lowest technology node as the 32 nm one. The results of this optimization technique are shown in Figure 4, where the PCE and VCE are plotted as a function of the N/P-MOSFET widths for the TFET and 32 nm technologies. In the following, we consider only the solutions where the PCE and the VCE are maximized by the circuit sizing. Based on that, the transistors and capacitors sizing of the optimized CDC, CDB, and CDN topologies are given in Table 1. Note that the total width is obtained for each transistor, summing all the fingers.

Layout and Parasitic Components
As explained previously, the best way to assess and predict the circuit performance is to simulate the rectifier circuit, including the parasitic components caused by the circuit integration into material. To do so, we laid out the 32 nm circuit using the commercial PDK from TSMC. The developed layouts of the CDC, CDB, and CDN using the 32 nm technology are shown in Figure 5. It is important to highlight that the optimization of the capacitor size was considered for the layout, above all in the LPE extraction step. For the load, a specific port was considered for the connection to the next circuit (e.g., the DC-DC converter). Regarding the TFET technology, there is no commercial design kit; therefore, we could not consider a standard for the TFET-based circuit layout. However, many works have reported TFET fabrication [15,24] and some proposed parasitic component models resulting from the material integration of the TFET. In the present study, we used the model proposed in [23] to provide parasitic components, as in Figure 6a, with an equivalent circuit shown in Figure 6b. We took good care to use the proper physics constants and descriptions related to the materials used to implement our TFET technology: AlGaSb and InAs. Then, we assumed that we would obtain the most realistic results for the use of the TFET technologies with the considered topologies (CDC and CDN). It is worth noting that we did not consider the RC effects of the path from the circuit to Cr, CF, and CL for the TFET since no model considers it. However, for the 32 nm, we considered both cases with and without these specific effects, and no more than a 1% variation in the results was observed. Therefore, we assumed that their effect was negligible for the comparison of both technologies.
capacitor size was considered for the layout, above all in the LPE extraction step. For the load, a specific port was considered for the connection to the next circuit (e.g., the DC-DC converter). Regarding the TFET technology, there is no commercial design kit; therefore, we could not consider a standard for the TFET-based circuit layout. However, many works have reported TFET fabrication [15,24] and some proposed parasitic component models resulting from the material integration of the TFET. In the present study, we used the model proposed in [23] to provide parasitic components, as in Figure 6a, with an equivalent circuit shown in Figure 6b. We took good care to use the proper physics constants and descriptions related to the materials used to implement our TFET technology: AlGaSb and InAs. Then, we assumed that we would obtain the most realistic results for the use of the TFET technologies with the considered topologies (CDC and CDN). It is worth noting that we did not consider the RC effects of the path from the circuit to Cr, CF, and CL for the TFET since no model considers it. However, for the 32 nm, we considered both cases with and without these specific effects, and no more than a 1% variation in the results was observed. Therefore, we assumed that their effect was negligible for the comparison of both technologies.

Results and Discussion
The FOMs (PCE and VCE) were extracted from the electrical simulations of the layouts in Figure 5, and the models described in Figure 6 were shown in the previous section. We considered the 32 nm planar and TFET technologies applied to the three different circuit topologies (Figure 3). Note that the results are benchmarked with the ones provided by the circuit simulation of the conventional CCDD labelled as CDC (Figure 3a) [13].
As expected in Figure 7a, the PCE increases as a function of the Pin up to a maximum (PCEpeak), which is the best yield for the circuit in terms of power consumption and provided output power. In the best conditions, this peak should coincide with the maximum output voltage (Vout) that can be delivered to the circuit for the best yield. In this regime (up to the peak), the PCE suggests that the transistors in the circuit, under the bias condition and for given input level, work in a such way that in OFF state, they properly block the reverse leakage current. Therefore, the peak suggests that the gate overdrive satisfies the least or lowest charge displacement on the gate to switch the transistor from the cut-

Results and Discussion
The FOMs (PCE and VCE) were extracted from the electrical simulations of the layouts in Figure 5, and the models described in Figure 6 were shown in the previous section. We considered the 32 nm planar and TFET technologies applied to the three different circuit topologies (Figure 3). Note that the results are benchmarked with the ones provided by the circuit simulation of the conventional CCDD labelled as CDC (Figure 3a) [13].
As expected in Figure 7a, the PCE increases as a function of the P in up to a maximum (PCE peak ), which is the best yield for the circuit in terms of power consumption and provided output power. In the best conditions, this peak should coincide with the maximum output voltage (V out ) that can be delivered to the circuit for the best yield. In this regime (up to the peak), the PCE suggests that the transistors in the circuit, under the bias condition and for given input level, work in a such way that in OFF state, they properly block the reverse leakage current. Therefore, the peak suggests that the gate overdrive satisfies the least or lowest charge displacement on the gate to switch the transistor from the cut-off to the triode regime.
Electronics 2022, 11, x FOR PEER REVIEW 10 of TFET would increase the resistance current in the triode regime (high RON), and the amb polarity phenomenon would increase the reverse current leakage in OFF state. As a resu the PCE most importantly decreases for large VG and Pin with the TFET.
(a) (b) Figure 7. The FOM to assess the performance of the different topologies for different technology: the PCE and (b) the VCE. In (a), the PCE for the TFET is the DR (>60%), which is increased from dBm to 8 dBm or 3 µW to 6 µW. For the 32 nm, the DR is not improved if we use the back bias control the VTH (CDB circuit). The PCE is importantly degraded for the CDN topology with 32 nm As compared with our previous work [8][9][10], we would have expected an improv ment of the PCE with the body-bias (CDB) topology with the 32 nm; this topology is n applicable for TFET technology since no back contact is physically possible [28]. Howev in Figure 7a, we can observe that there was no significant change between the CDC an CDB topology. We can assume that for such topology, the conventional planar 32 n faced large electrostatic effects that prevented a good control from the back gate. W would suggest for a future work to apply to this topology the FDSOI technology to answ this question. On the other side of the VCE, Figure 7b, the maximum value is limited 65% for the CDC and CDB topologies with the 32 nm technology, while the TFET-bas circuits show VCE at 15% lower. However, an improvement of 60% is observed, while t CDN topology is considered with the TFET.
The output voltage (Vout) is plotted in Figure 8a as a function of the input power (P and the input voltage (Vin) in Figure 8b. The 1 V-sensitivity extracted in Figure 8a show that TFET-based circuits presented a better sensitivity with a 10% improvement with t CDC topology (−14 dBm) and 30% with the CDN topology (−15.6 dBm). Regarding the Figure 7. The FOM to assess the performance of the different topologies for different technology: (a) the PCE and (b) the VCE. In (a), the PCE for the TFET is the DR (>60%), which is increased from 5 dBm to 8 dBm or 3 µW to 6 µW. For the 32 nm, the DR is not improved if we use the back bias to control the V TH (CDB circuit). The PCE is importantly degraded for the CDN topology with 32 nm.
Once the peak is reached, the PCE decreases as the P in increases, suggesting that the transistors are not able to block the leakage current since the signal level is too high; this is equivalent to the peak reverse voltage for diode devices. For the 32 nm, this is clearly explained by the source/drain leakage junction, while for the TFET, this is explained by the ambipolarity phenomenon [23,31]. As explained in Section 2, the use of the topologies should improve these intrinsic technology limits. We stress that the performance metric used to assess how much P in the circuit can hold in a given PCE is provided by the DR. In our case, we decided to define two DRs: one for PCE > 60% and one for PCE > 20%. In the case of the TFET, the DR increased by 200% when we used the CDN topology instead of the CDC topology (conventional CCDD). We also observed that the TFET always offered a much higher DR than 32 nm (1 to 4 dB larger). In addition, the conventional topology (CDC) designed with the 32 nm iPDK displayed a lower PCE peak (−4%) compared to the one designed with the TFET. This peak is slightly improved when we use the CDN topology for the TFET but is widely degraded with the 32 nm and the latter can only offer good performance for a DR > 20% (Figure 7a). Note that it was reported that a PCE of about 40% in other works used the same topology in 180 nm technology (planar). On the other hand, the TFET technology demonstrated that low voltage activation greatly increases the PCE for such design strategy, offering new options for the designer. It is important to highlight that the TFET physics model used in this work is limited to V G = 0.8 V. If one considers larger voltage, low ON-currents caused by the conduction mechanism of the TFET would increase the resistance current in the triode regime (high R ON ), and the ambipolarity phenomenon would increase the reverse current leakage in OFF state. As a result, the PCE most importantly decreases for large V G and P in with the TFET.
As compared with our previous work [8][9][10], we would have expected an improvement of the PCE with the body-bias (CDB) topology with the 32 nm; this topology is not applicable for TFET technology since no back contact is physically possible [28]. However, in Figure 7a, we can observe that there was no significant change between the CDC and CDB topology. We can assume that for such topology, the conventional planar 32 nm faced large electrostatic effects that prevented a good control from the back gate. We would suggest for a future work to apply to this topology the FDSOI technology to answer this question. On the other side of the VCE, Figure 7b, the maximum value is limited at 65% for the CDC and CDB topologies with the 32 nm technology, while the TFET-based circuits show VCE at 15% lower. However, an improvement of 60% is observed, while the CDN topology is considered with the TFET.
The output voltage (V out ) is plotted in Figure 8a as a function of the input power (P in ) and the input voltage (V in ) in Figure 8b. The 1 V-sensitivity extracted in Figure 8a shows that TFET-based circuits presented a better sensitivity with a 10% improvement with the CDC topology (−14 dBm) and 30% with the CDN topology (−15.6 dBm). Regarding the 32 nmbased circuits, sensitivity was at best −12.5 dBm with the CBC, CDB, and CBN topologies. We also introduce the Yield Factor, which is defined as DR (>60%)/Sensitivity (1 V).
This one is the maximum when we consider the CDN topology with the TFET technology, which is interpreted as the circuit that offers the largest DR and the lowest sensitivity for the different studied cases. All the FOM and performance assessments are summarized in Table 2.
As a result, for the 32 nm with conventional CCDD, we obtained within the DR (>60%) a V out of 0.55 to 0.75 V (VCE maximum of 65.5%) providing an output power ranging from 8.4 to 19.4 µW with a V out = 0.7 V for a PCE peak of 64%. An attempt to improve the performance by controlling the V TH by a bulk contact (CDB topology) did not significantly improve these results, and, more critically, the DR barely improved (4 dB against 3.5 dB), suggesting that the back bias is not effective for this technology for the CCDD topology since reverse currents for a larger bias cannot be sufficiently controlled this way. By comparison, the conventional CCDD using the TFET present within the DR (>60%) has a V out ranging from 0.37 to 0.72 V (VCE max of 53%), providing an output power ranging from 6.2 to 19.5 µW. It is worth remembering that an increase from 3.5 to 5 dB was obtained with the TFET in comparison with the 32 nm obtained with the CDC circuit. This also led to a 1 dB improvement of the 1 V-sensitivity. Interestingly, the most significant performance improvement was obtained with the CDN topology. Indeed, it was reported that with planar technology, this topology shows good VCE at the price of a reduced PCE with a 50 kΩ-load [6]. In our previous work, we already observed that the scaling from 90 nm to 32 nm was not so advantageous since the obtained VCE remained close to the one from the conventional CCDD topology for a PCE in the range of only 25-35%. In this present work, we obtained similar PCE with V out within the DR (>20%), which ranged from 0.25 to 0.6 V for an output power from 4 to 36 µW. In that case, the 1 V-sensitivity was not lower than 12.5 dB, suggesting a circuit producing an output of 1 V for a P in = 224 µW. However, and as shown in Figures 7 and 8, the design of the CDN topology that used the TFET technology showed interesting results. In that case, a maximum VCE of 82% with a peak of PCE of 70% was obtained. In that case, within the DR > 60%, a V out ranging from 0.45 to 1 V (0.9 at PCE peak ) with an output power ranging from 6.17 µW to 35 µW (13 µW at the peak) and a 1 V-sensitivity of −15.6 dB (the lowest) was obtained. In other terms, the 1 V-level output was produced in the range of the considered DR (60%), which meant a good power yield; note that it was the largest DR since it was about 8 dB.
Electronics 2022, 11, x FOR PEER REVIEW 11 of 1 nm-based circuits, sensitivity was at best −12.5 dBm with the CBC, CDB, and CBN topo ogies. We also introduce the Yield Factor, which is defined as DR (>60%)/Sensitivity (1 V (a) (b) This one is the maximum when we consider the CDN topology with the TFET tech nology, which is interpreted as the circuit that offers the largest DR and the lowest sens tivity for the different studied cases. All the FOM and performance assessments are sum marized in Table 2.
As a result, for the 32 nm with conventional CCDD, we obtained within the D (>60%) a Vout of 0.55 to 0.75 V (VCE maximum of 65.5%) providing an output power rang ing from 8.4 to 19.4 µW with a Vout = 0.7 V for a PCEpeak of 64%. An attempt to improve th performance by controlling the VTH by a bulk contact (CDB topology) did not significantl improve these results, and, more critically, the DR barely improved (4 dB against 3.5 dB suggesting that the back bias is not effective for this technology for the CCDD topolog  As a result, the TFET-based rectifier/multiplier enables a good PCE for larger input power. It is worth remembering that the advantages of the TFET are a low switching energy at the gate resulting from a subthreshold slope below the 60 mV/dec planar technology limit, along with a V TH in the range of 200 mV and an extremely high output impedance [22,32]. Furthermore, the used TFETs were unidirectional, producing an extremely low reverse leakage current [20,21,32]. All these features explain the very good PCE performance with both topologies (Table 2) and the highest V out values for V in ≈ V TH and low P in (Figure 8). However, in the triode regime (V in >> V TH) , the TFET yielded a low output current in ON state and too large a reverse current caused by ambipolarity in OFF state for large amplitude input signal. Additionally, we may expect improvement of the TFET technology to obtain a higher DR [33].
To conclude, the rectifier circuit needs an active switching device that can work with a low power budget. This means that in the range of small signals, as mostly observed for the RF-DC converter, topologies such as the CDN can keep improving performance through scaling only if we switch to other technologies than planar, and the TFET is a very good example for the purpose of this goal.

Conclusions
Conventional and based CCDD circuit topologies have been considered to implement multipliers for RFEH systems. These circuits have been optimized for the 32 nm planar and TFET nonplanar technologies by including the parasitic effect, resulting in a layout implementation. The performance metrics based on PCE and VCE FOM were extracted and compared. It resulted that the conventional circuit topology designed with TFET technology presented better dynamic range (PCE > 60%) and 1 V-Sensitivity (1 dB) performance than the one designed with the 32 nm. The performance improvement became considerable during the design of the CDN topology: the TFET circuit simulations demonstrated a +3 dB of DR (60%) and a reduction of almost 3 dB for the 1 V-sensitivity. Furthermore, the latter showed a 1 V output within the DR (>60%).
We conclude that from 32 nm, the planar technology shows some weakness for such a circuit. For instance, the body bias contact topology does not bring better DR, suggesting a V TH control less efficient than expected and likely explained by weak control of electrostatic. A FDSOI-based design could answer this problem. On the other hand, the specific features of the TFET, such as a low switching energy at the gate resulting from a subthreshold slope below the 60 mV/dec with a V TH in the range of 200 mV and an extremely high output impedance, support superior performance with specific topology. Furthermore, TFET technology opens new perspectives for CCDD bridge circuits to proposes solutions regarding the future needs with multiplier rectifier circuits used for RFEH systems.