Decoder-Type Scan Driver Suitable for Flexible and Stretchable Displays

: The integration of a scan drive circuit is required for ﬂexible and stretchable displays because a rigid scan driver IC is not ﬂexible and stretchable. In this study, decoder-type scan drivers were developed using amorphous IGZO thin-ﬁlm transistors for both depletion and enhancement mode TFTs. Simulations and measurements show that the proposed decoder-type scan driver operates well for both the enhancement and depletion-mode TFTs without error. The measurement results show that the proposed circuit provides scan pulses well, even with depletion-mode TFTs with a large negative threshold voltage of around − 25 V.


Introduction
Flat-panel displays such as liquid crystal display (LCD) and organic light-emitting diode (OLED) displays use a backplane with thin-film transistors (TFTs). Hydrogenated amorphous silicon (a-Si:H), low-temperature polycrystalline silicon (LTPS), and oxide TFTs are typically used for flat-panel displays [1][2][3]. To display images on a panel, display driver ICs (DDIs) are attached to a panel to interface with the electrical signals from image sources. A scan driver is used to select a horizontal line to write image data to pixels on a panel. In active-matrix displays, image data are written on a panel line by line. A scan driver selects a line to which image data are written [4].
The integration of the scan driver enables a narrow bezel and good reliability of the module. In addition, unlike a rigid scan driver IC, it is suitable for flexible displays with various form factors, or for stretchable displays that can be stretched like rubber. An integrated data drive circuit and scan driver has been developed, but due to high-level requirements, integrated scan drivers are mostly being used in LCD or OLED displays [5][6][7].
A typical scan driver is composed of a shift register, level shifter, and buffer. The shift register is a cascade of flip-flops and the output of a flip-flop is transferred to the input of the next flip-flop. An input start pulse to the first flip-flop of the shift register is shifted to the next flip-flop one by one, in sync with clocks. Each output is processed by a level shifter to turn TFTs on and off. Finally, a TFT of the pixel is turned on and off after increasing the driving ability by a buffer [8,9].
An inverter is a basic logic gate for designing a digital circuit, and CMOS inverters are widely used due to their high speed, low static current, and low power consumption. However, the use of a CMOS inverter is not possible with a-Si:H and oxide TFTs due to the absence of p-channel TFTs. Inverters with only n-channel TFTs show voltage loss, large static current, and offset voltage in a low output state [10]. To overcome these issues, several scan driver circuits have been proposed, including a scan driver with a-Si:H TFTs consisting of four TFTs and one capacitor [11]. In this circuit, the gate voltage of a drive TFT is bootstrapped when the output voltage increases to a high level. The gate voltage increased by bootstrapping reduces the voltage loss of the output pulse and increases the current driving ability. However, when the scan output is low, the scan output node floats and is not connected to any voltage source. Therefore, the output is unstable during the off state, which deteriorates the image quality. Circuits that reduce the output noise were proposed which use clock signal coupling [12][13][14].
However, there is an issue to consider when implementing these circuits on a flexible display. Flexible displays are subjected to external mechanical stress, which induces electrical failure. Therefore, conventional scan drivers in which the output of a stage becomes the input of the next stage are not suitable for flexible displays because when a stage is faulty, all the subsequent stages become faulty as well [4].
There are studies on decoder-type scan drivers to simplify the conventional scan drive circuit and increase circuit stability. A decoder-type scan driver was proposed using a-Si:H TFTs [15], and improved by reducing the signal lines and area of the circuit [16]. A carry-free scan driver using a-IGZO oxide TFTs was also proposed. It was manufactured on a flexible PI substrate and showed stable operation even after the 10,000 cycles of a bending test with a bending radius of 2 mm [6]. However, oxide TFTs including a-IGZO TFT often exhibit depletion-mode characteristics which have a negative threshold voltage (Vth), and a negative shift of the Vth by light illumination and negative bias stress [17][18][19][20][21][22][23][24][25]. The band-gap states and adsorption of oxygen and water molecules were studied in terms of the stability of the oxide TFTs. The adsorption and desorption of the oxygen and water molecules onto the backchannel were found to affect the stability of oxide TFTs [25]. However, in the top-gate structure TFT used in this study, the gate insulator and the gate metal act as passivation layers. Therefore, in the top gate structure, band-gap states play an important role in the instability of the oxide TFTs. It is known that oxygen vacancy states below the Fermi level act as donors when ionized by light illumination, which is the reason for the large negative shift under illumination. Therefore, the control of the oxygen vacancy is important to control the threshold voltages of the oxide TFTs. The large amount of oxygen vacancy results in a depletion-mode TFT by the donor states generated by thermally ionized oxygen vacancies. Due to the depletion-mode characteristics of the a-IGZO TFT, many problems arise when driving a conventional gate drive circuit [26]. To solve this problem, many research groups have proposed gate drive circuits that can be operated with depletion-mode oxide TFTs [26][27][28][29][30][31][32][33].
In a circuit, leakage control is difficult with depletion-mode TFTs because the off state is not realized by zero gate bias with zero-volt ground. To turn off a depletion-mode TFT, the gate bias should be lower than the source and drain voltages. One circuit for a depletionmode TFT uses multiple grounds with different voltages, and others use bootstrapping to shift the gate voltage to the negative and two series-connected transistors [28][29][30][31][32][33]. All these circuits require a design change when the mode of the TFT changes from enhancement mode to depletion mode. A circuit which is adaptive to both the enhancement and depletion modes can be used in any case without a design change.
In this work, a scan driver that can operate well for both the enhancement and depletion mode is proposed. The proposed circuit is evaluated by simulation and measurement. It is suitable for a flexible backplane of a display because of its small circuit area due to a reduced number of TFTs and decoder-type block driving. The proposed scan drive circuits are fabricated on a glass substrate using a-IGZO TFTs to verify their performance.

Proposed Scan Drivers
A unit stage of the proposed scan driver and its timing chart are shown in Figure 1a,b. When PS is high, TFT T1 is turned on and node P is charged with the high voltage of the PS signal, which turns on TFT T2. The scan output then becomes high when SS becomes high. Increase of the scan voltage bootstraps node P's voltage up using coupling capacitor C1. Bootstrapping the gate voltage of T2 reduces the threshold voltage loss of the scan output. The voltage of PS should be higher than SS by more than the threshold voltage in order to avoid output-voltage loss and low on current because V gs = V g − V s is given by V PS − V SS . Low Vgs results in a drop of the output voltage and long rise and fall times of the output voltage in order to avoid output-voltage loss and low on current because = − is given by − . Low Vgs results in a drop of the output voltage and long rise and fall times of the output pulses. The bootstrapped gate voltage of the drive TFT reduces the rise time of the output pulse by increasing the current driving ability.
When the scan output is high, TFTs T4 and T3 are turned off by PSB. When SS becomes low, the scan output becomes low. To avoid a floating state in the scan line, PSB becomes high when PS becomes low. When PS is low and PSB is high, T3 and T4 turn on. Then, node P is discharged to the ground level, and the scan is electrically connected to the ground level to avoid a floating state in the scan line. The scan driver should provide sequential outputs to scan lines; Figure 2a shows its block diagram, and Figure 2b shows its timing chart. The driver consists of several blocks that use multiple SS signals; Figure 2a shows 30 SS signals. After the PS1 pulse becomes high, all the TFTs in block 1 turn on, and SS signals appear at the scan output sequentially from SS1 to SS30. Next, a PS2 pulse is applied to all the TFTs in block 2, which in turn output SSs from SS1 to SS30 sequentially. By adjusting the number N of SS pulses and the number M of blocks, we can scan M × N lines.  When the scan output is high, TFTs T4 and T3 are turned off by PSB. When SS becomes low, the scan output becomes low. To avoid a floating state in the scan line, PSB becomes high when PS becomes low. When PS is low and PSB is high, T3 and T4 turn on. Then, node P is discharged to the ground level, and the scan is electrically connected to the ground level to avoid a floating state in the scan line.
The scan driver should provide sequential outputs to scan lines; Figure 2a shows its block diagram, and Figure 2b shows its timing chart. The driver consists of several blocks that use multiple SS signals; Figure 2a shows 30 SS signals. After the PS1 pulse becomes high, all the TFTs in block 1 turn on, and SS signals appear at the scan output sequentially from SS1 to SS30. Next, a PS2 pulse is applied to all the TFTs in block 2, which in turn output SSs from SS1 to SS30 sequentially. By adjusting the number N of SS pulses and the number M of blocks, we can scan M × N lines.
Electronics 2021, 10, x FOR PEER REVIEW 3 of 12 voltage in order to avoid output-voltage loss and low on current because = − is given by − . Low Vgs results in a drop of the output voltage and long rise and fall times of the output pulses. The bootstrapped gate voltage of the drive TFT reduces the rise time of the output pulse by increasing the current driving ability.
When the scan output is high, TFTs T4 and T3 are turned off by PSB. When SS becomes low, the scan output becomes low. To avoid a floating state in the scan line, PSB becomes high when PS becomes low. When PS is low and PSB is high, T3 and T4 turn on. Then, node P is discharged to the ground level, and the scan is electrically connected to the ground level to avoid a floating state in the scan line. The scan driver should provide sequential outputs to scan lines; Figure 2a shows its block diagram, and Figure 2b shows its timing chart. The driver consists of several blocks that use multiple SS signals; Figure 2a shows 30 SS signals. After the PS1 pulse becomes high, all the TFTs in block 1 turn on, and SS signals appear at the scan output sequentially from SS1 to SS30. Next, a PS2 pulse is applied to all the TFTs in block 2, which in turn output SSs from SS1 to SS30 sequentially. By adjusting the number N of SS pulses and the number M of blocks, we can scan M × N lines.    Figure 3a shows simulation results for both the unit stage of the proposed scan driver and a scan driver with two switch TFTs, as shown in Figure 4. PS, PSB, and SS signals are shown, and the output pulses are shown at the lowest. The pulses from both the circuit in Figure 4 and the proposed one are shown and replotted in Figure 3b. Output voltages in Figure 3b show the effect of bootstrapping in the proposed circuit-the voltage loss was reduced for the proposed circuit. Increasing the gate voltage of the drive TFT by bootstrapping shortened the rise time and reduced the voltage drop in the output. Table 1 shows that the rise time decreased to 26.9 µs from 174.5 µs, and the ratio of the output voltage to SS increased from 0.863 to 0.999.
Electronics 2021, 10, x FOR PEER REVIEW 4 of 12 Figure 3a shows simulation results for both the unit stage of the proposed scan driver and a scan driver with two switch TFTs, as shown in Figure 4. PS, PSB, and SS signals are shown, and the output pulses are shown at the lowest. The pulses from both the circuit in Figure 4 and the proposed one are shown and replotted in Figure 3b. Output voltages in Figure 3b show the effect of bootstrapping in the proposed circuit-the voltage loss was reduced for the proposed circuit. Increasing the gate voltage of the drive TFT by bootstrapping shortened the rise time and reduced the voltage drop in the output. Table 1 shows that the rise time decreased to 26.9 μs from 174.5 μs, and the ratio of the output voltage to SS increased from 0.863 to 0.999.   The gate of TFT T1 in Figure 1a is connected to the drain electrode and acts as a diode. However, with a depletion-mode a-IGZO TFT, currents flow even in reverse bias because the off state cannot be accomplished with zero bias between the gate and drain. Therefore, currents flow even in reverse bias with the drain voltage lower than the source voltage. As a result, during the increase of the node P voltage by bootstrapping, current flows through T1, and bootstrapping does not occur.
To settle this issue, the gate and drain electrodes of T1 are separated as shown in Figure 5a. The timing chart is shown in Figure 5b. Unlike the previous bootstrapped circuit, the drain of T1 is not connected to the gate and is connected to Vpulse. and a scan driver with two switch TFTs, as shown in Figure 4. PS, PSB, and SS signals are shown, and the output pulses are shown at the lowest. The pulses from both the circuit in Figure 4 and the proposed one are shown and replotted in Figure 3b. Output voltages in Figure 3b show the effect of bootstrapping in the proposed circuit-the voltage loss was reduced for the proposed circuit. Increasing the gate voltage of the drive TFT by bootstrapping shortened the rise time and reduced the voltage drop in the output. Table 1 shows that the rise time decreased to 26.9 μs from 174.5 μs, and the ratio of the output voltage to SS increased from 0.863 to 0.999.   The gate of TFT T1 in Figure 1a is connected to the drain electrode and acts as a diode. However, with a depletion-mode a-IGZO TFT, currents flow even in reverse bias because the off state cannot be accomplished with zero bias between the gate and drain. Therefore, currents flow even in reverse bias with the drain voltage lower than the source voltage. As a result, during the increase of the node P voltage by bootstrapping, current flows through T1, and bootstrapping does not occur.
To settle this issue, the gate and drain electrodes of T1 are separated as shown in Figure 5a. The timing chart is shown in Figure 5b. Unlike the previous bootstrapped circuit, the drain of T1 is not connected to the gate and is connected to Vpulse.  The gate of TFT T1 in Figure 1a is connected to the drain electrode and acts as a diode. However, with a depletion-mode a-IGZO TFT, currents flow even in reverse bias because the off state cannot be accomplished with zero bias between the gate and drain. Therefore, currents flow even in reverse bias with the drain voltage lower than the source voltage. As a result, during the increase of the node P voltage by bootstrapping, current flows through T1, and bootstrapping does not occur.
To settle this issue, the gate and drain electrodes of T1 are separated as shown in Figure 5a. The timing chart is shown in Figure 5b. Unlike the previous bootstrapped circuit, the drain of T1 is not connected to the gate and is connected to Vpulse. The operation of the modified bootstrap scan driver is shown in Figure 6. In the reset period, the PSB signal is high, and TFTs T3 and T4 are turned on. The scan line of the previous stage is initialized through TFT T4. In addition, since Vpulse is in a high state, a high voltage of Vpulse is charged in node P, which in turn turns on T2. In the output period, PS and Vpulse become high, which turns on TFTs T1 and T2. When SS becomes high in the output period, the scan output increases, which bootstraps the node P voltage through coupling capacitor C1. The PS low voltage should be lower than that of Vpulse to make T1 be in an off state, which enables the bootstrapping in node P by the low leakage of T1. The increased gate voltage of T2 by bootstrapping prevents voltage loss of the SS output to the scan line.   Figure 8a,b shows the simulation results from using parameters of the depletion-mode TFT as shown in Figure 7. Figure 8a shows the result for the proposed circuit shown in Figure 1a, and Figure 8b shows the result for the modified circuit shown in Figure 5a. The modified bootstrap circuit showed improved error-free driving capability because the current flowing through T1 during bootstrapping to the T2 gate was suppressed by applying the appropriate voltages of Vpulse and PS. Since one advantage of the proposed circuit is adaptive operation for both the enhancement and depletion-mode TFTs without design change, we verified the operation using enhancement-mode TFT parameters as shown in Figure 8c. The operation of the modified bootstrap scan driver is shown in Figure 6. In the reset period, the PSB signal is high, and TFTs T3 and T4 are turned on. The scan line of the previous stage is initialized through TFT T4. In addition, since Vpulse is in a high state, a high voltage of Vpulse is charged in node P, which in turn turns on T2. In the output period, PS and Vpulse become high, which turns on TFTs T1 and T2. When SS becomes high in the output period, the scan output increases, which bootstraps the node P voltage through coupling capacitor C1. The PS low voltage should be lower than that of Vpulse to make T1 be in an off state, which enables the bootstrapping in node P by the low leakage of T1. The increased gate voltage of T2 by bootstrapping prevents voltage loss of the SS output to the scan line. The operation of the modified bootstrap scan driver is shown in Figure 6. In the reset period, the PSB signal is high, and TFTs T3 and T4 are turned on. The scan line of the previous stage is initialized through TFT T4. In addition, since Vpulse is in a high state, a high voltage of Vpulse is charged in node P, which in turn turns on T2. In the output period, PS and Vpulse become high, which turns on TFTs T1 and T2. When SS becomes high in the output period, the scan output increases, which bootstraps the node P voltage through coupling capacitor C1. The PS low voltage should be lower than that of Vpulse to make T1 be in an off state, which enables the bootstrapping in node P by the low leakage of T1. The increased gate voltage of T2 by bootstrapping prevents voltage loss of the SS output to the scan line.   Figure 8a,b shows the simulation results from using parameters of the depletion-mode TFT as shown in Figure 7. Figure 8a shows the result for the proposed circuit shown in Figure 1a, and Figure 8b shows the result for the modified circuit shown in Figure 5a. The modified bootstrap circuit showed improved error-free driving capability because the current flowing through T1 during bootstrapping to the T2 gate was suppressed by applying the appropriate voltages of Vpulse and PS. Since one advantage of the proposed circuit is adaptive operation for both the enhancement and depletion-mode TFTs without design change, we verified the operation using enhancement-mode TFT parameters as shown in Figure 8c.  Figure 7 shows the transfer characteristics of the depletion-mode TFT. Figure 8a,b shows the simulation results from using parameters of the depletion-mode TFT as shown in Figure 7. Figure 8a shows the result for the proposed circuit shown in Figure 1a, and Figure 8b shows the result for the modified circuit shown in Figure 5a. The modified bootstrap circuit showed improved error-free driving capability because the current flowing through T1 during bootstrapping to the T2 gate was suppressed by applying the appropriate voltages of Vpulse and PS. Since one advantage of the proposed circuit is adaptive operation for both the enhancement and depletion-mode TFTs without design change, we verified the operation using enhancement-mode TFT parameters as shown in Figure 8c. We changed the threshold voltage parameter to 20 V for the enhancement-mode simulation. Figure 8c shows the output waveforms without error. The rise time increased because the threshold voltage was large for the worst-case simulation.
Electronics 2021, 10, x FOR PEER REVIEW 6 of 12 We changed the threshold voltage parameter to 20 V for the enhancement-mode simulation. Figure 8c shows the output waveforms without error. The rise time increased because the threshold voltage was large for the worst-case simulation. Figure 9 shows a more detailed comparison between outputs for both the bootstrap circuit and modified bootstrap circuit. Improved results with the modified bootstrap scan driver are summarized in Table 2. The rise time decreased to 12.3 μs from 68.4 μs, and the fall time decreased to 10.9 μs from 60.5 μs.  We changed the threshold voltage parameter to 20 V for the enhancement-mode simulation. Figure 8c shows the output waveforms without error. The rise time increased because the threshold voltage was large for the worst-case simulation. Figure 9 shows a more detailed comparison between outputs for both the bootstrap circuit and modified bootstrap circuit. Improved results with the modified bootstrap scan driver are summarized in Table 2. The rise time decreased to 12.3 μs from 68.4 μs, and the fall time decreased to 10.9 μs from 60.5 μs.   Figure 9 shows a more detailed comparison between outputs for both the bootstrap circuit and modified bootstrap circuit. Improved results with the modified bootstrap scan driver are summarized in Table 2. The rise time decreased to 12.3 µs from 68.4 µs, and the fall time decreased to 10.9 µs from 60.5 µs.
Electronics 2021, 10, x FOR PEER REVIEW 6 of 12 We changed the threshold voltage parameter to 20 V for the enhancement-mode simulation. Figure 8c shows the output waveforms without error. The rise time increased because the threshold voltage was large for the worst-case simulation. Figure 9 shows a more detailed comparison between outputs for both the bootstrap circuit and modified bootstrap circuit. Improved results with the modified bootstrap scan driver are summarized in Table 2. The rise time decreased to 12.3 μs from 68.4 μs, and the fall time decreased to 10.9 μs from 60.5 μs.

Materials and Methods
Drive circuits were fabricated using an a-IGZO TFT process on a glass substrate. The cross-sectional structure and a microscopic image of the top-gate a-IGZO TFT are shown in Figure 10a,b, respectively. A 50 nm-thick active layer of a-IGZO was deposited by RF magnetron sputtering with Ar gas mixed with O 2 gas (Ar:O 2 = 22.5 sccm:7.5 sccm) using an IGZO target (In 2 O 3 :Ga 2 O 3 :ZnO = 2:1:2 in mole ratio). The working pressure was 5 mTorr, and the power was 50 W.

Materials and Methods
Drive circuits were fabricated using an a-IGZO TFT process on a glass substrate. The cross-sectional structure and a microscopic image of the top-gate a-IGZO TFT are shown in Figure 10a,b, respectively. A 50 nm-thick active layer of a-IGZO was deposited by RF magnetron sputtering with Ar gas mixed with O2 gas (Ar:O2 = 22.5 sccm:7.5 sccm) using an IGZO target (In2O3:Ga2O3:ZnO = 2:1:2 in mole ratio). The working pressure was 5 mTorr, and the power was 50 W.
After making a photoresist pattern by photolithography, the a-IGZO layer was etched by buffered oxide etchant (BOE) diluted with water at a 500:1 ratio to make an a-IGZO active pattern. A 500 nm-thick gate insulator was formed by spin-coating SU-8 negative photoresist, followed by a curing process. A 200 nm-thick Al layer was deposited by DC magnetron sputtering. The working pressure of Al sputtering was 5 mTorr in Ar gas, and the DC power was 250 W. After deposition of Al, it was wet-etched to form a gate electrode.
After the gate pattern, SU-8 insulator was removed except for the part under the gate electrode. This was done by reactive ion etching (RIE) with oxygen plasma, a flow rate of 60 sccm, and power of 180 W. During over-etching of the SU-8 insulator, the source and drain regions of IGZO were doped to achieve low sheet resistance. Then, 500 nm-thick SU-8 was formed for inter-layer dielectrics (ILDs) by spin-coating and curing. After contact hole etching by RIE, Al was deposited by DC magnetron sputtering and patterned by wet etching to form source and drain electrodes.  Figure 11 shows the transfer characteristics of the fabricated a-IGZO TFT with a channel width and length of 100 and 10 μm, respectively. The fabricated TFT showed negative shift in the transfer characteristics, which can be attributed to both the oxygen vacancies and the hydrogen ion in the SU-8 gate insulator. The oxygen vacancies act as donors when ionized by molecular vibration energy, which results in a negative shift of the threshold voltage by increased carrier density. The other factor explaining the negative shift is the hydrogen atom in the SU-8 gate insulator, because the hydrogen is believed to serve as a donor in the IGZO layer. The hydrogen ions are generated during UV illumination for After making a photoresist pattern by photolithography, the a-IGZO layer was etched by buffered oxide etchant (BOE) diluted with water at a 500:1 ratio to make an a-IGZO active pattern. A 500 nm-thick gate insulator was formed by spin-coating SU-8 negative photoresist, followed by a curing process. A 200 nm-thick Al layer was deposited by DC magnetron sputtering. The working pressure of Al sputtering was 5 mTorr in Ar gas, and the DC power was 250 W. After deposition of Al, it was wet-etched to form a gate electrode.

Results and Discussion
After the gate pattern, SU-8 insulator was removed except for the part under the gate electrode. This was done by reactive ion etching (RIE) with oxygen plasma, a flow rate of 60 sccm, and power of 180 W. During over-etching of the SU-8 insulator, the source and drain regions of IGZO were doped to achieve low sheet resistance. Then, 500 nm-thick SU-8 was formed for inter-layer dielectrics (ILDs) by spin-coating and curing. After contact hole etching by RIE, Al was deposited by DC magnetron sputtering and patterned by wet etching to form source and drain electrodes. Figure 11 shows the transfer characteristics of the fabricated a-IGZO TFT with a channel width and length of 100 and 10 µm, respectively. The fabricated TFT showed negative shift in the transfer characteristics, which can be attributed to both the oxygen vacancies and the hydrogen ion in the SU-8 gate insulator. The oxygen vacancies act as donors when ionized by molecular vibration energy, which results in a negative shift of the threshold voltage by increased carrier density. The other factor explaining the negative shift is the hydrogen atom in the SU-8 gate insulator, because the hydrogen is believed to serve as a donor in the IGZO layer. The hydrogen ions are generated during UV illumination for curing the SU-8 negative photoresist. Therefore, the remaining hydrogen in SU-8 gate curing the SU-8 negative photoresist. Therefore, the remaining hydrogen in SU-8 gate insulator can diffuse into the IGZO interface, which results in the negative shift of the threshold voltage by increased carrier density. Figure 11. Transfer characteristics of the fabricated a-IGZO TFT. Table 3 shows the parameters extracted from the fabricated a-IGZO TFT. The fieldeffect mobility and on/off ratio were 6.2 cm 2 /V•s and 2.1 × 10 7 , respectively. The subthreshold swing was 1.8 V/dec, and the threshold voltage was −4.8 V. The mobility and threshold voltage were obtained from the saturation current (Ids) Equation (1):

Results and Discussion
where W and L are channel width and length, respectively. Cox is the capacitance of the gate insulator per unit area and is a field effect mobility. The subthreshold swing (SS) was obtained according to Equation (2).  Figure 12a,b. Figure 12a shows the bootstrap scan driver, and Figure 12b shows the modified bootstrap scan driver. The circuit area of a unit stage was 620 μm × 290 μm. The design parameters of the scan drivers are indicated in Table 4. In order to ensure driving capability, the size of the drive TFT, T2, was designed to be the largest among all four TFTs. T3 and T4 are TFTs for reset. The difference between Figure 12a,b is whether T1′s gate is connected to the drain or not. In the modified bootstrap scan driver, the drain of T1 is not connected to the gate and is connected to Vpulse.  Table 3 shows the parameters extracted from the fabricated a-IGZO TFT. The fieldeffect mobility and on/off ratio were 6.2 cm 2 /V·s and 2.1 × 10 7 , respectively. The subthreshold swing was 1.8 V/dec, and the threshold voltage was −4.8 V. The mobility and threshold voltage were obtained from the saturation current (I ds ) Equation (1):

= ( )
where W and L are channel width and length, respectively. C ox is the capacitance of the gate insulator per unit area and µ FE is a field effect mobility. The subthreshold swing (SS) was obtained according to Equation (2).  Figure 12a,b. Figure 12a shows the bootstrap scan driver, and Figure 12b shows the modified bootstrap scan driver. The circuit area of a unit stage was 620 µm × 290 µm. The design parameters of the scan drivers are indicated in Table 4. In order to ensure driving capability, the size of the drive TFT, T2, was designed to be the largest among all four TFTs. T3 and T4 are TFTs for reset. The difference between Figure 12a,b is whether T1 s gate is connected to the drain or not. In the modified bootstrap scan driver, the drain of T1 is not connected to the gate and is connected to Vpulse.
The measurement results of the bootstrap scan driver and modified bootstrap scan driver are shown in Figure 13 with waveforms of input signals. There were errors in the bootstrap scan driver's output waveform, while the modified bootstrap scan driver showed a good output waveform without errors. The modified bootstrap scan driver eliminated errors by appropriately adjusting the Vpulse signal connected to the drain of T1 and the PS signal connected to the gate of T1.  The measurement results of the bootstrap scan driver and modified bootstrap scan driver are shown in Figure 13 with waveforms of input signals. There were errors in the bootstrap scan driver's output waveform, while the modified bootstrap scan driver showed a good output waveform without errors. The modified bootstrap scan driver eliminated errors by appropriately adjusting the Vpulse signal connected to the drain of T1 and the PS signal connected to the gate of T1.  Figure 14 shows the transfer characteristic, in which the threshold voltage was more negative than in Figure 10. Figure 15 shows the measured output waveform of scan drivers with the TFTs shown in Figure 14. Figure 15a,b shows the output waveforms of the bootstrap scan driver and modified bootstrap scan driver, respectively. The operation frequency was 1 kHz. Since the TFT used was more negatively shifted than the TFT in Figure  10, Figure 15a shows a larger error than Figure 13a. However, as shown in Figure 15b, the modified bootstrap scan driver showed no error.    The measurement results of the bootstrap scan driver and modified bootstrap scan driver are shown in Figure 13 with waveforms of input signals. There were errors in the bootstrap scan driver's output waveform, while the modified bootstrap scan driver showed a good output waveform without errors. The modified bootstrap scan driver eliminated errors by appropriately adjusting the Vpulse signal connected to the drain of T1 and the PS signal connected to the gate of T1.  Figure 14 shows the transfer characteristic, in which the threshold voltage was more negative than in Figure 10. Figure 15 shows the measured output waveform of scan drivers with the TFTs shown in Figure 14. Figure 15a,b shows the output waveforms of the bootstrap scan driver and modified bootstrap scan driver, respectively. The operation frequency was 1 kHz. Since the TFT used was more negatively shifted than the TFT in Figure  10, Figure 15a shows a larger error than Figure 13a. However, as shown in Figure 15b, the modified bootstrap scan driver showed no error.  Figure 14 shows the transfer characteristic, in which the threshold voltage was more negative than in Figure 10. Figure 15 shows the measured output waveform of scan drivers with the TFTs shown in Figure 14. Figure 15a,b shows the output waveforms of the bootstrap scan driver and modified bootstrap scan driver, respectively. The operation frequency was 1 kHz. Since the TFT used was more negatively shifted than the TFT in Figure 10, Figure 15a shows a larger error than Figure 13a. However, as shown in Figure 15b, the modified bootstrap scan driver showed no error.

Conclusions
We proposed a decoder-type a-IGZO scan driver that is suitable for flexible and stretchable displays. Since a-IGZO TFTs often exhibit depletion-mode characteristics that have a negative threshold voltage (Vth), the proposed circuit was designed to operate well for both enhancement and depletion-mode TFTs. The circuits were optimized by a circuit simulation and fabricated by an a-IGZO TFT process. The simulation and measurement showed that the proposed decoder-type scan driver operated well for both the enhancement and depletion-mode TFTs without error. The operation at the threshold voltage of 20 V was verified by the simulation, and the measurement results showed that the proposed circuit provided scan output pulses with depletion-mode TFTs with a large negative threshold voltage of −25 V.   Figure 14: (a) bootstrap scan driver; (b) modified bootstrap scan driver.

Conclusions
We proposed a decoder-type a-IGZO scan driver that is suitable for flexible and stretchable displays. Since a-IGZO TFTs often exhibit depletion-mode characteristics that have a negative threshold voltage (Vth), the proposed circuit was designed to operate well for both enhancement and depletion-mode TFTs. The circuits were optimized by a circuit simulation and fabricated by an a-IGZO TFT process. The simulation and measurement showed that the proposed decoder-type scan driver operated well for both the enhancement and depletion-mode TFTs without error. The operation at the threshold voltage of 20 V was verified by the simulation, and the measurement results showed that the proposed circuit provided scan output pulses with depletion-mode TFTs with a large negative threshold voltage of −25 V.

Conclusions
We proposed a decoder-type a-IGZO scan driver that is suitable for flexible and stretchable displays. Since a-IGZO TFTs often exhibit depletion-mode characteristics that have a negative threshold voltage (Vth), the proposed circuit was designed to operate well for both enhancement and depletion-mode TFTs. The circuits were optimized by a circuit simulation and fabricated by an a-IGZO TFT process. The simulation and measurement showed that the proposed decoder-type scan driver operated well for both the enhancement and depletion-mode TFTs without error. The operation at the threshold voltage of 20 V was verified by the simulation, and the measurement results showed that the proposed circuit provided scan output pulses with depletion-mode TFTs with a large negative threshold voltage of −25 V.