Cascaded-like High-Step-Down Converter with Single Switch and Leakage Energy Recycling in Single-Stage Structure

A cascaded-like high-step-down converter (CHSDC) is proposed in this article, which can steeply convert a high voltage to a much lower level without the utilizing of extreme turns ratio or duty ratio. The proposed converter integrates two buck-boost converters and one forward converter to form a single-stage architecture containing only a single low-side driving switch, which, as a result, can lower the cost and reduce the complexity of the associated control driver. Even in a single-stage single-switch structure, the ability to step down input voltage is as effective as the cascade of two buck-boosts and one forward converter. Meanwhile, the proposed converter can avoid the low efficiency caused by a cascaded structure. Without an additional clamp circuit, the leakage energy stored in the transformer of the CHSDC can be still recycled so as to raise the efficiency of the converter and suppress voltage spikes at the power switch. Converter operation principle and key parameter design are discussed. Moreover, a 200 W prototype is built and then tested to validate the proposed converter and verify the theoretical analysis.


Introduction
Even though electric vehicles (EVs) have to be charged, the power for which comes from fossil-fuel plants, EVs can still reduce carbon dioxide production by 60% as compared with engine-system vehicles. EVs have been challenging the leading position of enginesystem vehicles as a matter of course.
EVs commonly have two built-in DC voltage levels for different kinds of power supply, as shown in Figure 1. The purpose of the high-voltage battery bank is mainly to provide power for motor driving. Meanwhile, the low-voltage lithium-ion battery is for in-car auxiliary appliances such as the panelboard, dashcam, lighting, audio and video systems, air conditioner, automatic seat, and power steering wheel. The low-voltage lithium-ion battery has to be charged from the high-voltage bus. However, the low-voltage battery can alternatively be removed. With this approach, the auxiliary appliances will be powered by the high-voltage bus through a step-down converter with a high conversion ratio. No matter whether a low-voltage lithium-ion battery should be installed in EVs, a high step-down converter to steeply lower bus voltage for powering auxiliary appliances is certainly required.
Conventional step-down converters, such as buck-derived DC/DC converters [1][2][3][4], can theoretically accomplish a high voltage-conversion ratio by operating under an extreme duty cycle. However, at the operating of an extreme duty cycle, significant conduction loss and switching loss, high voltage stresses, influential ripples, low efficiency of the converter, etc., will inevitably drop the performance of this kind of converter a lot. For efficiency improvement, among the buck-derived converters, some of them utilize softswitching mechanisms into the converter design to increase efficiency. Nevertheless, an switching mechanisms into the converter design to increase efficiency. Neverth acceptable efficiency still cannot be obtained under an extreme duty ratio. As con isolated topologies, the bridge-derived configurations can be a choice [5][6][7][8][9]. How order to obtain a huge conversion ratio, a higher turns ratio has to be adopted, w decreases converter efficiency and then narrows the conversion range. Besides, mu tive switches will increase costs, the complexity of the drier, and the interference o ing noise. The structure of a two-/multi-stage converter [10][11][12][13] can be an option for a an expected voltage gain and for a wide voltage-range operation. With the stru multi-stages, the parameter tuning will have higher flexibility to average voltage in each stage, which is one advantage of this kind of converter; however, it still ha drawbacks, such as at least two active switches need to be employed and it disp overall efficiency. Therefore, a cascaded-like converter is developed, which poss characteristics of both a high voltage ratio and wide voltage range, the same as t pleted by a two-stage converter, and only needs a single switch [14][15][16][17][18][19]. Neve their step-down voltage ratios still cannot be as high as for EV applications. Co transformers into cascaded-like converters to further raise the voltage ratio is, t studied [20][21][22][23][24][25], but high voltage spikes caused by the leakage inductance of a tran need to be taken into consideration [21][22][23]. Usually, a snubber circuit or an active cell is necessarily integrated into converter design [24,25], which accordingly incre and circuit complexity.
To step down a high voltage to a much lower level for auxiliary power app in EV systems as well as overcome the aforementioned problems, a cascaded-l step-down converter (CHSDC) is proposed in this paper. As shown in Figu CHSDC integrates two buck-boost converters and one forward converter to be switch single-stage architecture. It can accomplish a step-down voltage ratio as obtained by the three-stage cascade of two buck-boost converters and one forw  The structure of a two-/multi-stage converter [10][11][12][13] can be an option for achieving an expected voltage gain and for a wide voltage-range operation. With the structure of multi-stages, the parameter tuning will have higher flexibility to average voltage stresses in each stage, which is one advantage of this kind of converter; however, it still has several drawbacks, such as at least two active switches need to be employed and it displays low overall efficiency. Therefore, a cascaded-like converter is developed, which possesses the characteristics of both a high voltage ratio and wide voltage range, the same as that completed by a two-stage converter, and only needs a single switch [14][15][16][17][18][19]. Nevertheless, their step-down voltage ratios still cannot be as high as for EV applications. Combining transformers into cascaded-like converters to further raise the voltage ratio is, therefore, studied [20][21][22][23][24][25], but high voltage spikes caused by the leakage inductance of a transformer need to be taken into consideration [21][22][23]. Usually, a snubber circuit or an active clamped cell is necessarily integrated into converter design [24,25], which accordingly increases cost and circuit complexity.
To step down a high voltage to a much lower level for auxiliary power applications in EV systems as well as overcome the aforementioned problems, a cascaded-like high-stepdown converter (CHSDC) is proposed in this paper. As shown in Figure 2, the CHSDC integrates two buck-boost converters and one forward converter to be a single-switch singlestage architecture. It can accomplish a step-down voltage ratio as high as obtained by the three-stage cascade of two buck-boost converters and one forward converter. In addition, the CHSDC intrinsically has the features of leakage energy recycling and galvanic isolation.

Converter Structure and Operation Principle
The main power circuit of the proposed CHSDC is depicted in Figure 3, which is derived from the integration of dual buck-boost converters and a forward converter to construct a single-stage structure with a single switch and galvanic isolation. Even though only one active switch is adopted, the CHSDC is able to step down input voltage as effectively as the cascade type of two buck-boost converters and one forward converter. The cascade of three converters needs three active switches at least, the worst of which belongs to a multi-stage structure, lowering overall efficiency dramatically. Therefore, the CHSDC is much better than the cascade structure.
As shown in Figure 3, it can be observed that the CHSDC incorporates buck-boost 1, buck-boost 2, and a forward, only using a common switch but still possessing a high conversion ratio achieved by a cascaded multi-stage converter. In the main power circuit, the equivalent of the high-frequency transformer includes a turns ratio of N2 to N1, a magnetizing inductance Lm1, two leakage inductances Lk1 and Lk2.  To clearly describe the operation of the CHSDC, the definitions of voltage polarity and current direction are shown in Figure 4. To simplify the analysis, the following assumptions are considered: 1. All the capacitors are large enough so that the voltages across them are regarded as constant and ripple-free; 2. All semiconductor devices and diodes are ideal. That is, parasitic parameters can be neglected; 3. The Lk1 and Lk2 represent the leakage inductances at the primary side and secondary side of the high-frequency transformer, respectively, values of which both are much smaller than the magnetizing inductance Lm1; 4. The duty ratio of the switch SW will be less than 0.5; 5. The turns ratio of the coupled inductor n is equal to ;

Converter Structure and Operation Principle
The main power circuit of the proposed CHSDC is depicted in Figure 3, which is derived from the integration of dual buck-boost converters and a forward converter to construct a single-stage structure with a single switch and galvanic isolation. Even though only one active switch is adopted, the CHSDC is able to step down input voltage as effectively as the cascade type of two buck-boost converters and one forward converter. The cascade of three converters needs three active switches at least, the worst of which belongs to a multi-stage structure, lowering overall efficiency dramatically. Therefore, the CHSDC is much better than the cascade structure.

Converter Structure and Operation Principle
The main power circuit of the proposed CHSDC is depicted in Figure 3, derived from the integration of dual buck-boost converters and a forward con construct a single-stage structure with a single switch and galvanic isolation. Even only one active switch is adopted, the CHSDC is able to step down input voltage tively as the cascade type of two buck-boost converters and one forward conve cascade of three converters needs three active switches at least, the worst of which to a multi-stage structure, lowering overall efficiency dramatically. Therefore, the is much better than the cascade structure.
As shown in Figure 3, it can be observed that the CHSDC incorporates buck buck-boost 2, and a forward, only using a common switch but still possessing a h version ratio achieved by a cascaded multi-stage converter. In the main power cir equivalent of the high-frequency transformer includes a turns ratio of N2 to N1, a izing inductance Lm1, two leakage inductances Lk1 and Lk2.  To clearly describe the operation of the CHSDC, the definitions of voltage and current direction are shown in Figure 4. To simplify the analysis, the follo sumptions are considered: 1. All the capacitors are large enough so that the voltages across them are reg constant and ripple-free; 2. All semiconductor devices and diodes are ideal. That is, parasitic parameter neglected; 3. The Lk1 and Lk2 represent the leakage inductances at the primary side and se side of the high-frequency transformer, respectively, values of which both a smaller than the magnetizing inductance Lm1; 4. The duty ratio of the switch SW will be less than 0.5; 5. The turns ratio of the coupled inductor n is equal to ; As shown in Figure 3, it can be observed that the CHSDC incorporates buck-boost 1, buck-boost 2, and a forward, only using a common switch but still possessing a high conversion ratio achieved by a cascaded multi-stage converter. In the main power circuit, the equivalent of the high-frequency transformer includes a turns ratio of N 2 to N 1 , a magnetizing inductance L m1 , two leakage inductances L k1 and L k2 .
To clearly describe the operation of the CHSDC, the definitions of voltage polarity and current direction are shown in Figure 4. To simplify the analysis, the following assumptions are considered:

1.
All the capacitors are large enough so that the voltages across them are regarded as constant and ripple-free; 2.
All semiconductor devices and diodes are ideal. That is, parasitic parameters can be neglected; 3.
The L k1 and L k2 represent the leakage inductances at the primary side and secondary side of the high-frequency transformer, respectively, values of which both are much smaller than the magnetizing inductance L m1 ; 4.
The duty ratio of the switch SW will be less than 0.5; The operation of the proposed CHSDC at steady-state and in CCM can be divided into five modes over one switching cycle. Figure 5 depicts the conceptual key waveform of this converter, while Figures 6-10 are the equivalents for each mode in turn. In the following, the five operating modes of the converter will be discussed mode by mode. The operation of the proposed CHSDC at steady-state and in CCM can be divided into five modes over one switching cycle. Figure 5 depicts the conceptual key waveforms of this converter, while Figures 6-10 are the equivalents for each mode in turn. In the following, the five operating modes of the converter will be discussed mode by mode.

Mode 1 [t 0~t1 ]:
As shown in Figure 6, Mode 1 begins when the power switch SW is turned on at t 0 . During the time interval of Mode 1, diodes D 2 , D 4 , D 5 , and D 6 are in forwarding bias, but diodes D 1 and D 3 are reversely biased. During this short-time transition, the current of the leakage inductor L k1 , i Lk1 increases linearly. Meanwhile, the current flowing through L k2 , i Lk2 also increases linearly. The energy of inductor L o is delivered to the load and capacitor C o . As the increasing current of i Lk2 is equal to the current of i Lo , the diode D 6 becomes OFF and this mode ends.

Mode 2 [t 1~t2 ]:
Mode 2 lasts from t 1~t2 . The equivalent circuit of Mode 2 is presented in Figure 7, which indicates that the SW, D 2 , D 4 , and D 5 are still conducting and diodes D 1 , D 3 , and D 6 are OFF. Inductor L 1 absorbs energy from the input voltage, and capacitor C 2 charges the inductor L 2 through switch SW and diode D 2 . In addition, capacitor C 1 forwards its stored energy to the low-voltage side through the high-frequency transformer to supply the output. Thus, the leakage-inductance current i Lk1 and magnetizing-inductance current i Lm1 are increasing linearly, as does the output-inductor current i Lo . As the switch SW is turned off, the operation of the converter enters the next mode.

Mode 3 [t 2~t3 ]:
Mode 3 starts at time t = t 2 . Figure 8 is the related equivalent, where switch SW and diode D 2 are in OFF state but diodes D 1 , D 3 , D 4 , D 5 , and D 6 are in ON-state. During this short period, the energy stored in L k1 is recycled to capacitor C 2 and the input voltage through diode D 1 . At the same time, the leakage energy of L k2 is recycled to the capacitor C o via the diode D 5 . In this mode, capacitor C 2 is also charged by the inductor L 1 , and capacitor C 1 is charged by L 2 via diode D 3 . This mode ends when leakage energy in L k2 releases completely at t = t 3 .

Mode 4 [t 3~t4 ]:
After leakage inductance releases all stored energy, diode D 5 becomes OFF and converter operation will be in Mode 4. As illustrated in Figure 9, the switch SW remains OFF and diodes D 2 and D 5 are reversely biased. On the contrary, diodes D 1 , D 3 , D 4, and D 6 are forwarded. Leakage inductance L k2 keeps recycling its energy. In this time interval, the currents i Lk1 and i Lm1 decrease linearly. On the low-voltage side, output inductor L o still supplies for the output as well as capacitor C o . When the leakage-inductance current i Lk1 and magnetizing-inductance current i Lm1 drop to zero at t = t 4 , the next operation mode begins. The operation of the proposed CHSDC at steady-state and in CCM can be divided into five modes over one switching cycle. Figure 5 depicts the conceptual key waveform of this converter, while Figures 6-10 are the equivalents for each mode in turn. In th following, the five operating modes of the converter will be discussed mode by mode.   As shown in Figure 6, Mode 1 begins when the power switch SW is turned on at t0. During the time interval of Mode 1, diodes D2, D4, D5, and D6 are in forwarding bias, but diodes D1 and D3 are reversely biased. During this short-time transition, the current of the leakage inductor Lk1, iLk1 increases linearly. Meanwhile, the current flowing through Lk2, iLk2 also increases linearly. The energy of inductor Lo is delivered to the load and capacitor Co. As the increasing current of iLk2 is equal to the current of iLo, the diode D6 becomes OFF and this mode ends.  Figure 7, which indicates that the SW, D2, D4, and D5 are still conducting and diodes D1, D3, and D6 are OFF. Inductor L1 absorbs energy from the input voltage, and capacitor C2 charges the are OFF. Inductor L1 absorbs energy from the input voltage, and capacitor C2 charges inductor L2 through switch SW and diode D2. In addition, capacitor C1 forwards its sto energy to the low-voltage side through the high-frequency transformer to supply the put. Thus, the leakage-inductance current iLk1 and magnetizing-inductance current iLm increasing linearly, as does the output-inductor current iLo. As the switch SW is turned the operation of the converter enters the next mode.

Mode 3 [t2~t3]:
Mode 3 starts at time t = t2. Figure 8 is the related equivalent, where switch SW diode D2 are in OFF state but diodes D1, D3, D4, D5, and D6 are in ON-state. During short period, the energy stored in Lk1 is recycled to capacitor C2 and the input vol through diode D1. At the same time, the leakage energy of Lk2 is recycled to the capac Co via the diode D5. In this mode, capacitor C2 is also charged by the inductor L1, capacitor C1 is charged by L2 via diode D3. This mode ends when leakage energy in releases completely at t = t3. Electronics 2022, 11, x FOR PEER REVIEW 6

Mode 4 [t3~t4]:
After leakage inductance releases all stored energy, diode D5 becomes OFF and verter operation will be in Mode 4. As illustrated in Figure 9, the switch SW remains and diodes D2 and D5 are reversely biased. On the contrary, diodes D1, D3, D4, and D forwarded. Leakage inductance Lk2 keeps recycling its energy. In this time interval currents iLk1 and iLm1 decrease linearly. On the low-voltage side, output inductor Lo supplies for the output as well as capacitor Co. When the leakage-inductance curren and magnetizing-inductance current iLm1 drop to zero at t = t4, the next operation m begins. As indicated in Figure 10, this equivalent circuit is for Mode 5, the switch SW is in OFF-state, diodes D1, D3, and D6 are in forwarding bias, and diodes D2, D4, and D reverse biased. In this mode, capacitor C2 is charged by inductor L1 through diod Electronics 2022, 11, x FOR PEER REVIEW 6

Mode 4 [t3~t4]:
After leakage inductance releases all stored energy, diode D5 becomes OFF and verter operation will be in Mode 4. As illustrated in Figure 9, the switch SW remains and diodes D2 and D5 are reversely biased. On the contrary, diodes D1, D3, D4, and D forwarded. Leakage inductance Lk2 keeps recycling its energy. In this time interval currents iLk1 and iLm1 decrease linearly. On the low-voltage side, output inductor Lo supplies for the output as well as capacitor Co. When the leakage-inductance curren and magnetizing-inductance current iLm1 drop to zero at t = t4, the next operation m begins.

Mode 5 [t4~t5]:
As indicated in Figure 10, this equivalent circuit is for Mode 5, the switch SW is in OFF-state, diodes D1, D3, and D6 are in forwarding bias, and diodes D2, D4, and D reverse biased. In this mode, capacitor C2 is charged by inductor L1 through diod while inductor L2 charges capacitor C1 via diode D3. The output inductor Lo keeps ene supplying for the load. This mode ends when switch SW is turned on. The complete eration of the converter finishes at t = t5.

Mode 4 [t3~t4]:
After leakage inductance releases all stored energy, diode D5 becomes OFF a verter operation will be in Mode 4. As illustrated in Figure 9, the switch SW rema and diodes D2 and D5 are reversely biased. On the contrary, diodes D1, D3, D4, an forwarded. Leakage inductance Lk2 keeps recycling its energy. In this time inte currents iLk1 and iLm1 decrease linearly. On the low-voltage side, output inducto supplies for the output as well as capacitor Co. When the leakage-inductance cu and magnetizing-inductance current iLm1 drop to zero at t = t4, the next operatio begins.

Mode 5 [t4~t5]:
As indicated in Figure 10, this equivalent circuit is for Mode 5, the switch SW in OFF-state, diodes D1, D3, and D6 are in forwarding bias, and diodes D2, D4, an reverse biased. In this mode, capacitor C2 is charged by inductor L1 through d while inductor L2 charges capacitor C1 via diode D3. The output inductor Lo keeps supplying for the load. This mode ends when switch SW is turned on. The comp eration of the converter finishes at t = t5.   As indicated in Figure 10, this equivalent circuit is for Mode 5, the switch SW is still in OFF-state, diodes D 1 , D 3 , and D 6 are in forwarding bias, and diodes D 2 , D 4 , and D 5 are reverse biased. In this mode, capacitor C 2 is charged by inductor L 1 through diode D 1 , while inductor L 2 charges capacitor C 1 via diode D 3 . The output inductor L o keeps energy-supplying for the load. This mode ends when switch SW is turned on. The complete operation of the converter finishes at t = t 5 .

Voltage Gain
The followings discuss the voltage gain derivation of the converter. The definitions of voltage polarity and the current direction are according to Figure 4. Applying the voltage-second balance principle to output inductor L o yields in which the V Lo,on and V Lo,off are denoted as the voltages across the inductor L o during the intervals of SW ON and OFF, respectively, D stands for the duty ratio of the active switch, and T s is switching period. As indicated in Figure 7, while SW is in ON state, the voltage of inductor L 1 , V L1,on , and the voltage of inductor L 2 , V L2,on , can therefore be found as follows: and Additionally, as the switch is ON, the voltage across inductor L o , V Lo,on , is expressed as When switch SW is OFF, as depicted in Figure 10, the voltages across inductors L 1 , L 2 , and L o are and respectively. By substituting (4) and (7) into (1), the output voltage V o is obtained as While applying the criterion of voltage-second balance to the inductors L 1 and L 2 individually, the capacitor voltages V C1 and V C2 in terms of duty ratio D and input voltage V in can be given as and respectively. Then, substituting (8) into (9), as a result, the converter voltage ratio of output to input is estimated as While the CHSDC is in CCM operation, the relationship of voltage gain versus switch duty cycle D, under different turns ratios of the transformer, is illustrated in Figure 11. It can be observed that the CHSDC is capable of stepping down a high input voltage significantly even under the operating with a regular turns ratio. That is, this converter can avoid employing a high turn-ratio transform. As revealed in Figure 11, the CHSDC achieves a conversion ratio of 0.03 at the conditions that turn ratio is 1:3 and duty cycle is 0.34. That is, based on this conversion ratio, the CHSDC can deal with a 400 V input voltage to power a 12 V load.

Voltage Stresses of Semiconductors
In order to choose a proper power switch and diodes, the determination of voltage stress and current stress for each semiconductor device has to be fulfilled. According to Figure 10, during the period of SW OFF, the blocking voltages of the SW and diodes D2, D4, D5 can be expressed as and (15) in turn. Similarly, according to Figure 7, during the period of SW ON, the blocking voltages of diodes D1, D3, and D6 are, respectively, denoted as follows: and Figure 11. Relationship among voltage gain, duty ratio, and turns ratio.

Voltage Stresses of Semiconductors
In order to choose a proper power switch and diodes, the determination of voltage stress and current stress for each semiconductor device has to be fulfilled. According to Figure 10, during the period of SW OFF, the blocking voltages of the SW and diodes D 2 , D 4 , D 5 can be expressed as and in turn. Similarly, according to Figure 7, during the period of SW ON, the blocking voltages of diodes D 1 , D 3 , and D 6 are, respectively, denoted as follows: and

Current Stresses of Semiconductors
Since the output inductor L o is in series with the output port, the inductor current i Lo will be equal to the output current i o and can be calculated by In (19), R is the load resistance. As referred to Mode 2 and Mode 5, the inductor current i Lo passes through diode D 5 and diode D 6 when SW is ON and OFF, respectively. Therefore, the current stresses of D 5 and D 6 will be identical to each other, which are obtained as For determining the current stresses of the other semiconductor devices, including D 1 , D 2 , D 3 , D 4 , and SW, average currents of L m1 , L 1 , and L 2 along with the capacitor current of C 1 during SW-ON, that is, i Lm1 , avg i L1,avg , i L2,avg , and i C1,on , have to be found in advance. To comprehend the finding, the waveform of i Lm1 is depicted in Figure 12, based on which the current i Lm1,avg can be computed as

Current Stresses of Semiconductors
Since the output inductor Lo is in series with the output por will be equal to the output current io and can be calculated by In (19), R is the load resistance. As referred to Mode 2 and Mode passes through diode D5 and diode D6 when SW is ON and OFF the current stresses of D5 and D6 will be identical to each other, w For determining the current stresses of the other semicond D1, D2, D3, D4, and SW, average currents of Lm1, L1, and L2 along w of C1 during SW-ON, that is, iLm1,avg iL1,avg, iL2,avg, and iC1,on, have to comprehend the finding, the waveform of iLm1 is depicted in Figur current iLm1,avg can be computed as The ΔiLm1 in (21) is equal to Placing ΔiLm1 in (22) into (21) yields Based on Mode 2 and Mode 5, the expresses of iL1,avg, iL2,avg, an as follows: The ∆i Lm1 in (21) is equal to Placing ∆i Lm1 in (22) into (21) yields Based on Mode 2 and Mode 5, the expresses of i L1,avg , i L2,avg , and i C1,on can be figured out as follows: Di Lm1,avg = i in (24) (1 − D)i L1,avg = Di L2,avg (25) and Suppose that the input power will equal output power. That is, Since the voltage gain of the CHSDC has been obtained in (11), the input current of the converter can be Substituting both relationships of (19) and (28) into (24), (25), and (26), individually, the currents of i L1,avg , i L2,avg i C1,on are therefore obtained as and Because the average current flowing through diode D 1 and the inductance current i L1,avg are the same, the following relationship holds: Besides, the average currents of D 2 and D 3 are equal to the inductor current i L2,avg , which leads to Concerning the current stress of D 4 , it can be determined as For active switch SW, Mode 2 is referred and then, its current stress is denoted as Substituting (29), (30), and (31) into (35), the current stress of SW, i SW,avg , is then obtained as:

Inductance Design
To guarantee that the converter operation is in CCM, all the minimum currents of the inductors L o , L 1 , and L 2 , that is, i Lo(min) , i L1(min) , and i L2(min) , are set to be zero and accordingly the following relationships hold: Based on (37)-(39), the required minimum inductances of L o , L 1 , and L 2 , denotes as L o(min) , L 1(min) , and L 2(min) , respectively, to ensure the CHSDC is in CCM are determined as and

Capacitance Design
In the CHSDC, the larger the capacitances are, the smaller the voltage ripples become. In order to suppress voltage ripples within the requirements, estimating for the minimum capacitances should be fulfilled. Voltage variation on a capacitor is given as with (43), the capacitances of C 1 , C 2 , and C o can be derived as: and The equivalent series resistance (ESR) in a capacitor will dissipate power and thus lower converter efficiency. It seems that a much higher capacitance should be designed, however, which raises the cost. Therefore, an appropriate capacitance should compromise with voltage ripples. When building the CHSDC prototype, we consider to the voltage ripples of the capacitors C 1 , C 2 , and C o should be under 1 V, 5 V and 0.1 V, when the capacitance of each capacitors are 47 µF, 4.7 µF and 470 µF. Table 1 summarizes the comparison of the proposed converter with other step-down converters. The performance comparison includes voltage gain, the numbers of semiconductor devices, the numbers of capacitors and magnetic elements, isolation features, and the ability of leakage-energy recycling. Table 1 reveals that the merits of the proposed converter contains: having the mechanism of leakage-energy recycling, a lower number of switches, lower capacitance used, and a better voltage gain. As illustrated in Table 1, even though the proposed CHSDC only requires a single power switch, it can still achieve an excellent step-down competence over all possible range of duty ratios, almost surpassing other similar converters. In addition, the CHSDC has the mechanism of leakage-energy recycling and the feature of galvanic isolation. There are six diodes in the proposed converter, which would imply that, because more diodes are utilized, conversion efficiency would be dropped dramatically. However, among all diodes in the CHSDC, two diodes are located on the low-voltage side. The low-voltage diodes can avoid the converter from consuming too much power. Concerning the number of magnetic elements, since the proposed converter is mainly derived from the integration of two buck-boosts and one forward converter, theoretically, the converter will contain more magnetic components. Nevertheless, from the viewpoint of gaining a higher voltage ratio, it is worthwhile. The designs of the magnetic components are in DCM while operating below two-thirds of the load, which means that lower inductances can be considered. Conduction loss can be accordingly restrained. In addition, leakage energy stored in the transformer of the CHSDC can be recycled. Owing to the inductor design and energy-recycling competence, even though more magnetic components are used, power loss still can be suppressed. Table 1. Performance comparison among the proposed converter and other recently proposed topologies.

Experimental Results
To prove the theoretical derivation, illustrate the performance, and verify the validity of the CHSDC, a 200 W prototype is constructed and then tested. The input voltage of the converter is 400 V and the output voltage is 12 V. The key parameters of the prototype are summarized in Table 2. Figure 13a shows the waveforms of the practical input current and the related control signal, while Figure 13b is the corresponding simulations. Figure 13 reveals that the practical measurements can be consistent with the simulations. In addition, Figure 13 also illustrates that energy stored in leakage inductance can be recycled to the input source and the converter can avoid extreme duty-cycle operation even under the full-load condition. The duty ratio of the switch is close to 0.34, instead of operating in a heavy-duty ratio. Figure 14 is the voltage and current waveforms of the active switch with practical measure and simulation. It reveals that the average current of the switch is about 9.5 A, which is close to the calculation result of 9.91 A with (36). The current stresses of D 1 -D 6 are calculated with (20) and (32)-(34), individually, then to be 1.48 A, 2.87 A, 2.87 A, 5.5 A, 16.6 A, and 16.6 A, respectively, all of which match with the measurement results of i D1 to i D6 in Figure 15. In addition, Figure 15a,g demonstrates that diodes D 1 and D 4 both have the feature of zero-current switching (ZCS) during the turn OFF transition. Experimental and simulated current and voltage waveforms of inductors and the output capacitor are also presented in Figures 16 and 17, respectively. Figure 16b shows the simulated inductor currents i L1 and i L2 , while Figure 16a is their practical measurements. From Figure 16, it can be observed that the inductors L 1 and L 2 are in DCM and CCM, respectively, which have confirmed the theoretical derivation in Section 3.4. Figure 17b is the simulated output voltage v o and output inductor i Lo , practical measurements of which are demonstrated in Figure 17a. As shown in Figure 17, it can be found that the output inductor L o is in CCM, and the output voltage is controlled at a stable level of 12 V with a quite small ripple of less than 1%.         Figure 18 gives the voltage gain of the proposed converter in comparison with the step-down converters in [3,10,14,25]. It shows that the proposed converter is better at stepping down a high input voltage than other similar converters. Figure 19 expresses the power budget of the proposed CHSDC while operating in the full-load situation, in which diode loss accounts for 56% of the total loss. Switch loss accounts for 11%, while inductor loss, transformer loss, and capacitor loss are 15%, 11%, and 7%, respectively. The efficiency of the CHSDC is measured per 20 W from light load to full load. Figure 20 depicts the measured results. From this figure, the highest efficiency is around 93% at 140 W and 91% at the full load. Figure 21 is the photograph of the prototype of CHSDC.   Figure 18 gives the voltage gain of the proposed converter in comparison with the step-down converters in [3,10,14,25]. It shows that the proposed converter is better at stepping down a high input voltage than other similar converters. Figure 19 expresses the power budget of the proposed CHSDC while operating in the full-load situation, in which diode loss accounts for 56% of the total loss. Switch loss accounts for 11%, while inductor loss, transformer loss, and capacitor loss are 15%, 11%, and 7%, respectively. The efficiency of the CHSDC is measured per 20 W from light load to full load. Figure 20 depicts the measured results. From this figure, the highest efficiency is around 93% at 140 W and 91% at the full load. Figure 21 is the photograph of the prototype of CHSDC.  Figure 18 gives the voltage gain of the proposed converter in comparison with the step-down converters in [3,10,14,25]. It shows that the proposed converter is better at stepping down a high input voltage than other similar converters. Figure 19 expresses the power budget of the proposed CHSDC while operating in the full-load situation, in which diode loss accounts for 56% of the total loss. Switch loss accounts for 11%, while inductor loss, transformer loss, and capacitor loss are 15%, 11%, and 7%, respectively. The efficiency of the CHSDC is measured per 20 W from light load to full load. Figure 20 depicts the measured results. From this figure, the highest efficiency is around 93% at 140 W and 91% at the full load. Figure 21 is the photograph of the prototype of CHSDC.

Conclusions
In this article, a high step-down converter is proposed, which is able to accomplish an excellent voltage conversion ratio, avoiding the adopting of high turns ratio and extreme switch cycle. That is, the proposed converter can step down a high input voltage to a much lower level under a regular switch cycle and turns ratio. In the power stage, the CHSDC integrates two buck-boost circuits and one forward circuit to be a single-stage single-switch structure to achieve an excellent voltage conversion ratio which is the same as the effect obtained by the cascade of the three converters. Because only one switch is needed, the complexity of driving circuit design is reduced significantly. The leakage energy stored in the transformer can be recycled for improving the conversion efficiency of the converter and suppressing voltage spikes on the power switch as well. Furthermore, diodes D 1 and D 4 possess ZCS-off features. The operation principle, steady-state analysis, and parameter design of the converter in CCM have been explored. Finally, the correctness of the theoretical analysis and the feasibility of the converter are verified through the measurements from a 200 W prototype.