Research on Topology Recognition Technology Based on Intelligent Measurement Switches

: Distribution network topology identiﬁcation provides information on low-voltage station areas in a power system. However, it requires either heavy computation or additional measuring equipment. This paper proposes topology identiﬁcation technology based on intelligent measurement switches. The topology is identiﬁed by using the characteristic current measured by the designed intelligent measurement switch. The modulation/demodulation method and information encoding method for the topology identiﬁcation are presented. The communication protocol stack structure and message encapsulation format of the topology identiﬁcation unit are designed. The experimental veriﬁcation and analysis show that the topology identiﬁcation technology proposed in this paper has a short identiﬁcation time and an identiﬁcation accuracy of 100%, and it can be widely promoted and applied in low-voltage distribution networks.


Introduction
As the State Grid Corporation's investment in the construction of smart grids continues to increase, the construction of smart grids has achieved remarkable results. The functions of smart grids, such as monitoring power quality [1,2], photovoltaic power generation consumption [3,4], line loss management and anti-theft purposes [5,6], are widely used. However, because the topology of the current system is inconsistent with the actual topology, the accuracy of its results are greatly reduced. In a low-voltage distribution network, the lack or inaccuracy of network topology information is a problem worthy of attention. Accurate user-side phases and topological connection relations are of great significance to the operation and maintenance management of a distribution network. Usually, a power company records and manages the network connection information of various power distribution equipment and assets in the enterprise geographic information system. However, a considerable number of enterprise Geographic Information Systems (GISs) only cover medium-voltage distribution networks, and there is little information about low-voltage distribution networks. Due to the extensive coverage of distribution networks, there are rapid changes in power supply and a lack of working resources and effective technical means to establish a low-voltage network topology downstream of the distribution transformer, coupled with frequent line upgrades and an increase in new customers. There is no topology record of low-voltage distribution networks in most domestic power companies' GISs. Manual online investigations are time-consuming and laborious, and there is no automatic system change after a topology change. Y. Li et al. [7] proposed a new method for topology identification based on the inner desynchronization of a Hindmarsh-Rose neural network. Through this method, the original neural network can achieve internal desynchronization, and topology observers can successfully identify unknown topologies. Y. CHEN et al. [8] proposed a novel two-stage method to identify the connection relationship between distribution transformers and feeders. The proposed two-stage method can help operators correct topology errors. Y. Shen et al. [9] proposed a directed network topology inference method based on joint diagonalization (JD), developed three JD algorithms tailored for network topology inference and demonstrated them using simulation and real data tests. S. Li et al. [10] obtained effective results by fully mining the potentially effective information of the distribution network's big data and by applying it to the identification of the distribution network topology. In order to improve the success rate and efficiency of the automatic identification of low-voltage power distribution topology, C. Xu et al. [11] proposed a record-based topology identification method. This topology identification method has the advantages of simple control logic, fast identification speed and high identification accuracy. Y. Chen et al. [12] proposed a design technique for the topology generation of chapless radio frequency identification (RFID) tags and proposed a topology identification design method that does not require an iterative optimization process. Y. Liu et al. [13] proposed a distribution network topology error identification method based on distribution phasor measurement units (D-PMU) and branch state functions. This method uses telemetry and remote signaling information to identify a single topology error and multiple topology errors in a distribution network. In order to solve the task of blind topology identification, Z. Xiang et al. [14] proposed a topology identification method based on dictionary learning, which improves the accuracy of topology identification. In order to meet the calculation speed requirements of real-time network topology analysis, W. Deng et al. [15] proposed a two-layer calculation method that uses the K-nearest neighbor algorithm for rough judgment and mutual information for precise calculation, which shortens the running time and improves the calculation speed.
Current research mainly focuses on network topology identification and blind topology identification. Waarde et al. [16] studied topology identification for a more general class of so-called heterogeneous networks, in which the dynamics of the nodes were modeled by general (possibly distinct) linear systems. Farajollahi et al. [17] presented a new topology identification algorithm based on measurements from a few line current sensors, together with available pseudo-measurements for nodal power injections. Wang et al. [18] presented topology identification in two-layer complex dynamical networks. Coutino et al. [19] presented state-space network topology identification from partial observations. Zhao et al. [20] presented full-scale distribution system topology identification using a Markov random field. Cavraro et al. [21] presented bus clustering for distribution grid topology identification in a smart grid. It can be seen that research on the identification of the connection relationship between distribution transformers and feeders, as well as topology identification based on the distribution network's big data, has been carried out. Most topology identification methods require either heavy computation or additional measuring equipment.
An intelligent measurement switch is a popular protection device with the function of measuring power in a system. It has current protection functions (overload long delay protection, short circuit short delay protection and short circuit transient protection), voltage protection (over-and under-voltage protection, phase failure protection and frequency protection) and temperature protection functions. It also can also measure node voltage, current, power and frequency. Intelligent measurement switches are installed at all levels of a low-voltage distribution network, and nodes are completely distributed, which is convenient for the complete identification of the topology of the entire station area. Thus, distribution network topology identification based on intelligent measurement switches has the inherent advantage of a low cost. However, research on topology identification technology based on intelligent measurement switches has not yet carried out. This paper presents topology identification technology based on intelligent measurement switches. Firstly, a modulation/demodulation method and an information encoding method for the topology identification are presented. Then, the communication protocol's stack structure and the message encapsulation format of the topology identification unit are designed. Finally, a new type of intelligent measurement switch with the function of topology identification Electronics 2022, 11, 3903 3 of 16 is designed. In the proposed method, the distribution network's topology is identified by using the characteristic current measured with the designed intelligent measurement switch. Experiments validate the effectiveness of the proposed method.

Topology Identification Technology Solution
As mentioned in the Introduction, distribution network topology identification requires either heavy computation or additional measuring equipment. Intelligent measurement switches are installed at all levels of a low-voltage distribution network, and they can be potential devices for topology identification with the advantage of a low cost. This paper presents topology identification technology based on intelligent measurement switches. In the new designed intelligent measurement switch, the control circuit with the topology identification function is mainly composed of the main control unit module, power supply module, metering module, communication module, clock module, topology identification current generation module, etc. The schematic diagram of the control circuit is shown in Figure 1. The intelligent measurement switch developed based on this scheme can accurately identify the physical topology of the low-voltage distribution station area and can realize the online generation of the self-portrait structure diagram of the station area by using this system. encoding method for the topology identification are presented. Then, the communica protocol's stack structure and the message encapsulation format of the topol identification unit are designed. Finally, a new type of intelligent measurement sw with the function of topology identification is designed. In the proposed method, distribution network's topology is identified by using the characteristic current measu with the designed intelligent measurement switch. Experiments validate the effective of the proposed method.

Topology Identification Technology Solution
As mentioned in the Introduction, distribution network topology identifica requires either heavy computation or additional measuring equipment. Intellig measurement switches are installed at all levels of a low-voltage distribution netw and they can be potential devices for topology identification with the advantage of a cost. This paper presents topology identification technology based on intelli measurement switches. In the new designed intelligent measurement switch, the con circuit with the topology identification function is mainly composed of the main con unit module, power supply module, metering module, communication module, c module, topology identification current generation module, etc. The schematic diag of the control circuit is shown in Figure 1. The intelligent measurement switch develo based on this scheme can accurately identify the physical topology of the low-vol distribution station area and can realize the online generation of the self-portrait struc diagram of the station area by using this system. The main control unit module is used for the online processing of metering data of topology identification commands collected by the smart measurement sw receiving accurate time synchronization tasks set by the terminal and accurately tim the clock module of the smart measurement switch every day to ensure time consiste The time deviation is less than 9 s. The main control unit module receives the t distribution, sends instruction, sends interval settings, etc., through the communica module, and it sorts and analyzes the collected time stamps to obtain the real phys topology. The main control unit module uses DMA for raw data storage. It reads the in the DMA, and if it is greater than the critical value and is in the monitoring pulse si state, the device sending this state is considered to be at the front end of the receiv module. The main control module is a circuit composed of a controller chip whose m is STM32F103RCT6.
The topology identification current generation module is used to generate the cur encoding signal that can be recognized by other intelligent measurement switches in The main control unit module is used for the online processing of metering data and of topology identification commands collected by the smart measurement switch, receiving accurate time synchronization tasks set by the terminal and accurately timing the clock module of the smart measurement switch every day to ensure time consistency. The time deviation is less than 9 s. The main control unit module receives the time distribution, sends instruction, sends interval settings, etc., through the communication module, and it sorts and analyzes the collected time stamps to obtain the real physical topology. The main control unit module uses DMA for raw data storage. It reads the data in the DMA, and if it is greater than the critical value and is in the monitoring pulse signal state, the device sending this state is considered to be at the front end of the receiving module. The main control module is a circuit composed of a controller chip whose model is STM32F103RCT6.
The topology identification current generation module is used to generate the current encoding signal that can be recognized by other intelligent measurement switches in the same branch, and it performs voltage zero crossing detection (rising). After detecting the voltage zero crossing (fixed delay 2 ms), it waits for 7 ms and turns on the IO port corresponding to the main control unit module, carrying out a high current pulse injec-tion. After zero crossing, it automatically shuts down and completes a short-time current pulse injection.
The metering module is used to collect the metering data of the smart measurement switch and to complete the accurate identification of the topology identification current. The metering module collects the topology identification current signal sent by the topology identification module of other smart measurement switches for data analysis. In the lowvoltage station area, the network topology from the transformer to the branch box, from the branch box to the meter box and from the meter box to the household meter is automatically drawn, and the data are transmitted to the terminal, which are displayed in the form of an illustration. The metering module receives the topology identification command of the main control unit module, enters the signal monitoring state, receives and parses the current signal from other intelligent measurement switch topology identification generation modules in real time, determines its location and can also use the communication module to obtain the resulting feedback to the terminal.
The power supply module is used to supply power to the intelligent measurement switch. The power supply module includes a rectifier circuit and a voltage-stabilizing circuit. The rectifier circuit and the voltage-stabilizing circuit are connected in a series. The rectifier circuit is used to convert the AC power input from the power grid into DC power. The voltage-stabilizing circuit is used to convert DC power into stable DC power and supply power. The voltage-stabilizing circuit includes a 5 V power supply circuit and a 3.3 V power supply circuit. The 5 V power supply circuit is used to convert the DC power into a stable 5 V power supply voltage and supply power, and the 3.3 V power supply circuit is used to convert the 5 V power supply into a 3.3 V power supply and supply power.
The communication module is used for remote communication between the intelligent measurement switch and the upstream device. The clock module is used to realize accurate clock data for the intelligent measurement switch, and the clock module is a circuit composed of a clock chip of model RX8025T.

Topology Identification Mechanism Based on the Characteristic Current
The characteristic electric current sending procedure is shown in Figure 2. The main control unit module issues a characteristic current signal sending instruction to the topology identification current generation module, and the topology identification current generation module controls the on and off states of the characteristic load to generate a characteristic current signal on the power line after receiving the instruction.
command of the main control unit module, enters the signal monitoring state, r and parses the current signal from other intelligent measurement switch to identification generation modules in real time, determines its location and can a the communication module to obtain the resulting feedback to the terminal.
The power supply module is used to supply power to the intelligent measu switch. The power supply module includes a rectifier circuit and a voltage-sta circuit. The rectifier circuit and the voltage-stabilizing circuit are connected in a ser rectifier circuit is used to convert the AC power input from the power grid into DC The voltage-stabilizing circuit is used to convert DC power into stable DC pow supply power. The voltage-stabilizing circuit includes a 5 V power supply circu 3.3 V power supply circuit. The 5 V power supply circuit is used to convert the DC into a stable 5 V power supply voltage and supply power, and the 3.3 V power circuit is used to convert the 5 V power supply into a 3.3 V power supply and power.
The communication module is used for remote communication betwe intelligent measurement switch and the upstream device. The clock module is realize accurate clock data for the intelligent measurement switch, and the clock is a circuit composed of a clock chip of model RX8025T.

Topology Identification Mechanism Based on the Characteristic Current
The characteristic electric current sending procedure is shown in Figure 2. Th control unit module issues a characteristic current signal sending instruction topology identification current generation module, and the topology identi current generation module controls the on and off states of the characteristic generate a characteristic current signal on the power line after receiving the instru The current characteristics of topological identification are shown in Figure  switching frequency can be set, with the default being 833.3 Hz, and both high-le low-level pulse widths can be set. The characteristic current's carried information set, the start symbol is AAH = 10101010C, the control code is E9H = 11101001C length of the subsequent extended domain information is variable. Among them the code bit is 0, there is no characteristic current transmission, and when the cod 1, there is a characteristic current transmission. The length of each bit code's sendi can be set, and the default is 600 ms ± 15 ms.  The current characteristics of topological identification are shown in Figure 3. The switching frequency can be set, with the default being 833.3 Hz, and both high-level and low-level pulse widths can be set. The characteristic current's carried information can be set, the start symbol is AAH = 10101010C, the control code is E9H = 11101001C and the length of the subsequent extended domain information is variable. Among them, when the code bit is 0, there is no characteristic current transmission, and when the code bit is 1, there is a characteristic current transmission. The length of each bit code's sending time can be set, and the default is 600 ms ± 15 ms.

Modulation and Demodulation Process
The sending device forms a characteristic current signal and feeds it to the power line through a predetermined modulation method. The identification device CT detects the characteristic current signal, performs corresponding demodulation processing, finally restores the characteristic current signal on the power line to decode data information and makes a logical judgment. The modulation and demodulation process are shown in Figure  4.

Modulation and Demodulation Process
Bulleted lists can be described as follows. Through OOK modulation, the presence or absence of a characteristic current with a fixed bit width is used to represent the '1' and '0' of the digital signal. The modulation carrier frequency 1 f is the switching frequency for sending the characteristic signal. The original information is modulated, and the signal is Among them, A represents the characteristic current amplitude, and DUTY represents the duty cycle of the characteristic signal. The modulation process is shown in Figure 5. For the modulation carrier frequency, the duration of each bit is the set bit width

Modulation and Demodulation Process
The sending device forms a characteristic current signal and feeds it to the power line through a predetermined modulation method. The identification device CT detects the characteristic current signal, performs corresponding demodulation processing, finally restores the characteristic current signal on the power line to decode data information and makes a logical judgment. The modulation and demodulation process are shown in Figure 4.

Modulation and Demodulation Process
The sending device forms a characteristic current signal and feeds it to the power line through a predetermined modulation method. The identification device CT detects the characteristic current signal, performs corresponding demodulation processing, finally restores the characteristic current signal on the power line to decode data information and makes a logical judgment. The modulation and demodulation process are shown in Figure  4.

Modulation
Analog front end Data input

Modulation and Demodulation Process
Bulleted lists can be described as follows. Through OOK modulation, the presence or absence of a characteristic current with a fixed bit width is used to represent the '1' and '0' of the digital signal. The modulation carrier frequency 1 f is the switching frequency for sending the characteristic signal. The original information is modulated, and the signal is Among them, A represents the characteristic current amplitude, and DUTY represents the duty cycle of the characteristic signal. The modulation process is shown in Figure 5. For the modulation carrier frequency, the duration of each bit is the set bit width

Modulation and Demodulation Process
Bulleted lists can be described as follows. Through OOK modulation, the presence or absence of a characteristic current with a fixed bit width is used to represent the '1' and '0' of the digital signal. The modulation carrier frequency f 1 is the switching frequency for sending the characteristic signal. The original information is modulated, and the signal is m(t).
Among them, A represents the characteristic current amplitude, and DUTY represents the duty cycle of the characteristic signal. The modulation process is shown in Figure 5. For the modulation carrier frequency, the duration of each bit is the set bit width time. If the bit is 1, the frequency is used for switching within the bit duration; if the bit is 0, no switching is performed. time. If the bit is 1, the frequency is used for switching within the 0, no switching is performed.

Topology Identification Program Flow
The topology identification process is shown in Figure 7. An example of modulation implementation is shown in Figure 6. The modulation carrier frequency defaults to 833.3 Hz, and the duration of each bit is 0.6 s. If the bit is 1, a frequency of 833.3 Hz is used for switching during the duration of the bit; if the bit is 0, switching is not performed. An example of modulation implementation is shown in Figure 6. The modulation carrier frequency defaults to 833.3 Hz, and the duration of each bit is 0.6 s. If the bit is 1, a frequency of 833.3 Hz is used for switching during the duration of the bit; if the bit is 0, switching is not performed.

Topology Identification Program Flow
The topology identification process is shown in Figure 7. After the initialization procedure, the power-consuming terminal sends the 'clear topology data' instruction to all switches. After the topology data are cleared, it sends the 'send topology signal' instruction to the i-th switch and waits for 30 s. The i switch sends a signal, and the related switch recognizes the signal. The power-consuming terminal sends the 'query topology data' command to all switches, and the related switches return topology signals. Then, it sends the 'send topology signal' command to the i + 1th switch until the polling of all the switches to which it belongs is completed. It then analyzes the inquired topology data and forms a topology relationship diagram.

Topology Identification Program Flow
The topology identification process is shown in Figure 7. After the initialization procedure, the power-consuming terminal sends the 'clear topology data' instruction to all switches. After the topology data are cleared, it sends the 'send topology signal' instruction to the i-th switch and waits for 30 s. The i switch sends a signal, and the related switch recognizes the signal. The power-consuming terminal sends the 'query topology data' command to all switches, and the related switches return topology signals. Then, it sends the 'send topology signal' command to the i + 1th switch until the polling of all the switches to which it belongs is completed. It then analyzes the inquired topology data and forms a topology relationship diagram.  Figure 7. Topology identification process. Table 1 shows the definition of the coding mode of the topology identification unit. The data frame format is composed of six parts: the data synchronization header, start bit, data bit, insert bit, parity bit and end bit. Among them, the data synchronization header is a 6-bit '1', which means that there is no current time of more than 360 ms; the start bit is a 1-bit '0'. The data bit includes a feature code and a check code, and the feature code consists of 24 bits. The code has 16 bits, with 1 insert bit being inserted every 4 bits, and the insert bit is opposite to the previous data bit. The check bit is 10 bits in total, with 1 insert bit being inserted every 4 bits, and the insert bit is opposite to the previous data bit. The end bit is 1, which consists of the bit '0'.

Project
Coding Method Definition Data frame format Data sync header + start bit + data bit + insert bit + parity bit + end bit Data sync header 6 digits '1' (i.e., no current time lasting for more than 360 ms) Start bit 1 bit '0' Data Signature A total of 24 bits, with 1 insertion bit inserted every 4 bits. A total of 30 bits; the inserted bit is opposite to the previous data bit.

Check code
A total of 16 bits, with an insertion bit inserted every 4 bits. A total of 20 bits; the inserted bit is opposite to the previous data bit. Check (message authentication code) A total of 8 bits, with 1 insert bit inserted every 4 bits. A total of 10 bits; the inserted bit is opposite to the previous data bit.  Table 1 shows the definition of the coding mode of the topology identification unit. The data frame format is composed of six parts: the data synchronization header, start bit, data bit, insert bit, parity bit and end bit. Among them, the data synchronization header is a 6-bit '1', which means that there is no current time of more than 360 ms; the start bit is a 1-bit '0'. The data bit includes a feature code and a check code, and the feature code consists of 24 bits. The code has 16 bits, with 1 insert bit being inserted every 4 bits, and the insert bit is opposite to the previous data bit. The check bit is 10 bits in total, with 1 insert bit being inserted every 4 bits, and the insert bit is opposite to the previous data bit. The end bit is 1, which consists of the bit '0'.

Communication Protocol Stack Structure
The communication network protocol stack of the topology identification unit is shown in Figure 8. The communication protocol stack has a three-layer structure, which mainly includes a physical layer, a data link layer and an application layer. End bit 1-bit '0'

Communication Protocol Stack Structure
The communication network protocol stack of the topology identification unit is shown in Figure 8. The communication protocol stack has a three-layer structure, which mainly includes a physical layer, a data link layer and an application layer.  When the business data are transmitted, they need to be encapsulated according to Figure 9, and they are finally transmitted through the power line. The data message received by the physical layer through the power line is encapsulated in the process of submitting it to the application layer. The actual data length transmitted on the physical layer is 68-bit, and the maximum length of the physical layer decoding unit is 76-bit. The transmission data can then be decoded all at once. The message authentication code adopts CRC8 check, and the polynomial that is used is X8 + X2 + X + 1.

Design of the Power Supply
The principle for the power supply module is shown in Figure 10. The 5 V power supply circuit mainly adopts an LM78L05-type power supply chip, and the 3.3 V power When the business data are transmitted, they need to be encapsulated according to Figure 9, and they are finally transmitted through the power line. The data message received by the physical layer through the power line is encapsulated in the process of submitting it to the application layer. End bit 1-bit '0'

Communication Protocol Stack Structure
The communication network protocol stack of the topology identification unit is shown in Figure 8. The communication protocol stack has a three-layer structure, which mainly includes a physical layer, a data link layer and an application layer.  When the business data are transmitted, they need to be encapsulated according to Figure 9, and they are finally transmitted through the power line. The data message received by the physical layer through the power line is encapsulated in the process of submitting it to the application layer. The actual data length transmitted on the physical layer is 68-bit, and the maximum length of the physical layer decoding unit is 76-bit. The transmission data can then be decoded all at once. The message authentication code adopts CRC8 check, and the polynomial that is used is X8 + X2 + X + 1.

Design of the Power Supply
The principle for the power supply module is shown in Figure 10. The 5 V power supply circuit mainly adopts an LM78L05-type power supply chip, and the 3.3 V power The actual data length transmitted on the physical layer is 68-bit, and the maximum length of the physical layer decoding unit is 76-bit. The transmission data can then be decoded all at once. The message authentication code adopts CRC8 check, and the polynomial that is used is X8 + X2 + X + 1.

Design of the Power Supply
The principle for the power supply module is shown in Figure 10. The 5 V power supply circuit mainly adopts an LM78L05-type power supply chip, and the 3.3 V power supply circuit mainly adopts an HT7533-1-type power supply chip. After rectification, the power VCC is filtered by capacitors C2 and C3. It inputs to the VR1 chip, and the VR1 chip outputs +5 V of power. The +5 V power supply is filtered through the grounding of capacitors C4 and C5 and through D1 voltage regulator protection, and then it inputs to the VR2 power chip, which outputs +3.3 V of power that is filtered by capacitors C6 and C7.
Electronics 2022, 11, 3903 9 o supply circuit mainly adopts an HT7533-1-type power supply chip. After rectification power VCC is filtered by capacitors C2 and C3. It inputs to the VR1 chip, and the V chip outputs +5 V of power. The +5 V power supply is filtered through the groundin capacitors C4 and C5 and through D1 voltage regulator protection, and then it input the VR2 power chip, which outputs +3.3 V of power that is filtered by capacitors C6 C7.

Design of Current Sampling
The principle of current sampling and CT power extraction is shown in Figure  The current sampling circuit is used to accurately sample the line current. The exte input current signal of the secondary side of the three-way current transforme converted into a voltage signal by the sampling resistor, rectified by the rectifier bri (D12, D13 and D14), which is then filtered by the respective RC circuits (R37, R39 and as a group; R41, R44 and C30 as a group; and R47, R50 and C31 as a group). Then, amplified by the op-amp constituted by the voltage conversion signal, which is samp and uploaded to the main control unit.
The CT pickup circuit is used to provide DC power for the control section (includ the main control module, communication module, etc.) in combination with the po supply module when the voltage pickup is abnormal. The current is charged by a half-wave rectifier for electrolytic capacitor C34, which is used as the energy stor element for CT power take-off at 1-VCC. Voltage regulator diode D18 plays the rol protecting the line from over-voltage. U10 is a voltage regulator triode, which can ou a high-precision 2.495 V voltage to stabilize the Vinb-pin of U9 at 2.495 V. U9 acts voltage comparator when the Vinb+ voltage is greater than Vinb-, the open high-l output Q4 transistor, so the current flows directly to GND, no longer charging capacitor. Therefore, 1-VCC voltage can output a stable voltage of 2.495 × (1 + 100 K/3 = 10.06 V.

Design of Functions and Interfaces
The major function of an intelligent measurement switch can be summarized follows.

Design of Current Sampling
The principle of current sampling and CT power extraction is shown in Figure 11. The current sampling circuit is used to accurately sample the line current. The external input current signal of the secondary side of the three-way current transformer is converted into a voltage signal by the sampling resistor, rectified by the rectifier bridge (D12, D13 and D14), which is then filtered by the respective RC circuits (R37, R39 and C29 as a group; R41, R44 and C30 as a group; and R47, R50 and C31 as a group). Then, it is amplified by the op-amp constituted by the voltage conversion signal, which is sampled and uploaded to the main control unit.  The main technical parameters of the circuit breaker branch identification modul are shown in Table 2. The interface-labelling diagram of HPLC topology module for th measurement switch is shown in Figure 12. The main interface's definition and description of the HPLC topology module for the designed intelligent measuremen switch are listed in Table 3.  The CT pickup circuit is used to provide DC power for the control section (including the main control module, communication module, etc.) in combination with the power supply module when the voltage pickup is abnormal. The current is charged by a D16 halfwave rectifier for electrolytic capacitor C34, which is used as the energy storage element for CT power take-off at 1-VCC. Voltage regulator diode D18 plays the role of protecting the line from over-voltage. U10 is a voltage regulator triode, which can output a high-precision 2.495 V voltage to stabilize the Vinb-pin of U9 at 2.495 V. U9 acts as a voltage comparator when the Vinb+ voltage is greater than Vinb-, the open high-level output Q4 transistor, so the current flows directly to GND, no longer charging the capacitor. Therefore, 1-VCC voltage can output a stable voltage of 2.495 × (1 + 100 K/33 K) = 10.06 V.

Design of Functions and Interfaces
The major function of an intelligent measurement switch can be summarized as follows. The amount of signal information for storage is not less than 2000 while supporting the reading of historical records, and stored information is not lost when power is lost.
The main technical parameters of the circuit breaker branch identification module are shown in Table 2. The interface-labelling diagram of HPLC topology module for the measurement switch is shown in Figure 12. The main interface's definition and a description of the HPLC topology module for the designed intelligent measurement switch are listed in Table 3. Add a 100 Ω resistor to the whole board Temperature rise ≤55 °C Figure 12. Interface labeling diagram of HPLC topology module for measurement switch.

Experiment and Effect Analysis
To verify the proposed topology identification technology and the designed intelligent measurement switch (IMS), we selected nine measurement switches with the topology identification function in the network, whose numbers are as follows: 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 and 9 . In addition, we built the experimental platform in the laboratory environment, as shown in Figure 13. The topology data table obtained through the topology identification process is shown in Table 4. Table 4. Topology Data Sheet.

Experiment and Effect Analysis
To verify the proposed topology identification technology and the designed intelligent measurement switch (IMS), we selected nine measurement switches with the topology identification function in the network, whose numbers are as follows: ①, ②, ③ , ④ , ⑤, ⑥ , ⑦, ⑧ and ⑨. In addition, we built the experimental platform in the laboratory environment, as shown in Figure 13. The topology data table obtained through the topology identification process is shown in Table 4.  Figure 13. Topology test platform (IMS1 represents intelligent measurement switch ①).    Table 5.          By utilizing the principle by which the switch itself and its superior switch can detect a topological signal, a topological structure was obtained with the proposed technique, as shown in Figure 17. The terminal sends out identification signals sequentially through the communication module. Taking switch ④ as an example, the terminal requires switch ④ to generate a pulse current signal. Switches ⑥, ① and ⑤ can detect the pulse current signal and inform the terminal, and the terminal is able to determine that switches ⑥, ① and ⑤ are the upper nodes of switch ④. When switch ⑥ sends out the pulse current signal, and switches ① and ⑤ can detect the pulse current signal and inform the terminal. The terminal is able to determine that switches ① and ⑤ are the upper nodes of switch ⑥. When switch ① sends out the pulse current signal, only switch ⑤ can detect the pulse current signal, and the terminal is able to judge that switch ⑤ is the upper node of switch ①. The terminal thinks that the hierarchy of the topology is ④→⑥ →①→⑤→Smart terminal.

Switches That Recognize Topological Signals Level
During the experiment, the overall topology identification time was 96 s, and the topology identification accuracy rate was 100%. The results are good because the undertest topology, as shown in Figure 17, is not very complex. Because the under-test topology was built in the laboratory, the number of branches and devices (smart meters) was limited. It should be noticed that, in most practical applications, the accuracy is below 100% because the practical topology is more complex than that of the test. Table 6 shows the topology identification results from using the distribution network [10], the topology signal exchange information [11] and our method. From Table 6, it can be seen that all three adapted methods can achieve topology identification with 100% accuracy. It should be noticed that the proposed method requires the smallest overhead time.  The terminal sends out identification signals sequentially through the communication module. Taking switch 4 as an example, the terminal requires switch 4 to generate a pulse current signal. Switches 6 , 1 and 5 can detect the pulse current signal and inform the terminal, and the terminal is able to determine that switches 6 , 1 and 5 are the upper nodes of switch 4 . When switch 6 sends out the pulse current signal, and switches 1 and 5 can detect the pulse current signal and inform the terminal. The terminal is able to determine that switches 1 and 5 are the upper nodes of switch 6 . When switch 1 sends out the pulse current signal, only switch 5 can detect the pulse current signal, and the terminal is able to judge that switch 5 is the upper node of switch 1 . The terminal thinks that the hierarchy of the topology is 4 → 6 → 1 → 5 →Smart terminal.
During the experiment, the overall topology identification time was 96 s, and the topology identification accuracy rate was 100%. The results are good because the under-test topology, as shown in Figure 17, is not very complex. Because the under-test topology was built in the laboratory, the number of branches and devices (smart meters) was limited. It should be noticed that, in most practical applications, the accuracy is below 100% because the practical topology is more complex than that of the test. Table 6 shows the topology identification results from using the distribution network [10], the topology signal exchange information [11] and our method. From Table 6, it can be seen that all three adapted methods can achieve topology identification with 100% accuracy. It should be noticed that the proposed method requires the smallest overhead time. The experimental results show that, in the test environment, the topology structure diagram and the topology data table formed by the technology in this paper are accurate and reliable, and the topology identification time is short. It can clearly show the relationship between switches at all levels, and it provides a technical approach in order to accurately locate the fault point and identify the fault type.

Conclusions
In view of the defects of existing technology, such as low availability and inconsistencies between a system's topology and the actual topology, this paper proposes a technical solution for topology identification based on intelligent measurement switches, and the topology identification mechanism based on the characteristic current is built. The modulation and demodulation process and the modulation method are designed. The design is clear, and the current characteristics and key parameters of the topology identification are clarified. A complete topology identification process is proposed, the information encoding method and data frame format are given and the communication network protocol's stack structure as well as the message encapsulation format of the topology identification unit are designed. Experimental verification and analysis show that the technical solution proposed in this paper has a short topology identification time, low power consumption and an identification accuracy of 100%. It can effectively solve the defects of existing technology and can be widely promoted and applied in low-voltage distribution networks, so the prospect is very broad.  Data Availability Statement: Since the study did not report any data, the authors chose to exclude this statement.

Conflicts of Interest:
The authors declare no conflict of interest.