Analysis of DC-Side Snubbers for SiC Devices Application

: Due to parasitic parameters existing in Silicon Carbide (SiC) devices application, SiC devices have poor turn-off performances. SiC diode and SiC MOSFET have severe turn-off overvoltage and oscillation. The DC-side snubber is one simple suppressing method. The simplest circuit is the high-frequency decoupling capacitor in parallel with the bridge leg. However, choosing the component value is empirical. Based on the turn-off terminal impedances of the SiC diode and the SiC MOSFET, the suppressing mechanism of this DC-side snubber is analyzed. The guideline selection for the component value is provided. Furthermore, the DC-side snubber with a damping resistor is analyzed based on the terminal impedances. The design principles are provided. Finally, the validity and effectiveness of the DC-side snubbers were proven based on the double-pulse test platform.


Introduction
In recent years, Silicon Carbide (SiC) devices have emerged as a kind of promising candidates for high-performance power conversion [1,2]. Compared with state-of-theart silicon devices, they are featured with higher switching speeds and lower switching loss [3,4]. Therefore, the switching frequency of the power electronic equipment with SiC devices has been continuously pushed up to reduce the size of passive components, which realizes the high-power density [5,6]. However, due to parasitic parameters existing in SiC devices application, SiC devices have poor turn-off performances [7]. SiC diode and SiC MOSFET will have severe turn-off overvoltage and oscillation [8,9]. To avoid damaging the devices, the voltage rating must be enough, which will increase the system cost [10][11][12].
The turn-off terminal impedance is used to analyze the mechanism of the turn-off voltage and oscillation of the SiC MOSFET [13,14]. The parasitic capacitors of the SiC MOSFET and the loop parasitic inductors resonate, which amplifies the component of the excitation source and results in the turn-off overvoltage and oscillation [15,16]. The turn-off terminal impedance analysis method can be performed to provide the suppressing guidelines.
The suppressing methods for the turn-off overvoltage and oscillation on devices can be classified into two categories. One method is to reduce the switching speed of devices, which can be implemented by increasing the gate resistor. However, poor switching performances will be attained, including the switching delay time and the switching loss [17,18]. Another method is to add snubbers to the circuit. One type of snubber is connected directly to the devices, such as the R¬-C snubber [19,20] and the R-C-D snubber [21,22]. By these device snubbers, the turn-off overvoltage can be decreased, but the turn-on overcurrent and the loss can be increased. Furthermore, the suppressing effectiveness can be weakened by the added parasitic inductors owning to device snubbers. Therefore, device snubbers are used less in high-speed SiC devices application. Another type of snubber is the DC-side snubber, which is one simple suppressing method. The simplest circuit is the high-frequency decoupling capacitor in parallel with the bridge leg [23]. By DC-side snubbers, a portion of parasitic inductors can be decoupled from the switching power loop. However, choosing the component value is empirical. Moreover, the suppressing effectiveness is not good when the bulk of the decoupling capacitor leads

Suppressing Mechanism of DC-Side Snubber C DE
In a phase-leg configuration, such as boost, buck-boost, half-bridge, and full-bridge, the active switch makes current communication with the freewheeling diode during the turn-on and turn-off transition of the active switch. The basic cell is shown in Figure 1, with one branch being the output current, I o , one branch being the freewheeling diode, and one branch being the active switch, which was chosen to study. The input voltage source, V DC , is constant. The output current, I o , is constant. C DC is the DC bulk capacitor. C DE is the DC-side snubber capacitor. The switch, Q, is driven by the double pulse signal. The switching of Q causes current commutation with the external circuit and the diode, D. However, the parasitic elements existing in the circuit need to be considered due to the high-speed switching SiC MOSFET. The parasitic elements in Figure 1 are the gate-source capacitance (C GS ), the gate-drain capacitance (C GD ), the drain-source capacitance (C DS ), the gate inductance (L G ), the drain inductance (L D ), the source inductance (L S ) of the Q and the junction capacitance (C F ), the cathode inductance (L C1 ), and the anode inductance (L A1 ) of the diode (D). A SiC diode is employed as the freewheeling diode, which does not have the reverse recovery charge (Q rr ) and has a low voltage drop. L bus1 , L bus2 , L bus1 , and L bus2 represent the interconnection parasitic inductors of the PCB traces. L CS are the common source inductances shared by the switching power loop and the gate drive loop. R G represents the external gate drive resistance. v P is the gate signal for the SiC MOSFET.
The turn-on switching transition of the SiC MOSFET can be divided into four stages [26], which are the Turn-on Delay Time (Stage 1:

Analysis of Stage 4
At t 4 , the voltage of the SiC diode, v F , reaches the input voltage, V DC . Then the turn-off overvoltage and oscillation on the SiC diode occurs. In this stage, the SiC MOSFET is equivalent to the on-state resistor (R DS_on ). Figure 3a shows the equivalent circuit at this stage, in which L P is the sum of L C , L A , L D , L CS , L bus1 , and L bus2 . L bus is the sum of L bus1 and L bus2 . The parasitic capacitors of the SiC MOSFET are neglected because the SiC MOSFET is in the on-state. The terminal impedance Z d_1 is calculated as Equation (1), as the following, where N d_1 (s) and D d_1 (s) are shown in Appendix A. The amplitude-frequency curves of the terminal impedance Z d_1 are shown in Figure 4a, based on the parameters in Table 1. To be consistent with the experimental verification in Section 4, parameters of the SiC MOSFET C2M0080120D and the SiC diode C4D20120A were used. Based on Figure 4a, there are two resonant peaks existing on the terminal impedance Z d_1 . The resonant frequencies are expressed as Equations (2) and (3), where f d_1_1 represents the high-resonance frequency of the terminal impedance Z d_1 , and f d_1_2 represents the low-resonance frequency of the terminal impedance Z d_1 . The peak resonant impedances of the terminal impedance Z d_1 amplify the excitation source at the resonant frequencies and result in two oscillations overlaying on the turn-off voltage of the SiC diode.

Analysis of Stage 7 and Stage 8
At t 7 , the SiC diode and the SiC MOSFET make a current commutation, and the turn-off overvoltage of the SiC MOSFET occurs. At t 8 , the current commutation comes to an end, and the oscillation on the turn-off voltage of the SiC MOSFET occurs. Figure 3b shows the equivalent circuit at these two stages. The capacitor of the SiC diode is neglected because the SiC diode is in the on-state. The terminal impedance Z m2_1 is calculated as Equation (4), where N m2_1 (s) and D m2_1 (s) are shown in Appendix A. The amplitude-frequency curves of the terminal impedance, Z m2_1 , are based on the parameters in Table 1, as shown in Figure 4b. In Figure 4b, there are two resonant peaks existing on the terminal impedance Z m2_1 , which is the same as the terminal impedance Z d_1 . The resonant frequencies are expressed as Equations (2) and (3), where f m2_1_1 represents the high-resonance frequency of the terminal impedance Z m2_1 and f m2_1_2 represents the low-resonance frequency of the terminal impedance Z m2_1 , and C oss = C GD + C DS . The peak resonant impedances of the terminal impedance Z m2_1 amplify the excitation source at the resonant frequencies and result in two oscillations overlaying on the turn-off voltage of the SiC MOSFET.

Guideline Selection for Capacitor C DE
To realize the decouple of the inductor L bus from the switching power loop and make inductor L bus and parasitic capacitors C F , C GD , and C DS no resonance, capacitor C DE must be much larger than the parasitic capacitors C F , C GD , and C DS according to Equations (1)- (6). In addition, the impedance Z L_1 of the paralleling branches L bus and C DE at the high-resonance frequency f d1_1_1 and the high-resonance frequency f m2_1_1 should be much lower than the impedance of inductor L P . In general, the capacitor C DE satisfies the inequality in Equation (7). It is considered that capacitor C DE is large enough than parasitic capacitors C F , C GD , and C DS .
The impedance Z L_1 of the paralleling branches L bus and C DE can be expressed as Equation (8). In addition, Equation (9) should be satisfied and simplified as Equation (10).
In Figure 4, capacitor C DE is set to none, 0.1 nF, 1 nF, 10 nF, 100 nF, and 1000 nF, respectively. When capacitor C DE is larger than 10nF, the peak impedances on the terminal impedances, Z d_1 and Z m2_1 , are obviously smaller than without the capacitor C DE . In addition, the high-resonance frequencies are scarcely affected by capacitor C DE . However, the low-frequency resonances are still affected by the capacitor C DE . Based on Equations (3) and (6), the low-frequency resonances are caused by the capacitor C DE and inductor L bus . The voltage fluctuation, ∆v CDE , on capacitor C DE can be calculated as Equation (12). Assuming that the limitation of the voltage fluctuation is ∆V CDE , capacitor C DE also needs to satisfy Equation (13).
In summary, the DC-side snubber C DE needs to satisfy Equation (14), and the decoupling of the parasitic inductor L bus and the suppression for the low-frequency oscillation on the turn-off voltage can be realized.

Analyzation for the Suppressing Effectiveness of Capacitor C DE
Assume the peak impedances, Z d_1_H_P and Z m2_1_H_P , of the SiC diode and SiC MOSFET with the capacitor C DE are 1/ρ times the peak impedances, Z d_H_P and Z m2_H_P , without the capacitor C DE . Equations (15)-(18) express the peak impedances without and with the capacitor C DE .
Therefore, Equation (19) can be derived based on the relations between the peak impedances Z d_H_P , Z m2_H_P and Z d_1_H_P , Z m2_1_H_P . Figure 5 presents the amplitude-frequency curves of terminal impedances, Z d_1 and Z m2_1 , with different n values based on parameters in Table 1. Inductors L bus and L P are set to 50 nH, 150 nH or 100 nH, 100 nH, respectively, which means n = 3 or n = 1. Based on Figure 5, the larger n is, the smaller L P is, which represents that the capacitor C DE is closer to the devices, the lower the peak impedance is. Compared to without C DE , the peak impedance of terminal impedances, Z d_1 and Z m2_1 , with C DE is reduced nearly n/(n + 1) times.

Analyzation for DC-Side Snubber with Damping Resistor C DE -R DE
When the DC-side snubber C DE cannot be selected large enough to avoid the lowfrequency oscillation on the turn-off voltage, the suppressing effectiveness is not good owning to the bigger capacitor with parasitic inductors added to the switching power loop. The DC-side snubber with a damping resistor can be used to solve this problem, which is the high-frequency decoupling capacitor in series with a damping resistor. Figure 6 shows the equivalent circuits with this DC-side snubber. Capacitor C DE is to decouple the parasitic inductor L bus , and resistor R DE is to dampen the low-frequency oscillation on the turn-off voltage. If capacitor C DE satisfies Equation (7) and Equation (11) and realizes the decoupling of the inductor L bus from the switching power loop, the low-frequency resonance is only caused by the capacitor C DE and inductor L bus . The impedance Z L_2 of the paralleling branches L bus and C DE -R DE can be calculated as Equation (20), Due to the damping resistor R DE that is in series with capacitor C DE , the impedance Z L_2 at the high-resonance frequency f d1_1_1 and the high-resonance frequency f m2_1_1 should be much lower than the impedance of inductor L P . The relations can be expressed as Equation (21), Assuming that C DE = m 1 C F and C DE = m 2 C oss , Equation (21) can be simplified as where R DE1 = ((1 − nm 1 ) 2 − n 2 )/((n 2 − 1)(n + 1)m 1 )) 1/2 ((L bus + L P )/C DE ) 1/2 and R DE2 = (((1 − nm 2 ) 2 − n 2 )/((n 2 − 1)(n + 1) m 2 )) 1/2 ((L bus + L P )/C DE ) 1/2 . To reduce the scale of the damping resistor R DE , Equation (22) can be simplified as, Due to its discriminant of Equation (20), the low-frequency resonances on the terminal impedances, Z d_1 and Z m2_1 , of the SiC diode and SiC MOSFET can be cancelled completely when the damping resistor R DE satisfies Equation (24).
where R DE3 = 2(n/(n + 1)) 1/2 ((L bus + L P )/C DE ) 1/2 . According to Equations (23) and (24), Figure 7 shows the range of the damping resistor R DE . The larger n is, the smaller the range of the damping resistor R DE is. According to Figure 7, the terminal impedances, Z d_2 and Z m2_2 , of the SiC diode and SiC MOSFET can be calculated as Equations (25) and (26), where N d_2 (s), D d_2 (s), N m2_2 (s), and D m2_2 (s) are shown in Appendix A. The amplitudefrequency curves of Z d_2 and Z m2_2 , based on Table 1, are shown in Figure 8. From Figure 8, the low-frequency peak impedances of Z d_2 and Z m2_2 are eliminated, which indicates this DC-side snubber can effectively suppress the low-frequency oscillation on turn-off voltage. In addition, if resistor R DE satisfies its range requirement, the high-resonance frequency of the terminal impedance, Z d_2 and Z m2_2 , is scarcely affected, and the high-frequency peak impedances are reduced. It is indicated that inductor L bus can be decoupled from the switching power loop, and resistor R DE has suppressing effectiveness on the turn-off overvoltage.

Experimental Results
To verify the suppressing effectiveness of DC-side snubbers, experiments using the 1200V SiC MOSFET C2M0080120D and the SiC diode C4D20120A by Cree Inc. are marked based on the double-pulse-test circuit. Figure 9 presents the testing platform, and Table 2 shows the test equipment used in the platform.   Figure 10 shows the experimental waveforms without and with capacitor C DE , in which capacitor C DE is the multilayer ceramic capacitor and C DE = 100 nF. In Figure 10a,b, the turn-off voltage of the SiC diode is presented. In Figure 10c,d, the turn-off voltage of the SiC MOSFET is presented. Compared to results in Figure 10a,c, without capacitor C DE , the turn-off overvoltage of the SiC diode and SiC MOSFET reduces obviously in Figure 10b,d. However, it is shown that the low-frequency oscillation overlays the highfrequency oscillation on the turn-off voltage of the SiC diode and SiC MOSFET.  Figure 11 shows the experimental waveforms with capacitor C DE and resistor R DE , in which C DE = 100 nF and R DE = 2.5 Ω or R DE = 5 Ω. In Figure 11a,b, the turn-off voltage of the SiC diode is presented. In Figure 11c,d, the turn-off voltage of the SiC MOSFET is presented. Compared to the results in Figure 10b Figure 12, although the higher I o , higher V DC , and lower R G make the turn-off overvoltage higher, DC-side snubbers have effective suppression on the turn-off overvoltage of the SiC diode and SiC MOSFET. Moreover, the DC-side snubber with the damping resistor C DE -R DE is the most effective. Figure 13 presents the effect of DC-side snubbers on the switching losses of the SiC MOSFET at different I o and V DC . Figure 13 employs the switching losses of the SiC MOSFET without the snubber as a reference quantity and transforms the switching losses with DC-side snubbers into per-unit. The turn-on loss of the SiC MOSFET with DC-side snubbers increases, and the turn-off loss of the SiC MOSFET decrease, because a portion of parasitic inductors is decoupled from the power switching loop. Figure 14 presents the efficiency of a 1.1kW buck converter with DC-side snubbers. The tested conditions of the buck converter are presented in Table 3, and the efficiency is tested under open-loop control. From Figure 14, it is observed that the efficiency of the buck converter with C DE = 100 nF, R DE = 2.5 Ω is a little lower than with C DE = 100 nF, which is owning to the loss of R DE .

Conclusions
This paper designs effective DC-side snubbers to suppress the turn-off overvoltage and oscillation for SiC devices application. By the turn-off terminal impedances of the SiC diode and SiC MOSFET, the suppressing mechanisms and design principles of DC-side snubbers are investigated. Based on the above analysis and experimental results, the following conclusions can be drawn: (1) According to the guideline design for DC-side snubbers, the turn-off overvoltage and oscillation of the SiC diode and the SiC MOSFET can be suppressed effectively. (2) Capacitor C DE is closer to devices, which represents the parasitic inductors in the switching power loop are lower, which means the lower the peak impedance is and the lower the turn-off overvoltage is.

Conflicts of Interest:
The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; or in the decision to publish the results.

Appendix A
In Equation (1), N d_1 (s) and D d_1 (s) are as the following, N d_1 (s) = C DE L bus L P s 3 + C DE L bus R DS_on s 2 + L P s + R DS_on (A1) D d_1 (s) = C DE C F L bus L P s 4 + C DE C F L bus R DS_on s 3 + (C DE L bus + C F L P )s 2 + C F R DS_on s + 1 (A2) In Equation (4), N m2_1 (s) and D m2_1 (s) are as the following, N m2_1 (s) = s C DE C GD L bus L P R G s 3 + C DE L bus L P s 2 + C GD R G L P s + L P (A3) D m2_1 (s) = C DE C DS C GD L bus L P R G s 5 + C DE C oss L bus L P s 4 + C GD R G (C DE L bus + C DS L P )s 3 + (C DE L bus + C oss L P )s 2 + C GD R G s + 1 (A4) In Equation (25), N d_2 (s) and D d_2 (s) are as the following, N d_2 (s) = C DE L bus L P s 3 + (C DE L bus R DE + C DE L bus R DS_on + C DE L P R DE )s 2 + (L P + C DE R DE R DS_on )s + R DS_on (A5) D d_2 (s) = C DE C F L bus L P s 4 + (C DE C F L bus R DS_on + C DE C F L P R DE )s 3 + (C DE L bus + C F L P + C DE C F R DE R DS_on )s 2 + (C DE R DE + C F R DS_on )s + 1 (A6) In Equation (26), N m2_2 (s) and D m2_2 (s) are as the following, N m2_2 (s) = C DE C GD L bus L P R G s 4 + (C DE L bus L P + C DE C GD L P R DE R G )s 3 + (C DE L bus R DE + C GD L bus R G + C DE L P R DE + C GD L P R G )s 2 + L P s (A7) D m2_2 (s) = C DE C DS C GD L bus L P R G s 5 + (C DE C oss L bus L P + C DE C DS C GD L P R DE R G )s 4 + (C GD C oss L bus R G + C DE C oss L P R DE + C DS C GD L P R G )s 3 + (C DE L bus + C oss L P + C DE C GD R DE R G )s 2 + (C DE R DE + C GD R G )s + 1 (A8)