More Enhanced Swing Colpitts Oscillators : A Circuit Analysis

: In this paper, we show that an additional inductor–capacitor–inductor ﬁlter can increase the oscillation amplitude of the enhanced swing Colpitts oscillator (ESCO), and call this topology the more enhanced swing Colpitts oscillator (mESCO). When it is connected with a rectiﬁer, the DC–DC boost conversion ratio can be increased, especially for low-voltage sensor ICs or energy harvesting. This paper focuses on the electrical characteristics of mESCO. The oscillation frequency was modeled as a function of the circuit parameters of mESCO. The common gate voltage gain ( A CG ), deﬁned by the ratio of the drain voltage amplitude to the source voltage amplitude of the switching MOSFET of mESCO, was also modeled under the assumption that all the circuit elements are ideal. The model was validated with a SPICE simulation. For A CG < 1.5, the model was in good agreement with the SPICE results within 10%. In addition, the drain voltage amplitude v da was modeled by assuming that the average transconductance of the MOSFET in a half cycle is null when the long-channel Shockley model is used. v da needs to be sufﬁciently high to have a large DC–DC boost conversion ratio. The model can predict the tendency that v da increases as A CG approaches unity. We found that the voltage difference of the drain voltage amplitude to the source voltage amplitude is a constant even when the circuit parameters, and thereby A CG are varied.


Introduction
Battery-free IoT sensor modules are required to eliminate battery replacement to reduce costs. Wireless power transfer (WPT) charges the modules with electromagnetic waves [1][2][3][4]. An energy transducer (ET) transforms environmental energy such as lights, heat flow, and vibration into electric power [5,6]. Those techniques can remove the batteries out of the modules. Circuit designs have improved the power efficiency of power converters even with low power received via WPT and ET. Multisine WPT can increase the peak power with the same average transmitter power, resulting in improvement in power efficiency [7][8][9]. Figure 1 graphically explains how it works. Each of the N multisine waves has power of 1/N to attain the same power as the conventional continuous wave. At the receiving antenna, the peak voltage amplitude can be theoretically increased by a factor of √ N with beating multisine waves when the input impedance is common for N multisine waves with different frequencies. Due to the nonlinearity of the rectifying diode, the multisine waves can output more averaged current than the continuous wave. The Colpitts oscillator is one of the oscillator circuit topologies that provides a carrier frequency for wireless communication [10][11][12][13]. The phase noise of the oscillator is a critical factor limiting the sensitivity of wireless communication. It is important to increase the output voltage amplitude of the oscillator to reduce the phase noise. In order to increase the voltage amplitude, an enhanced swing Colpitts oscillator (ESCO) was proposed [14][15][16][17][18]. What about adding beating to the ESCO to further increase the output voltage amplitude in DC-DC boost converter applications for low-voltage sensor ICs or energy harvesting? In this paper, we show that an additional inductor-capacitor-inductor filter can increase the oscillation amplitude of the ESCO, and call this topology the more enhanced swing Colpitts oscillator (mESCO). Rectifiers were connected with the output terminals of ESCO all the circuit elements are ideal. The drain voltage amplitude vda was also modeled by assuming that an averaged transconductance of the MOSFET in a half cycle is null when the long-channel Shockley model is used. vda needs to be sufficiently high to have a large DC-DC boost conversion ratio. The model can predict the tendency that vda increases as ACG approaches unity. We also found that the voltage difference of the drain voltage amplitude to the source voltage amplitude is a constant even when the circuit parameters, and thereby ACG, are varied. The paper is organized as follows: Section 2 proposes the mESCO and mER. The performance of mER is compared with that of ER. Section 3 analyzes the oscillation frequency, common gate voltage gain, and drain voltage amplitude of mESCO. The models are validated with SPICE simulation. The conclusion is given in Section 4.

More Enhanced Swing Colpitts Oscillator (mESCO), and DC-DC Converter with mESCO and Rectifier (mER)
Let us consider on-chip DC-DC boost converters composed of an oscillator whose peak output voltage is higher than the input DC voltage VIN and a rectifier to supply power to building blocks in sensor/RF IC, as shown in Figure 2. When the decoupling capacitor CDEC is too large to stabilize the input power rails, the oscillator runs with the DC supply voltage, as shown in Figure 2a. On the other hand, if CDEC is set to a relatively small value, the AC component adds to the DC supply voltage to create beat tones into the oscillator, as shown in Figure 2b. The rest of the paper discusses a circuit analysis of the mESCO. The oscillation frequency is shown as a function of the circuit parameters of mESCO. The common gate voltage gain A CG , defined by the ratio of the drain voltage amplitude to the source voltage amplitude of the switching MOSFET of mESCO, was modeled under the assumption that all the circuit elements are ideal. The drain voltage amplitude v da was also modeled by assuming that an averaged transconductance of the MOSFET in a half cycle is null when the long-channel Shockley model is used. v da needs to be sufficiently high to have a large DC-DC boost conversion ratio. The model can predict the tendency that v da increases as A CG approaches unity. We also found that the voltage difference of the drain voltage amplitude to the source voltage amplitude is a constant even when the circuit parameters, and thereby A CG, are varied. The paper is organized as follows: Section 2 proposes the mESCO and mER. The performance of mER is compared with that of ER. Section 3 analyzes the oscillation frequency, common gate voltage gain, and drain voltage amplitude of mESCO. The models are validated with SPICE simulation. The conclusion is given in Section 4.

More Enhanced Swing Colpitts Oscillator (mESCO), and DC-DC Converter with mESCO and Rectifier (mER)
Let us consider on-chip DC-DC boost converters composed of an oscillator whose peak output voltage is higher than the input DC voltage V IN and a rectifier to supply power to building blocks in sensor/RF IC, as shown in Figure 2. When the decoupling capacitor C DEC is too large to stabilize the input power rails, the oscillator runs with the DC supply voltage, as shown in Figure 2a. On the other hand, if C DEC is set to a relatively small value, the AC component adds to the DC supply voltage to create beat tones into the oscillator, as shown in Figure 2b.  Figure 3a illustrates a boost converter (ER) with an enhanced swing Colpitts oscillator (ESCO) followed by a rectifier to drive the load RL. The drain voltage of M1 exceeds VIN. M2 transfers the current when the peak drain voltage of M1 is higher than the target voltage VOUT. To increase the VSS of the ESCO, a small decoupling capacitor is connected  M2 transfers the current when the peak drain voltage of M1 is higher than the target voltage V OUT . To increase the V SS of the ESCO, a small decoupling capacitor is connected between the V IN and V SS through the parasitic inductance of bonding wires, as shown in Figure 3b. Additional oscillation at V SS increases the drain voltage of M1, resulting in a higher output current at the same V OUT as ER.  illustrates a boost converter (ER) with an enhanced swing Colpitts oscillator (ESCO) followed by a rectifier to drive the load RL. The drain voltage of M1 exceeds VIN. M2 transfers the current when the peak drain voltage of M1 is higher than the target voltage VOUT. To increase the VSS of the ESCO, a small decoupling capacitor is connected between the VIN and VSS through the parasitic inductance of bonding wires, as shown in Figure 3b. Additional oscillation at VSS increases the drain voltage of M1, resulting in a higher output current at the same VOUT as ER.  Figure 4a shows the waveform of VD and VS of ER and mER when the outputs are open. The highest peak voltages of VD were 1.08 V with ER and 2.01 V with mER. In mER, the peak voltages were alternately high and low. Figure 4b shows the VOUT vs. IOUT of ER and mER. In addition to an increase in the maximum attainable output voltage, mER can have a larger output current at any operating output voltage than ER. In Section 3, a circuit analysis for mESCO is conducted. A SPICE simulation was run with V IN = 0.3 V, L BW = 2 nH, C DEC = 25 pF, L 1 = 0.239 nH, L 2 = 2.93 nH, C 1 = 4 pF, and C 2 = 1.5 pF. The parameters L 1 , L 2 , C 1 , and C 2 are common to both circuits. The SPICE model in 65 nm CMOS was used in this study. Figure 4a shows the waveform of V D and V S of ER and mER when the outputs are open. The highest peak voltages of V D were 1.08 V with ER and 2.01 V with mER. In mER, the peak voltages were alternately high and low. Figure 4b shows the V OUT vs. I OUT of ER and mER. In addition to an increase in the maximum attainable output voltage, mER can have a larger output current at any operating output voltage than ER. In Section 3, a circuit analysis for mESCO is conducted.

Circuit Analysis of mESCO
Let us define the notation of voltages in this work, as shown in Figure 5. The DC offset and voltage amplitude are described by VX and vxa, respectively. The voltage differences from the ground and DC offset are described by Vx and vx as a function of phase θ, respectively.

Circuit Analysis of mESCO
Let us define the notation of voltages in this work, as shown in Figure 5. The DC offset and voltage amplitude are described by V X and v xa , respectively. The voltage differences from the ground and DC offset are described by V x and v x as a function of phase θ, respectively.

Circuit Analysis of mESCO
Let us define the notation of voltages in this work, as shown in Figure 5. The DC offset and voltage amplitude are described by VX and vxa, respectively. The voltage differences from the ground and DC offset are described by Vx and vx as a function of phase θ, respectively.

Oscillation Frequency
The oscillation frequency of ESCO was modeled in [16] by ignoring any real part of impedance and conductance, assuming the ESCO operates in steady state. We can similarly formulate the oscillation frequency of mESCO. Figure 6 shows the circuit reduction of mESCO from Figure 6a through Figure 6g. A small-signal equivalent circuit of Figure  6a is reduced to Figure 6b. Introducing Ltb for the series connection of Lt and Lb with Ltb = Lt + Lb, and eliminating M1 results in Figure 6c under the assumption that any real part of impedance and conductance is omitted for a simple model. When the impedances of the parallel connections of Ltb and CIN and of L2 and C2 are capacitive, they can be replaced with single capacitors Ceq1 and Ceq2, respectively, by using the formula shown in Figure 6d, where ω is the angular velocity of a signal of interest. Likewise, when the impedance of the series connection of L1 and C1 is inductive, we can replace it with a single inductor Leq, by using the formula shown in Figure 6e. Thus, the circuit shown in Figure 6c is reduced to Figure 6f using Leq, Ceq1 and Ceq2. Finally, we can obtain an LC circuit as shown in Figure  6g, where Ceq = Ceq1 + Ceq2. Thus, (1)-(4) hold for mESCO.

Oscillation Frequency
The oscillation frequency of ESCO was modeled in [16] by ignoring any real part of impedance and conductance, assuming the ESCO operates in steady state. We can similarly formulate the oscillation frequency of mESCO. Figure 6 shows the circuit reduction of mESCO from Figure 6a through Figure 6g. A small-signal equivalent circuit of Figure 6a is reduced to Figure 6b. Introducing L tb for the series connection of L t and L b with L tb = L t + L b , and eliminating M 1 results in Figure 6c under the assumption that any real part of impedance and conductance is omitted for a simple model. When the impedances of the parallel connections of L tb and C IN and of L 2 and C 2 are capacitive, they can be replaced with single capacitors C eq1 and C eq2 , respectively, by using the formula shown in Figure 6d, where ω is the angular velocity of a signal of interest. Likewise, when the impedance of the series connection of L 1 and C 1 is inductive, we can replace it with a single inductor L eq , by using the formula shown in Figure 6e. Thus, the circuit shown in Figure 6c is reduced to Figure 6f using L eq , C eq1 and C eq2 . Finally, we can obtain an LC circuit as shown in Figure 6g, where C eq = C eq1 + C eq2 . Thus, (1)-(4) hold for mESCO.  (2) Electronics 2022, 11, 2808 5 of 12 A fundamental frequency is given by the solution in cubic Equation (5) in terms of f 2 , and thereby can be resolved with three different values. To validate the models proposed in Section 3 with SPICE simulation, the nominal condition shown in Table 1 was used. The values of the inductors and capacitors were much larger than the ones fabricated in a single chip because the SPICE model in 180 nm CMOS was used for M 1 . For parameter response on electrical characteristics, the remaining ones except for the sweeping parameter were set as shown in Table 1. Table 1. Nominal condition to validate the models proposed in Section 3 with SPICE simulation.

Parameter
Default Value The numerical solutions under wide ranges of circuit parameters were in good agreement with the SPICE results within 10% at most, as shown in Figure 7. Among the three solutions, the highest one was selected because the other two frequencies are too low to have L eq and C eq positive values.
Electronics 2022, 11, x FOR PEER REVIEW 6 of 13 Table 1. Nominal condition to validate the models proposed in Section 3 with SPICE simulation.

Parameter Default Value
The numerical solutions under wide ranges of circuit parameters were in good agreement with the SPICE results within 10% at most, as shown in Figure 7. Among the three solutions, the highest one was selected because the other two frequencies are too low to have Leq and Ceq positive values.

Common-Gate Voltage Gain
For DC-DC boost converters to have large boost ratios, a large voltage amplitude at the drain of M1 is required. Let us determine a common gate voltage gain ACG as a function of the circuit parameters first. As performed for modeling the operation frequency of mESCO, a circuit transformation was produced from an original circuit diagram of mESCO as shown in Figure 8a to its small-signal equivalent circuit as shown in Figure 8b,

Common-Gate Voltage Gain
For DC-DC boost converters to have large boost ratios, a large voltage amplitude at the drain of M1 is required. Let us determine a common gate voltage gain A CG as a function of the circuit parameters first. As performed for modeling the operation frequency of mESCO, a circuit transformation was produced from an original circuit diagram of mESCO as shown in Figure 8a to its small-signal equivalent circuit as shown in Figure 8b, and then a circuit model of mESCO as shown in Figure 8c.
Therefore, an equation can relate any two variables. After some calculations, (12) was derived for the common gate voltage gain ACG. With (13)-(18), (12) provides a value for ACG when the circuit parameters are given.
where Ceq2 is given by (2). β, LX, and CX, defined by (16), (17), and (18), respectively, were used to calculate TSQ1-3. Figure 9 shows ACG as a function of each design parameter. The tendencies of ACG vs. L1 (a) and C1 (b) are matched with those for ESCO [16]. As expected, the smaller the CIN, the closer to unity for ACG in (c). (This tendency validated increasing the drain voltage amplitude with a smaller CIN in the following sub-section, as expected in Section 1). There were substantial discrepancies in ACG between the model and SPICE results for CIN > 2 nF. A physical background is required here, but its investigation will be When v d is forced, what voltage appears at v s ? Seven variables (four voltages and three currents) among six equations were applied, as shown by (6)- (11).
Therefore, an equation can relate any two variables. After some calculations, (12) was derived for the common gate voltage gain A CG . With (13)-(18), (12) provides a value for A CG when the circuit parameters are given.
where C eq2 is given by (2). β, L X , and C X , defined by (16), (17), and (18), respectively, were used to calculate T SQ1-3 . Figure 9 shows A CG as a function of each design parameter. The tendencies of A CG vs. L 1 (a) and C 1 (b) are matched with those for ESCO [16]. As expected, the smaller the C IN , the closer to unity for A CG in (c). (This tendency validated increasing the drain voltage amplitude with a smaller C IN in the following sub-section, as expected in Section 1). There were substantial discrepancies in A CG between the model and SPICE results for C IN > 2 nF. A physical background is required here, but its investigation will be conducted in future work. Figure 9d suggests that Lt and Lb can be minor contributors to A CG , resulting in no significant impact on the drain voltage amplitude, as discussed in the following subsection. In summary, the model calculation results were in good agreement with the SPICE results, except for C IN > 2 nF.

Drain Voltage Amplitude vda
In this subsection, the drain voltage amplitude vda is modeled. In reality, there was a distortion in Vd and Vs due to the nonlinear behavior of the transconductance and drain conductance of M1, but it was assumed for simplicity in this study that the AC components of Vd and Vs are modeled with sinusoidal waveforms whose amplitudes are vda and vsa, respectively, as shown in Figure 10. When vsa is large enough, M1 operates in three different modes, i.e., in cut-off, satu-

Drain Voltage Amplitude v da
In this subsection, the drain voltage amplitude v da is modeled. In reality, there was a distortion in V d and V s due to the nonlinear behavior of the transconductance and drain conductance of M1, but it was assumed for simplicity in this study that the AC components of V d and V s are modeled with sinusoidal waveforms whose amplitudes are v da and v sa , respectively, as shown in Figure 10.

Drain Voltage Amplitude vda
In this subsection, the drain voltage amplitude vda is modeled. In reality, there was a distortion in Vd and Vs due to the nonlinear behavior of the transconductance and drain conductance of M1, but it was assumed for simplicity in this study that the AC components of Vd and Vs are modeled with sinusoidal waveforms whose amplitudes are vda and vsa, respectively, as shown in Figure 10. Vd has an offset voltage of VIN. Thus, Vd and Vs can be written as (19) and (20), respectively.
When vsa is large enough, M1 operates in three different modes, i.e., in cut-off, satu- When v sa is large enough, M1 operates in three different modes, i.e., in cut-off, saturation, and linear operation modes. θ 1 is the boundary between cut-off and saturation, resulting in (21), where V TH is the threshold voltage of M1. θ 2 is the boundary between saturation and linear, resulting in (22).
Let us assume a simple Shockley model for M1, as described in (23) and (24), where Ids_sat and Ids_lin are the drain current in saturation and liner modes, respectively, and k is a proportional coefficient of the drain current.
The transconductance is expressed by (25) and (26) in saturation and liner modes, respectively.
Let us assume (27) holds when mESCO runs in steady state, where the peak drain voltage does not change by cycle, because when the left side value of (27) is positive, the amplitude increases by a cycle; whereas when it is negative, the amplitude decreases by a cycle. π 0 g m (θ)dθ = Equation (28) shows that v da is a function of A CG , V IN and V TH . Therefore, the model was compared with the SPICE results in terms of v da vs. A CG , as shown in Figure 11a. Dots in colors show the SPICE results where the circuit parameters are varied as much as the ones in Figure 9. Because the SPICE model for NMOSFET used in this study has no breakdown at high drain voltages, all the simulated data were plotted. However, because there is a strict specification for the maximum voltages in reality, it can limit the design space for the circuit parameters. Even though the model result has an offset from the trend curve of the SPICE results, the model well-represents the tendency that v da is determined by A CG rather than individual circuit parameters. It is interesting to note that the data points of v da and v sa are plotted on a linear line with a slope of 1.00 for both the SPICE results and model calculated results with a slightly different offset of 1.05 and 1.25 V for the SPICE results and model calculated results, respectively, as shown in Figure 11b.   To compare the vda of mESCO with that of ESCO, SPICE simulations and model calculations based on [16] were made with the same parameter conditions for L1, C1, and VIN as mESCO. Figure 13 shows the comparison results. Even though the model accuracy of (28) for mESCO is not as sufficient as that of [16] for ESCO, the trend over circuit parameters represents the SPICE results. With the same values for L1, L2, C1, and C2 as those of ESCO, mESCO has a 2× or larger vda than ESCO.    To compare the vda of mESCO with that of ESCO, SPICE simulations and model calculations based on [16] were made with the same parameter conditions for L1, C1, and VIN as mESCO. Figure 13 shows the comparison results. Even though the model accuracy of (28) for mESCO is not as sufficient as that of [16] for ESCO, the trend over circuit parameters represents the SPICE results. With the same values for L1, L2, C1, and C2 as those of ESCO, mESCO has a 2× or larger vda than ESCO. To compare the v da of mESCO with that of ESCO, SPICE simulations and model calculations based on [16] were made with the same parameter conditions for L 1 , C 1 , and V IN as mESCO. Figure 13 shows the comparison results. Even though the model accuracy of (28) for mESCO is not as sufficient as that of [16] for ESCO, the trend over circuit parameters represents the SPICE results. With the same values for L 1 , L 2 , C 1 , and C 2 as those of ESCO, mESCO has a 2× or larger v da than ESCO. Electronics 2022, 11, x FOR PEER REVIEW 11 of 13 The data in Figure 13 are placed in a single vda−ACG graph as shown in Figure 14. mESCO, as well as ESCO, has a unified characteristic curve. It is essential to design mESCO and ESCO with ACG as close to unity as possible to have a large vda.

Conclusions
We found that an additional L-C-L filter for ESCO, called mESCO, increased the peak drain voltage, which will contribute to increasing the boost ratio when it is used in DC-DC boost converter applications. In this study, the operation frequency, common gate voltage gain, and drain voltage amplitude were analyzed with simple proposed models for mESCO. Even though the frequency model potentially has three different frequencies as a solution, the lower two components were not allowed because an equivalent inductor and capacitor would have had negative inductance and capacitance, respectively. The highest frequency was matched with the SPICE results in wide circuit parameter ranges. The common gate voltage gain was also modeled with a simple circuit transformation. The model calculation results are in good agreement with the SPICE results within a 10% error, except for large CIN. In addition, the drain voltage amplitude was modeled with an assumption that the average transconductance of the switching transistor over a half cycle is null. Even with a simple Shockley model, the drain voltage amplitude was successfully modeled so that it is a function of the common gate voltage gain rather than individual circuit parameters. This fact is valid for ESCO as well as mESCO. In wide ranges of L1, C1, and VIN, the drain voltage amplitude of mESCO was 2× or larger than that of ESCO. ESCO and mESCO had the same trend in the drain voltage amplitude over the common gate voltage gain.
Further experiments to validate the model and SPICE results and an application of mESCO to DC-DC boost converters will be conducted in the future. When a rectifier is added to mESCO for the DC-DC boost converter, it would have another impedance at the drain of the switching transistor, potentially yielding a loss in the drain voltage amplitude The data in Figure 13 are placed in a single v da −A CG graph as shown in Figure 14. mESCO, as well as ESCO, has a unified characteristic curve. It is essential to design mESCO and ESCO with A CG as close to unity as possible to have a large v da . The data in Figure 13 are placed in a single vda−ACG graph as shown in Figure 14. mESCO, as well as ESCO, has a unified characteristic curve. It is essential to design mESCO and ESCO with ACG as close to unity as possible to have a large vda.

Conclusions
We found that an additional L-C-L filter for ESCO, called mESCO, increased the peak drain voltage, which will contribute to increasing the boost ratio when it is used in DC-DC boost converter applications. In this study, the operation frequency, common gate voltage gain, and drain voltage amplitude were analyzed with simple proposed models for mESCO. Even though the frequency model potentially has three different frequencies as a solution, the lower two components were not allowed because an equivalent inductor and capacitor would have had negative inductance and capacitance, respectively. The highest frequency was matched with the SPICE results in wide circuit parameter ranges. The common gate voltage gain was also modeled with a simple circuit transformation. The model calculation results are in good agreement with the SPICE results within a 10% error, except for large CIN. In addition, the drain voltage amplitude was modeled with an assumption that the average transconductance of the switching transistor over a half cycle is null. Even with a simple Shockley model, the drain voltage amplitude was successfully modeled so that it is a function of the common gate voltage gain rather than individual circuit parameters. This fact is valid for ESCO as well as mESCO. In wide ranges of L1, C1, and VIN, the drain voltage amplitude of mESCO was 2× or larger than that of ESCO. ESCO and mESCO had the same trend in the drain voltage amplitude over the common gate voltage gain.
Further experiments to validate the model and SPICE results and an application of mESCO to DC-DC boost converters will be conducted in the future. When a rectifier is added to mESCO for the DC-DC boost converter, it would have another impedance at the drain of the switching transistor, potentially yielding a loss in the drain voltage amplitude

Conclusions
We found that an additional L-C-L filter for ESCO, called mESCO, increased the peak drain voltage, which will contribute to increasing the boost ratio when it is used in DC-DC boost converter applications. In this study, the operation frequency, common gate voltage gain, and drain voltage amplitude were analyzed with simple proposed models for mESCO. Even though the frequency model potentially has three different frequencies as a solution, the lower two components were not allowed because an equivalent inductor and capacitor would have had negative inductance and capacitance, respectively. The highest frequency was matched with the SPICE results in wide circuit parameter ranges. The common gate voltage gain was also modeled with a simple circuit transformation. The model calculation results are in good agreement with the SPICE results within a 10% error, except for large C IN . In addition, the drain voltage amplitude was modeled with an assumption that the average transconductance of the switching transistor over a half cycle is null. Even with a simple Shockley model, the drain voltage amplitude was successfully modeled so that it is a function of the common gate voltage gain rather than individual circuit parameters. This fact is valid for ESCO as well as mESCO. In wide ranges of L 1 , C 1 , and V IN , the drain voltage amplitude of mESCO was 2× or larger than that of ESCO. ESCO and mESCO had the same trend in the drain voltage amplitude over the common gate voltage gain.
Further experiments to validate the model and SPICE results and an application of mESCO to DC-DC boost converters will be conducted in the future. When a rectifier is added to mESCO for the DC-DC boost converter, it would have another impedance at the drain of the switching transistor, potentially yielding a loss in the drain voltage amplitude and thereby a degradation of the output power of the DC-DC converter. One would need to analyze its impact to design a DC-DC converter with sufficient output power.