An Integrated Buck and Half-Bridge High Step-Down Converter

: In this paper, an integrated buck and asymmetrical half-bridge (IBAHB) high step-down converter utilizing a single-stage driving design for highly efﬁcient energy conversion is proposed. The proposed converter is able to instantly and synchronously transfer energy from input to output within one conversion period. The advantages of high step-down conversion, lower voltage stress and fewer semiconductor elements verify the feasibility of this proposed topology. The turns ratio of the transformer can be reduced to increase the coupling rate, which decreases the leakage inductance. The proposed integrated topology utilizes the single-stage energy transfer control algorithm to verify that the proposed experimental circuit has a full-load efﬁciency. This development will achieve the market’s demand for high-buck converters and other related products and the competitive advantage of growing with the trend.


Introduction
High step-down converters and high efficiency energy transformation are increasingly required in many industrial applications such as UPSs, LEDs, voltage regulator for MCUs, battery chargers, EVs and power supply for railways. A buck converter and a modified push−pull converter are merged in a novel conversion topology with galvanic isolation; thus, a high step-down ratio is easily achieved without extremely low duty cycle or high turns ratio of the transformer in [1]. Based on the capacitive voltage division, the main objectives of the converter are storing energy in the blocking capacitors for increasing the step-down conversion ratio and reducing voltage stresses. As a result, the converter topology possesses the low switch voltage stress and chooses lower voltage rating MOSFETs to reduce both switching and conduction losses, and the overall efficiency is consequently improved in [2]. An integrated conventional buck-boost converter with a coupled inductor is proposed. The coupled inductor operates not only as a filter inductor of the buck-boost, but also as a transformer [3]. In [4], for the high step-down multiple output and high conversion ratio, isolated bidirectional distributed energy storage systems in [5] are proposed. A new singleswitch (without considering SR switch) coupled inductor high step-down converter with an extended duty cycle and non-pulsating output current is presented in [6]. In order to recover the leakage energy, a simple lossless clamp circuit is also proposed. A non-isolated ultra-high step-down interleaved converter with low voltage stress and common ground between the input and output ports is proposed in [7]. High stepdown converters and a new topology ISC-TaB and LLC converter are discussed [8,9]. A single-stage step-down ac-dc universal input voltage application is proposed in [10]. A high step-up/down resonant converter at MHz switching frequency, as well as the circuit design techniques to reduce the parasitic effects are discussed in [11]. High efficiency under both full-load and light-load conditions [12] and auto-balanced hybrid LLC series resonant converters with flying capacitors have been proposed in [13]. A High efficiency under both full-load and light-load conditions [12] and auto-balanced brid LLC series resonant converters with flying capacitors have been proposed in [1 bidirectional dc-dc converter with a coupled inductor is proposed in [14,15], which is able for applications requiring a large step-down ratio topology. A high-efficiency S step-down converter was applied well to a single input power source plus two ou terminals in [16]. An isolated bidirectional dc-dc converter with low current ripples discussed in [17]. An isolated double step-down dc-dc converter was proposed in [18 present, most of the high step-down converters studied in the literature are 400 V/4 and 380 V/5 V converters are rarely studied. The buck converter with coupled wind showing excellent ZVS operation, was proposed in [19]. In this paper, the proposed to ogy can lower the voltage on the transformer and thus the turns ratio can be reduced shown in Figure 1, the proposed high step-down converter can be used for power su in renewable energy conversion and high DC conversion systems applications. DC can be regarded as the battery of electric vehicles. In this situation, more convert needed to lower the DC voltage from high DC voltage for load use. The main consid tion of this research is the demand for possible future development, so the comm used 5V output voltage specification is preliminarily determined. It can be speculated the power supply system used in green energy applications in the future must rel high-voltage buck converters to provide stable low-voltage power supplies. In order to achieve a very high step-down ratio in the design of the buck conve the conduction period is extremely low, so the conversion efficiency cannot be impro Isolated buck conversion topologies are designed to achieve very high step-down vo gain; the higher transformer turns ratio results in poor coupling, increased leakage ind ance and reduced conversion efficiency. Considering that the isolated high step-d conversion ratio design uses an integrated Buck+AHB cascade topology, in ord achieve high conversion efficiency, the power switch switching must achieve the effe single-stage power flow. Thus, we propose an isolated high step-down converter. Th timized design of single-stage signal-driven power switches in buck and half-bridge cading topologies enables synchronous power flow from the input stage to the ou stage within one switching period, allowing efficient energy conversion. In order to achieve a very high step-down ratio in the design of the buck converter, the conduction period is extremely low, so the conversion efficiency cannot be improved. Isolated buck conversion topologies are designed to achieve very high step-down voltage gain; the higher transformer turns ratio results in poor coupling, increased leakage inductance and reduced conversion efficiency. Considering that the isolated high step-down conversion ratio design uses an integrated Buck+AHB cascade topology, in order to achieve high conversion efficiency, the power switch switching must achieve the effect of single-stage power flow. Thus, we propose an isolated high step-down converter. The optimized design of single-stage signal-driven power switches in buck and half-bridge cascading topologies enables synchronous power flow from the input stage to the output stage within one switching period, allowing efficient energy conversion.

Integrated Buck and Asymmetrical Half-Bridge (IBAHB) Converter
The integrated buck and asymmetrical half-bridge (IBAHB) converter is shown in Figure 2. There are two elements, C 1 and C pT , for reducing the energy of the leakage inductance, which enables the suppression of the peak voltage on the power switches, thus allowing power switches with lower R DS(on) to be utilized; consequently, the reduced voltage stress improves its efficiency. A buck-type circuit is added to the primary side, which makes the voltage on the transformer unequal to V i Therefore, the turns ratio of the transformer can be reduced to increase the coupling rate, which decreases the leakage inductance. The proposed topology uses four signals that are created by a pair of push-pull signals and a pair of complementary signals to control the power switches. The half-bridge ones are used for the main switches, and the complementary ones are used for synchronous rectification. The secondary side employs a dual-winding center-tapped rectifier circuit to double the frequency of the output inductor current, which can reduce the output current ripple. Therefore, the output inductor and the output capacitor can both be designed with a smaller volume.
Electronics 2022, 11,2666 thus allowing power switches with lower DS(on) R to be utilized; consequently, the r voltage stress improves its efficiency. A buck-type circuit is added to the prima which makes the voltage on the transformer unequal to V i Therefore, the turns the transformer can be reduced to increase the coupling rate, which decreases the inductance. The proposed topology uses four signals that are created by a pair o pull signals and a pair of complementary signals to control the power switches. T bridge ones are used for the main switches, and the complementary ones are u synchronous rectification. The secondary side employs a dual-winding center-tapp tifier circuit to double the frequency of the output inductor current, which can red output current ripple. Therefore, the output inductor and the output capacitor c be designed with a smaller volume.

Operating Principles
The equivalent circuit of the IBAHB is shown in Figure 3. The 1 L and 2 L re the energy-storing inductor and the output inductor, respectively.  Figure 4. There a transient states, which are depicted as follows. Figure 3. Equivalent circuit of the proposed IBAHB.

Operating Principles
The equivalent circuit of the IBAHB is shown in Figure 3. The L 1 and L 2 represent the energy-storing inductor and the output inductor, respectively. Switches S 1 , S 2 , and S 3 are the main switches of this topology, and switches SR 1 and SR 2 are the synchronous rectifiers.
voltage stress improves its efficiency. A buck-type circuit is added to the prima which makes the voltage on the transformer unequal to V i Therefore, the turns the transformer can be reduced to increase the coupling rate, which decreases the inductance. The proposed topology uses four signals that are created by a pair o pull signals and a pair of complementary signals to control the power switches. T bridge ones are used for the main switches, and the complementary ones are u synchronous rectification. The secondary side employs a dual-winding center-tapp tifier circuit to double the frequency of the output inductor current, which can red output current ripple. Therefore, the output inductor and the output capacitor c be designed with a smaller volume.

Operating Principles
The equivalent circuit of the IBAHB is shown in Figure 3. The 1 L and 2 L re the energy-storing inductor and the output inductor, respectively. Switches 1 S , 3 S are the main switches of this topology, and switches 1 SR and 2 SR are the sy nous rectifiers.
Diode fw D is a flywheel diode, 1 C and pT C are the switching capacitors, and the filter capacitor. The primary side of the transformer is defined as N p , and ondary side is defined as s1 N and s 2 N . The turns ratio is defined as n ( n = s N s 2 p N N ). The transient-state waveforms in CCM are shown in Figure 4. There a transient states, which are depicted as follows. Figure 3. Equivalent circuit of the proposed IBAHB. Diode D f w is a flywheel diode, C 1 and C DS are the switching capacitors, and C O is the filter capacitor. The primary side of the transformer is defined as N p , and the secondary side is defined as N s1 and N s2 . The turns ratio is defined as n (n = N s1 /N p = N s2 /N p ). The transient-state waveforms in CCM are shown in Figure 4. There are eight transient states, which are depicted as follows.

Mode 1 [t 0~t1 ]
In Figure 5a, in this interval, the main switches S 1 and S 2 and the synchronous rectifier SR 1 are in the turned-on state. Voltage source V i transfers the energy to the inductor L 1 and capacitor C pT through the main switch S 2 . At the same time, capacitor C 1 discharges the energy stored by the previous cycle to C pT also through S 2 . The transformer starts to send Electronics 2022, 11, 2666 5 of 26 energy from the primary side to the secondary side. The current of the output inductor L 2 maintains its freewheeling state while passing through SR 1 and the body diode of SR 2 . However, the current passing through SR 2 decreases, and the current of SR 1 increases. The inductor currents i L1 , i N p , i Lm and i L2 are given, respectively, by Lm i and L 2 i are given, respectively, by

Mode 8 [t7~t8]
In Figure 5h, in this interval, the main switches 1 S , 2 S , and 3 S are in the turned-off state and the switches of the synchronous rectifier

Steady-State Analysis
In order to simplify the analysis, the proposed architecture is presumed to operate in continuous conduction mode (CCM), the method of control is shown in Figure 6. The characteristics of the transient state over the circuit will be ignored, and the currents passing through all of the components will be considered in DC. In addition, there are some assumptions listed as follows: (1) All components possess ideal characteristics.
(2) The coupling coefficient of the transformer is unity.

Mode 2 [t 1~t2 ]
In Figure 5b, in this interval, the main switches S 1 and S 2 and one of the synchronous rectifier switches, SR 1 , remain in the turned-on state. The voltage source V i continues transferring the energy to the energy-storage inductor L 1 and capacitor C pT , and the capacitor C 1 is still discharging to C pT . The transformer continues transferring the energy to the secondary side, and output inductor L 2 and output capacitor C O are storing the energy provided by the transformer. The inductor currents i L1 , i N p , i Lm and i L2 are given, respectively, by

Mode 3 [t 2~t3 ]
In Figure 5c, in this interval, the main switches S 1 , S 2 , and S 3 are in the turned-off state, while the switches of the synchronous rectifier, SR 1 and SR 2 , are in the turned-on state. The parasitic body diode of switch S 3 turns ON due to the freewheeling characteristic of leakage inductance. Additionally, the energy of leakage inductance can be retrieved by capacitor C pT . Inductor L 1 releases energy through D f w to capacitor C 1 by its freewheeling state; moreover, the output inductor L 2 starts releasing the energy passing through SR 1 and SR 2 to provide the load R L . The inductor currents i L1 , i N p , i Lm and i L2 are given, respectively, by

Mode 4 [t 3~t4 ]
In Figure 5d, in this interval, the main switches S 1 , S 2 , and S 3 remain in the turned-off state. Inductor L 1 continues releasing energy to C 1 through D f w . Output inductor L 2 also keeps releasing energy to R L , through SR 1 and SR 2 . The inductor currents i L1 , i N p , i Lm and i L2 are given, respectively, by

Mode 5 [t 4~t5 ]
In Figure 5e, in this interval, the main switch S 3 and one of the synchronous rectifiers SR 2 are in the turned-on state; the other switches are turned off. The inductor L 1 keeps releasing energy to the capacitor C 1 . When S 3 turns on, the capacitor C pT starts to release the stored energy, which can transfer to N s2 on the secondary side. Because the C pT releases energy, the current passing through SR 1 can decrease to zero, and the current passing through SR 2 can increase. The inductor currents i L1 , i N p , i Lm and i L2 are given, respectively, by

Mode 6 [t 5~t6 ]
In Figure 5f, in this interval, switch S 3 and the switch of the synchronous rectifier SR 2 remain in the turned-on state; the other switches are turned off. This mode is similar to mode 5. However, the current is no longer passing through switch SR 1 . The inductor currents i L1 , i N p , i Lm and i L2 are given, respectively, by

Mode 7 [t 6~t7 ]
In Figure 5g, in this interval, the main switches S 1 , S 2 , and S 3 are in the turned-off state, while the switches of the synchronous rectifier SR 1 and SR 2 are in the turned-on state.
The switching capacitor C 1 can recover the leakage inductor energy. In this interval, the load energy is absorbed by the output inductor. The inductor currents i L1 , i N p , i Lm and i L2 are given, respectively, by

Mode 8 [t 7~t8 ]
In Figure 5h, in this interval, the main switches S 1 , S 2 , and S 3 are in the turned-off state and the switches of the synchronous rectifier SR 1 and SR 2 are in the turned-on state. Same as Mode 4, inductors L 1 and L O release the energy to the switching capacitor C 1 and the load, respectively. The inductor currents i L1 , i N p , i Lm and i L2 are given, respectively, by

Steady-State Analysis
In order to simplify the analysis, the proposed architecture is presumed to operate in continuous conduction mode (CCM), the method of control is shown in Figure 6. The characteristics of the transient state over the circuit will be ignored, and the currents passing through all of the components will be considered in DC. In addition, there are some assumptions listed as follows: (1) All components possess ideal characteristics.
(2) The coupling coefficient of the transformer is unity.
(3) The duty cycle is low, under 50%. continuous conduction mode (CCM), the method of control is shown in Figure 6. The characteristics of the transient state over the circuit will be ignored, and the currents passing through all of the components will be considered in DC. In addition, there are some assumptions listed as follows: (1) All components possess ideal characteristics.
(2) The coupling coefficient of the transformer is unity.
(3) The duty cycle is low, under 50%. (4) The subscript "pft" denotes the average current in the corresponding mode. Figure 6. The switching sequence of the proposed topology.

Mode 1 [0, DT]
The main switches S1 and S2 are in the turned-on state. The input voltage source transfers energy to the inductor L1 and capacitor CpT. At the same time, the capacitor C1 also provides energy to CpT through S2. On the secondary side, the output inductor L2 and the output capacitor Co are charging from the transformer and the Co supplies energy to load RL. The equivalent circuit is shown in Figure 7 and the formulas can be expresses as:

Mode 1 [0, DT]
The main switches S 1 and S 2 are in the turned-on state. The input voltage source transfers energy to the inductor L 1 and capacitor C pT . At the same time, the capacitor C 1 also provides energy to C pT through S 2 . On the secondary side, the output inductor L 2 and the output capacitor C o are charging from the transformer and the C o supplies energy to load R L . The equivalent circuit is shown in Figure 7 and the formulas can be expresses as: Electronics 2022, 11, 2666 9 of 27 Figure 7. The switches S1, S2 and SR1 are in the turned-on state.

Mode 2 [DT, 0.5T]
The main switches S1, S2 and S3 are in the turned-off state. Inductor L1 changes into the freewheeling state to release energy to the capacitor C1. Output inductor Lo also turns into the freewheeling state to release energy to the capacitor Co and load RL. The equivalent circuit is shown in Figure 8 and the formulas can be expressed as:

Mode 2 [DT, 0.5T]
The main switches S 1 , S 2 and S 3 are in the turned-off state. Inductor L 1 changes into the freewheeling state to release energy to the capacitor C 1 . Output inductor L o also turns into the freewheeling state to release energy to the capacitor C o and load R L . The equivalent circuit is shown in Figure 8 and the formulas can be expressed as: circuit is shown in Figure 8 and the formulas can be expressed as: Figure 8. The switches S1, S2 and S3 are in the turned-off state.

Mode 3 [0.5T, (0.5+D)T]
The main switch S3 is in the turned-on state. Capacitor CpT starts to release energy through the transformer to the secondary side. Inductor L1 still keeps releasing energy to the capacitor C1. The output inductor L2 and the output capacitor Co are charging using the transformer, and the Co supplies energy to load RL. The equivalent circuit is shown in Figure 9 and the formulas can be expressed as: The main switch S 3 is in the turned-on state. Capacitor C pT starts to release energy through the transformer to the secondary side. Inductor L 1 still keeps releasing energy to the capacitor C 1 . The output inductor L 2 and the output capacitor C o are charging using the transformer, and the C o supplies energy to load R L . The equivalent circuit is shown in Figure 9 and the formulas can be expressed as: Electronics 2022, 11, 2666 1 Figure 9. The switches S3 and SR2 are in the turned-on state.

Mode 4 [(0.5+D)T, T]
Mode 4 is similar to Mode 2. The main switches S1, S2 and S3 are in the turn state. Inductor L1 still keeps the freewheeling state to release energy to the capaci Output inductor Lo turns into the freewheeling state to release energy to the capac and load RL. The equivalent circuit is shown in Figure 10 and the formulas can pressed as:

Mode 4 [(0.5+D)T, T]
Mode 4 is similar to Mode 2. The main switches S 1 , S 2 and S 3 are in the turned-off state. Inductor L 1 still keeps the freewheeling state to release energy to the capacitor C 1 . Output inductor L o turns into the freewheeling state to release energy to the capacitor C o and load R L . The equivalent circuit is shown in Figure 10 and the formulas can be expressed as: pressed as: Figure 10. The switches SR1 and SR2 are in the turned-on state.

Voltage Gain
All the voltages of the capacitors can be derived using the charge balance. The relative equations of the energy-storage inductors L1 and L2 are given as Because the proposed circuit is an asymmetric architecture, the volt-second balance equation of the output inductor L2 will be divided into two parts of derivations: Figure 10. The switches SR 1 and SR 2 are in the turned-on state.

Voltage Gain
All the voltages of the capacitors can be derived using the charge balance. The relative equations of the energy-storage inductors L 1 and L 2 are given as (41) and (46) into (51), the voltage of the capacitor C 1 can be given by Because the proposed circuit is an asymmetric architecture, the volt-second balance equation of the output inductor L 2 will be divided into two parts of derivations: Substituting Equations (32) and (37) into (53) will give Substituting Equations (42) and (47) Equations (55) and (56) will be equal, and substitute (52). The voltage of the capacitor C pT can be obtained by Finally, use Equations (56) and (57) to obtain the ideal voltage gain of the proposed architecture. The ideal voltage gain curve is shown in Figure 11: Finally, use Equations (56) and (57) to obtain the ideal voltage gain of the proposed architecture. The ideal voltage gain curve is shown in Figure 11: = • (58) Figure 11. Ideal voltage gain of the proposed topology.

Voltage Stress
The voltage stresses of semiconductor devices can be derived by the known voltage of all the capacitors. Therefore, when the main switches S1 and S2 are in the turned-on state, the voltage stress of switch S3 will be equal to the voltage of the capacitor C1, as shown in Figure 7.
The voltage stress of the freewheeling diode Dfw can be given by = Additionally, the voltage stress of the synchronous rectifier switch SR2 will be equal to the sum of VNs1 and VNs2, which is also equal to VC1 minus VCpT and then multiplied two times by the turns ratio 2n. Figure 11. Ideal voltage gain of the proposed topology.

Voltage Stress
The voltage stresses of semiconductor devices can be derived by the known voltage of all the capacitors. Therefore, when the main switches S 1 and S 2 are in the turned-on state, the voltage stress of switch S 3 will be equal to the voltage of the capacitor C 1 , as shown in Figure 7.
The voltage stress of the freewheeling diode D fw can be given by Additionally, the voltage stress of the synchronous rectifier switch SR 2 will be equal to the sum of V Ns1 and V Ns2 , which is also equal to V C1 minus V CpT and then multiplied two times by the turns ratio 2n.
when the switch S 3 is turned on, switches S 1 and S 2 are turned off. As shown in Figure 9, the voltage stress of the S 1 is equal to the sum of the input voltage V i and the capacitor C 1 . The voltage stress of S 2 is equal to the capacitor C 1 and the voltage stress can be given by Because the secondary winding structure is symmetrical, the voltage stress of the synchronous rectifier SR 1 is the same as SR 2 . The voltage stress can be given by when the input voltage and the turns ratio n equal 380V and 1 12 , respectively, the relationship between the voltage stress and the duty cycle is shown in Figure 12. It can be seen from Equations (53) and (57) that S 2 and S 3 have relatively lower voltage stress. Hence, lowvoltage-stress power devices, such as MOSFETs with low R DS(on) , can be employed. Similar to switches S 2 and S 3 , SR 1 and SR 2 can also adapt low-voltage-stress power devices with low R DS(on) to reduce the loss of semiconductors to improve efficiency.
when the input voltage and the turns ratio n equal 380V and , respectively, the relationship between the voltage stress and the duty cycle is shown in Figure 12. It can be seen from Equations (53) and (57) that S2 and S3 have relatively lower voltage stress. Hence, low-voltage-stress power devices, such as MOSFETs with low RDS(on), can be employed. Similar to switches S2 and S3, SR1 and SR2 can also adapt low-voltage-stress power devices with low RDS(on) to reduce the loss of semiconductors to improve efficiency.

Current Stresses
Due to the law of conservation of energy, the output current IRo is equal to the input current Ii divided by the voltage gain, which can be expressed as The main switches S1 and S2 are in the turned-on state and S3 is in the turned-off state, which is shown in Figure 7. The current through S1 and S2 can be expressed as The main switches S1, S2 and S3 are in the turned-off state, as shown in Figure 8. During this period, the current stresses through other semiconductor devices can be expressed as

Current Stresses
Due to the law of conservation of energy, the output current I Ro is equal to the input current I i divided by the voltage gain, which can be expressed as The main switches S 1 and S 2 are in the turned-on state and S 3 is in the turned-off state, which is shown in Figure 7. The current through S 1 and S 2 can be expressed as The main switches S 1 , S 2 and S 3 are in the turned-off state, as shown in Figure 8. During this period, the current stresses through other semiconductor devices can be expressed as As shown in Figure 9, the switch S 3 turns into the ON state, while the main switches S 1 and S 2 remain turned off. The current through the semiconductor devices can be expressed as when the main switches S 1 , S 2 and S 3 are in the turned-off state again, the current flowing through the semiconductor devices would be the same as the previous operation mode. The highest current flowing through each semiconductor element is the criterion for selecting current stress. The current stress of all the semiconductor devices would be reorganized and expressed below i DS1(stress) = nD · i R L (peak) (74) When the output current and the turns ratio n equal 40A and 1 12 , respectively, the relationship between the average current stress and the duty cycle is shown in Figure 13.
through the semiconductor devices would be the same as the previous operation mode.
The highest current flowing through each semiconductor element is the criterion for selecting current stress. The current stress of all the semiconductor devices would be reorganized and expressed below When the output current and the turns ratio n equal 40A and , respectively, the relationship between the average current stress and the duty cycle is shown in Figure 13.

Conduction Loss Analysis
The equivalent circuit for analyzing the conduction loss of inductors and semiconductor devices is shown in Figure 14

Conduction Loss Analysis
The equivalent circuit for analyzing the conduction loss of inductors and semiconductor devices is shown in Figure 14, in which r L1 and r L2 are the copper resistance of the inductors, r D f w and V D f w are the on-resistance and the forward voltage of the diode, respectively, r DS_S1 , r DS_S2 , r DS_S3 , r DS_SR1 and r DS_SR2 are the on-resistances of the switches.

Mode 1 [0, DT]
The main switches S1 and S2 are in turned-on state. The voltage source Vi transfers energy to the inductors L1 and the capacitor CpT receives energy from Vi and the capacitor C1.
Simultaneously, the output inductor L2 and capacitor Co are charging through the transformer, and then Co supplies energy to the load RL. The equivalent circuit is shown in Figure 15 and the formulas are expressed as follows:

Mode 1 [0, DT]
The main switches S 1 and S 2 are in turned-on state. The voltage source V i transfers energy to the inductors L 1 and the capacitor C pT receives energy from V i and the capacitor C 1 .
Simultaneously, the output inductor L 2 and capacitor C o are charging through the transformer, and then C o supplies energy to the load R L . The equivalent circuit is shown in Figure 15 and the formulas are expressed as follows: Figure 14. Equivalent circuit with parasitic components of the proposed topology.

Mode 1 [0, DT]
The main switches S1 and S2 are in turned-on state. The voltage source Vi transfers energy to the inductors L1 and the capacitor CpT receives energy from Vi and the capacitor C1.
Simultaneously, the output inductor L2 and capacitor Co are charging through the transformer, and then Co supplies energy to the load RL. The equivalent circuit is shown in Figure 15 and the formulas are expressed as follows:

Mode 2 [DT, 0.5T]
The main switches S1, S2 and S3 are in the turned-off state. In this interval, the inductor L1 releases energy to the capacitor C1, and the output inductor L2 changes into the freewheeling state, releasing energy to the output load RL. The equivalent circuit is shown in Figure 16 and the formulas are expressed as follows:

Mode 2 [DT, 0.5T]
The main switches S 1 , S 2 and S 3 are in the turned-off state. In this interval, the inductor L 1 releases energy to the capacitor C 1 , and the output inductor L 2 changes into the freewheeling state, releasing energy to the output load R L . The equivalent circuit is shown in Figure 16 and the formulas are expressed as follows:

Mode 3 [0.5T, (0.5+D) T]
In this interval, the main switch S3 is in the turned-on state. The inductor L1 keeps releasing energy to the capacitor C1, and the capacitor CpT sends the energy to the output inductor L2 and output capacitor Co through the transformer. Then, Co provides energy to the output load RL. The equivalent circuit is shown in Figure 17 and the formulas are expressed as follows:

Mode 3 [0.5T, (0.5+D) T]
In this interval, the main switch S 3 is in the turned-on state. The inductor L 1 keeps releasing energy to the capacitor C 1 , and the capacitor C pT sends the energy to the output inductor L 2 and output capacitor C o through the transformer. Then, C o provides energy to the output load R L . The equivalent circuit is shown in Figure 17 and the formulas are expressed as follows: In this interval, the main switch S3 is in the turned-on state. The inductor L1 keeps releasing energy to the capacitor C1, and the capacitor CpT sends the energy to the output inductor L2 and output capacitor Co through the transformer. Then, Co provides energy to the output load RL. The equivalent circuit is shown in Figure 17 and the formulas are expressed as follows:

Mode 4 [(0.5+D) T, T]
Similar to the Mode 2 state, the main switches S1, S2 and S3 are all in the turned-off state. The inductor L1 keeps releasing energy to the capacitor C1 and the output inductor L2 changes into the freewheeling state, releasing energy to the output load RL. The equivalent circuit is shown in Figure 18 and the formulas are expressed as follows:

Mode 4 [(0.5+D) T, T]
Similar to the Mode 2 state, the main switches S 1 , S 2 and S 3 are all in the turned-off state. The inductor L 1 keeps releasing energy to the capacitor C 1 and the output inductor L 2 changes into the freewheeling state, releasing energy to the output load R L . The equivalent circuit is shown in Figure 18 and the formulas are expressed as follows: Second, the proposed circuit is an asymmetric topology, so the volt-second balance equation of the output inductor L 2 should be divided into two parts of derivations: Substitute Equations (81) and (84) into (92) and simplify it. Then, replace r SR1 with r SR , which is shown below.
Substitute Equations (86) and (89) into (93) and simplify it. Then, replace r SR2 with r SR , which is shown below.
It is known that the summation and subtraction of Equations (94) and (95) are equal to zero, which are expressed as follows, respectively: Substitute v C1 of Equation (97) with Equation (91) and simplify it. Then, into Equation (95), as follows: Then, transfer Equation (98) into an equivalent circuit module, as shown in Figure 19.
Then, transfer Equation (98) into an equivalent circuit module, as shown in Figure  19. r a = n 2 D 3 · (r D f w − r DS S1 ) (99) Divide Equation (98) by V i to obtain the voltage gain of the non-ideal state, which is expressed as is the efficiency equation of the non-ideal state, which is expressed as follows: where After calculating, the non-ideal voltage gain and the efficiency curve are shown below, as Figures 20 and 21.

Inductances
In order to achieve high step-down conversion, the proposed power topology requires components that can store energy and stabilize potential. Thus, this section analyzes and discusses the ripple characteristics of the energy storage elements.

Inductances
In order to achieve high step-down conversion, the proposed power topology requires components that can store energy and stabilize potential. Thus, this section analyzes and discusses the ripple characteristics of the energy storage elements.

Inductances
In order to achieve high step-down conversion, the proposed power topology requires components that can store energy and stabilize potential. Thus, this section analyzes and discusses the ripple characteristics of the energy storage elements.
First, the corresponding equation of inductance and current ripple can be expressed as follows: Substituting Equation (31) into (112) would deduce the relationship between the inductor L 1 and current ripple, which is expressed as follows: The condition of the L 1 working in the boundary conduction mode (BCM) is expressed below: Obtain the equation of the L 1 working in BCM with (113) and (114), which is shown below: As shown in Figure 22, the curve shows the value of L 1 working in BCM at each duty cycle with a switching frequency of 50kHz and 1 12 turns ratio.
The condition of the L1 working in the boundary conduction mode (BCM) is expressed below: Obtain the equation of the L1 working in BCM with (113) and (114), which is shown below: As shown in Figure 22, the curve shows the value of L1 working in BCM at each duty cycle with a switching frequency of 50kHz and turns ratio. Next, derivate the equation of the output inductor L2 in BCM. Substitute Equation (37) into Equation (112), and the relationship between L2 and its current ripple would be derived as follows: The condition of L2 working in BCM is expressed as follows: Obtain the equation of the L2 working in BCM with Equations (116) and (117), as follows: Next, derivate the equation of the output inductor L 2 in BCM. Substitute Equation (37) into Equation (112), and the relationship between L 2 and its current ripple would be derived as follows: The condition of L 2 working in BCM is expressed as follows: Obtain the equation of the L 2 working in BCM with Equations (116) and (117), as follows: As shown in Figure 23, the curve shows the value of inductor L 2 working in BCM at each duty cycle with a switching frequency of 50 kHz and 1 12 turns ratio.

Capacitors
The equation of the relationship between all capacitors and voltage ripple in the proposed topology can be expressed as: According to Equation (119), the relationship between the value of each capacitor and its voltage ripple can be expressed as follows:

Control Block Diagram
As shown in Figure 24, after feedback voltage VFB is calculated and processed, a group of output signals VGS1,2 is generated through the comparison result with the sawtooth wave, and then VGS3 and the secondary side synchronous rectification control signal VGS_SR1 and VGS_SR2 are generated through the delay and the reversed signal.

Capacitors
The equation of the relationship between all capacitors and voltage ripple in the proposed topology can be expressed as: According to Equation (119), the relationship between the value of each capacitor and its voltage ripple can be expressed as follows:

Control Block Diagram
As shown in Figure 24, after feedback voltage V FB is calculated and processed, a group of output signals V GS1,2 is generated through the comparison result with the sawtooth wave, and then V GS3 and the secondary side synchronous rectification control signal V GS_SR1 and V GS_SR2 are generated through the delay and the reversed signal. Figure 24. A diagram of the proposed control scheme.

Design of Storage Elements
The turns ratio of the transformer n is preset to , so the duty cycle is almost equal to 0.4 (0.397). The derivation of the duty cycle is shown below.
The design of the inductance value operating in boundary mode is divided into two parts: the inductor L1 and the output inductor L2. Assume the inductor L1 working in the boundary conduction mode (BCM) is at 20% of full load and use the parameters in Equation (115). The inductance value of L1 in BCM is shown below: In addition, the output inductance L2 is preset working in BCM at 5% of full load and use the parameters in Equation (118), which is shown below: Additionally, the number of turns Np is calculated as follows: At full load, the allowable voltage ripple of the output capacitor Co would be designed to be less than 0.5%, and the capacitors C1 and CpT would be designed to be less than 1%. Use the parameters in Equations (120) to (122), and the capacitance value is calculated as follows:

Design of Storage Elements
The turns ratio of the transformer n is preset to 1 12 , so the duty cycle is almost equal to 0.4 (0.397). The derivation of the duty cycle is shown below.
The design of the inductance value operating in boundary mode is divided into two parts: the inductor L 1 and the output inductor L 2 . Assume the inductor L 1 working in the boundary conduction mode (BCM) is at 20% of full load and use the parameters in Equation (115). The inductance value of L 1 in BCM is shown below: In addition, the output inductance L 2 is preset working in BCM at 5% of full load and use the parameters in Equation (118), which is shown below: Additionally, the number of turns N p is calculated as follows: At full load, the allowable voltage ripple of the output capacitor C o would be designed to be less than 0.5%, and the capacitors C 1 and C pT would be designed to be less than 1%. Use the parameters in Equations (120) to (122), and the capacitance value is calculated as follows: Using Equations (52) and (57), the voltage generated by the capacitors C 1 and C pT is calculated as follows, respectively.
At full load, the reverse voltage and forward current of the diode can be calculated by (60) and (69), respectively.
The voltage stress of the power switches can be calculated using Equations (59) and (61)-(64), and the average current of the ones can be calculated using (74), (76)-(79), which is shown as follows:

Experimental Results
The specification and component parameters of the proposed topology are shown in Tables 1 and 2, respectively. Additionally, Figure 25 shows the presented converter and marks the main components. Experimental waveforms for the proposed topology at a full load of 200 W are shown in Figure 26. Figure 26a shows the voltage stress of the main switch S 1 and freewheeling diode D fw , and it can be seen from the waveform that the withstand voltage of the main switch and the flywheel diode D fw is very small. Figure 26b shows the voltage and current stress of S 2 , the voltage and current stress of S 2 are reasonable. Figure 26c shows the voltage and current stress of S 3 , the voltage stress and current stress of S 3 are reasonable. Figure 26d shows the voltage of C pT and the current through the transformer i Lk , from the i Lk current waveform. It can be seen that the current flowing through the transformer is balanced and symmetrical, and no bias phenomenon occurs. Figure 26e shows the voltage and current stress of SR 1 and SR 2 ; the voltage and current of the synchronous rectification in the waveform are correct. Figure 26f shows i L1 and i L2 , respectively, the current of L 2 is twice the switching frequency, effectively reducing the ripple of the output current.        Figure 27 shows the reality of the measured data for the proposed converter, obtained by a power analyzer of HIOKI 3390. The maximum efficiency and full-load efficiency of the proposed topology are 86.65% and 85.17%, respectively. The experimental results confirm that the proposed topology is effective and feasible. When the circuit has a full load of 200 W, maximum efficiency occurs at 140 W, as shown in Figure 28.   Figure 27 shows the reality of the measured data for the proposed converter, obtained by a power analyzer of HIOKI 3390. The maximum efficiency and full-load efficiency of the proposed topology are 86.65% and 85.17%, respectively. The experimental results confirm that the proposed topology is effective and feasible. When the circuit has a full load of 200 W, maximum efficiency occurs at 140 W, as shown in Figure 28. The maximum efficiency and full-load efficiency of the proposed topology are 86.65% and 85.17%, respectively. The experimental results confirm that the proposed topology is effective and feasible. When the circuit has a full load of 200 W, maximum efficiency occurs at 140 W, as shown in Figure 28. In Table 3, the proposed topology is compared with the number of MOSFETs and the number of diodes in Ref. [1]. It is shown that in the proposed topology, the main switch is a half-bridge and the synchronous rectification is complementary. The full load (250 W) efficiency of Ref. [1] is 81.44%, while the peak efficiency is 84.45%. Our proposed topology is 85.17% efficient at a full load of 200 W, but the maximum efficiency (86.65%) occurs at 140 W. In the voltage stress comparison, our proposed topology has lower voltage stress.
The power switch signals are divided into two parts, as shown in Figure 24: the pushpull control type signal and its complementary signals. The push-pull control type signal enables the core of the transformer to be reset without additional reset circuits. The frequency of the current ripple is double the switching frequency, which is helpful for reducing the volume of the inductor L2 and capacitor Co. The frequency of the current ripple is twice the switching frequency. Additionally, it is helpful to reduce the volume of the inductor L2 and capacitor Co. Simultaneously, if the semiconductor component possesses a low RDS(on), it would help improve efficiency.  In Table 3, the proposed topology is compared with the number of MOSFETs and the number of diodes in Ref. [1]. It is shown that in the proposed topology, the main switch is a half-bridge and the synchronous rectification is complementary. The full load (250 W) efficiency of Ref. [1] is 81.44%, while the peak efficiency is 84.45%. Our proposed topology is 85.17% efficient at a full load of 200 W, but the maximum efficiency (86.65%) occurs at 140 W. In the voltage stress comparison, our proposed topology has lower voltage stress. The power switch signals are divided into two parts, as shown in Figure 24: the push-pull control type signal and its complementary signals. The push-pull control type signal enables the core of the transformer to be reset without additional reset circuits. The frequency of the current ripple is double the switching frequency, which is helpful for reducing the volume of the inductor L 2 and capacitor C o . The frequency of the current ripple is twice the switching frequency. Additionally, it is helpful to reduce the volume of the inductor L 2 and capacitor C o . Simultaneously, if the semiconductor component possesses a low R DS(on) , it would help improve efficiency.

Conclusions
We propose a new high step-down conversion prototype through references, theoretical analysis and experimental results. The proposed topology has active clamping to recover the energy of leakage inductance, which would reduce the spike voltage. Hence, it could employ a semiconductor component with lower voltage stress. The proposed topology has the following advantage: by adding a step-down conversion architecture on the primary side, the potential of the transformer could be effectively reduced. Then, it could obtain a high step-down conversion ratio without an extremely low duty cycle or a high turns ratio.
The power switch signals are divided into two parts: the push-pull control type signal and its complementary signals. Additionally, the push-pull control type signal could reset the core of the transformer without additional reset circuits. The core of the transformer operates in quadrants I and III, so the utilization rate of the core is high which could reduce the volume of the whole transformer.