A High-Stability Regulation Circuit with Adaptive Linear Pole–Zero Tracking Compensation for USB Type-C Interface

: We present a high-stability regulation circuit to ensure the safety of a device within a wide range of the back-sink current for a USB Type-C interface application. The proposed adaptive linear pole–zero tracking compensation can linearly compensate for the changes in the back-sink current, thereby adaptively canceling the pole–zero changes caused by the current changes. The simulation results show that the phase margin remains greater than 60 ◦ . Meanwhile, the loop bandwidth changes between 45 kHz and 135 kHz, when the current increases from 0 A to 1 A, ensuring excellent loop stability. The high-stability regulation circuit is realized in a standard 180 nm CMOS process with an area of 0.4 mm × 0.6 mm. The chip regulates an output voltage from 4.5 V to 5.5 V with 1 A current capacity and 100 mV maximum dropout voltage with the help of the adaptive linear pole–zero tracking compensation.


Introduction
The USB Type-C interface is significantly advantageous over the conventional data transmission interfaces and has been widely used in various portable electronic devices such as notebooks, desktops and smartphones [1]. The current-limiting switch between the Type-C interface and peripherals is employed to prevent overcurrent, short-circuit or even reverse-current, thus effectively protecting the safety of the host and the device. Figure 1 shows the schematic structure of a typical USB interface protection circuit. Two NMOS switches M SW1 and M SW2 are connected in series, and the substrate can be prevented from being turned on when the switch is turned off. In practice, M SW1 is used for the current limit protection while M SW2 is employed to protect against the reverse current. The voltage stabilization loop used to control M SW2 is similar to the LDO structure, but the difference from the traditional LDO is that the dropout voltage of the loop needs to be reduced (<100 mV) to avoid the power loss of the switch itself [2][3][4][5][6][7][8][9][10][11]. Under such a low dropout voltage, the working state of the M SW2 transistor is approximately in the linear region. It should be noted that according to the protocol requirements of USB3.X, the current flowing through the switch varies from 0 A to several amperes corresponding to the change of the load on the output terminal of the switch, which poses difficulties for the compensation of the loop stability [1].
Due to the large capacitance (microfarad-level) connected to the switch output as the stabilized capacitor for power supply measurement, the output pole appears at a very low frequency when the load current is small. A large capacitance is thus required for conventional Miller compensation, which, however, is unacceptable for a chip application with limited floor space. On the other hand, the traditional equivalent series resistor (ESR) compensation has the problem of zero drift with limited compensation stability [2]. Dynamic pole-zero tracking frequency compensation can compensate the first nondominant pole in multistage op-amps by dynamically generating zeros [3,4]. However, in the conventional pole-zero compensation method, although the tracking MOS transistor works in the saturation region, the zero resistance works in the linear region leading to a continuous change in the impedance, which can further result in a large variation in the relative position of the pole-zero in the full current range. This can have a significant influence on the variation range of the bandwidth, making it unsuitable for the application of a current limiting switch system. In this work, an adaptive linear pole-zero tracking compensation method is proposed by introducing a current detection loop and a constant bandwidth tracking loop. While the loop stability is not affected by the change of the load current, the gain bandwidth of the entire loop is constant at a certain level.  Due to the large capacitance (microfarad-level) connected to the switch output as the stabilized capacitor for power supply measurement, the output pole appears at a very low frequency when the load current is small. A large capacitance is thus required for conventional Miller compensation, which, however, is unacceptable for a chip application with limited floor space. On the other hand, the traditional equivalent series resistor (ESR) compensation has the problem of zero drift with limited compensation stability [2]. Dynamic pole-zero tracking frequency compensation can compensate the first nondominant pole in multistage op-amps by dynamically generating zeros [3,4]. However, in the conventional pole-zero compensation method, although the tracking MOS transistor works in the saturation region, the zero resistance works in the linear region leading to a continuous change in the impedance, which can further result in a large variation in the relative position of the pole-zero in the full current range. This can have a significant influence on the variation range of the bandwidth, making it unsuitable for the application of a current limiting switch system. In this work, an adaptive linear pole-zero tracking compensation method is proposed by introducing a current detection loop and a constant bandwidth tracking loop. While the loop stability is not affected by the change of the load current, the gain bandwidth of the entire loop is constant at a certain level. Figure 2 shows the schematic structure of the circuit design with traditional polezero tracking compensation. The regulator loop is composed of a two-stage amplifier, pole-zero tracking voltage generator and output stage.

Traditional Regulation Circuit with Pole-Zero Tracking Compensation
The pole-zero (PZ) dynamic compensation is realized by the output current sensor, PZ tracking voltage generator, MRZ and CC circuits. The current sensor mirrors and tracks the output current and realizes 1/K current scaling by adjusting the mirror ratio of MSWB and MSW2. The drain voltages of MSWB and MSW2 are equal through the function of OP1, achieving accurate copying of the current, which is subsequently output through the current mirror composed of MN3 and MN4. The current of MP5 is the output of MP2 and MP3 current mirrors. As a result, the VGS voltage of MP5 is proportional to the output current. In addition, MRZ and CC form a zero, and the gate-source voltages of MRZ and MP5 are the same, which makes the on-resistance of MRZ proportional to the output current. When the output current decreases, the output pole (Po) and the VGS voltage of MP5 decrease. With a larger impedance of MRZ, the frequency of the zero formed by MRZ and CC is lowered, realizing the tracking compensation of the output pole. The compensated voltage stabilizing loop has only one dominant pole at the output of EA1, which makes the entire loop stable.  Figure 2 shows the schematic structure of the circuit design with traditional pole-zero tracking compensation. The regulator loop is composed of a two-stage amplifier, pole-zero tracking voltage generator and output stage. From the above analysis, there exist two dominant poles located at VOUT and EA1 in the traditional circuit with varying load current. In addition, the Po at the VOUT terminal will change with the varying load current. For example, with a small output current, RL >> RMSW2 (meanwhile, RMSW1 << RMSW2), and the output impedance at the VOUT terminal is:

Traditional Regulation Circuit with Pole-Zero Tracking Compensation
The VGS voltage of MP5 is calculated as: The pole-zero (PZ) dynamic compensation is realized by the output current sensor, PZ tracking voltage generator, M RZ and C C circuits. The current sensor mirrors and tracks the output current and realizes 1/K current scaling by adjusting the mirror ratio of M SWB and M SW2 . The drain voltages of M SWB and M SW2 are equal through the function of OP1, achieving accurate copying of the current, which is subsequently output through the current mirror composed of M N3 and M N4 . The current of M P5 is the output of M P2 and M P3 current mirrors. As a result, the V GS voltage of M P5 is proportional to the output current. In addition, M RZ and C C form a zero, and the gate-source voltages of M RZ and M P5 are the same, which makes the on-resistance of M RZ proportional to the output current. When the output current decreases, the output pole (P o ) and the V GS voltage of M P5 decrease. With a larger impedance of M RZ , the frequency of the zero formed by M RZ and C C is lowered, realizing the tracking compensation of the output pole. The compensated voltage stabilizing loop has only one dominant pole at the output of EA1, which makes the entire loop stable.
From the above analysis, there exist two dominant poles located at V OUT and EA1 in the traditional circuit with varying load current. In addition, the P o at the V OUT terminal will change with the varying load current. For example, with a small output current, R L >> R MSW2 (meanwhile, R MSW1 << R MSW2 ), and the output impedance at the V OUT terminal is: The V GS voltage of M P5 is calculated as: Since the V GS values of M RZ and M P5 are the same, and M RZ is operating in the linear region, the on-resistance of M RZ is: Thus, the zero formed by M RZ and C C can be expressed as: The K in Equations (3)-(5) represents the ratio of sensor current, and W MP5 and L MP5 are the channel width and length of the M P5 transistor. The frequency compensation can be achieved by using Z C to cancel out P o . However, due to the different dependence of P o (Equation (2)) and Z C (Equation (5)) on R L , Z C cannot track the change of P o well when R L varies in a large range. This can further result in a large change in bandwidth as well as a deterioration in stability.

Proposed Regulation Circuit with Adaptive Linear Pole-Zero Tracking Compensation
To solve the above issue, we propose a regulation circuit with an adaptive linear pole-zero tracking compensation, which is schematically illustrated in Figure 3. The entire circuit includes a two-stage amplifier (AMP STG1 and AMP STG2), buffer stage, output current sensor, adaptive linear PZ tracking voltage generator, output power transistor and load resistor and capacitor. Among these components, the AMP STG1 provides gain and the AMP STG2 provides low output impedance to push the output pole farther from the origin. The output power transistor provides a large current, and the output current sensor can achieve accurate reproduction of the output current. The adaptive linear PZ tracking voltage generator is used to perform the compensation of the output pole making the unity-gain bandwidth (GBW) of the feedback system constant while ensuring stability. current sensor, adaptive linear PZ tracking voltage generator, output power transistor and load resistor and capacitor. Among these components, the AMP STG1 provides gain and the AMP STG2 provides low output impedance to push the output pole farther from the origin. The output power transistor provides a large current, and the output current sensor can achieve accurate reproduction of the output current. The adaptive linear PZ tracking voltage generator is used to perform the compensation of the output pole making the unity-gain bandwidth (GBW) of the feedback system constant while ensuring stability.  The four poles can be expressed as:  Figure 4 shows the pole−zero distribution of the proposed regulation circuit. There are four poles (P 1~P3 , P o ) and a zero (Z C ) in the circuit illustrated in Figure 3. current sensor, adaptive linear PZ tracking voltage generator, output power transistor and load resistor and capacitor. Among these components, the AMP STG1 provides gain and the AMP STG2 provides low output impedance to push the output pole farther from the origin. The output power transistor provides a large current, and the output current sensor can achieve accurate reproduction of the output current. The adaptive linear PZ tracking voltage generator is used to perform the compensation of the output pole making the unity-gain bandwidth (GBW) of the feedback system constant while ensuring stability.  The four poles can be expressed as:  The four poles can be expressed as:  From the circuit shown in Figure 5, MN5 is in the linear region, and the drain-source current of MN5 is: There is a fixed 1/K relationship between the drain-source current of MN5 and the output current due to the current mirror: o DSN5 From Equations (10) and (11), the VGS of MN5 transistor is: Considering the fact that the VGS values of MRZ and MN5 are the same, and both work in the linear region, the on-resistance of MRZ can be obtained by: From Equations (11)-(14), we can obtain: From the circuit shown in Figure 5, M N5 is in the linear region, and the drain-source current of M N5 is: There is a fixed 1/K relationship between the drain-source current of M N5 and the output current due to the current mirror: From Equations (10) and (11), the V GS of M N5 transistor is: Considering the fact that the V GS values of M RZ and M N5 are the same, and both work in the linear region, the on-resistance of M RZ can be obtained by: From Equations (11)-(14), we can obtain: The corresponding zero can be obtained from Equation (15): Compared to the traditional circuit design, in our proposed circuit design, both P o and Z C are in a first-order linear relationship to R L , as indicated by Equations (9) and (16), respectively, realizing the linear tracking and compensation of Z C with a different loading current.

Simulation and Experimental Test Results
The positions of the poles are the outputs of each stage with P 1 as the dominant pole and P o as the first nondominant pole. P 2 and P 3 are far away from P 1 due to the small equivalent input capacitance and equivalent output impedance, and do not affect the stability of the loop. Then, we can plot the location of the poles of the proposed regulation circuit as shown in Figure 6. From Equations (9) and (16), it can be seen that both Z C and P o have a first-order linear proportional relationship with I O . When the load changes, Z C can be used to track and compensate for the change of P o linearly. Thus, we can obtain a high-stability loop in a wide current range.
Compared to the traditional circuit design, in our proposed circuit design, both Po and ZC are in a first-order linear relationship to RL, as indicated by Equations (9) and (16), respectively, realizing the linear tracking and compensation of ZC with a different loading current.

Simulation and Experimental Test Results
The positions of the poles are the outputs of each stage with P1 as the dominant pole and Po as the first nondominant pole. P2 and P3 are far away from P1 due to the small equivalent input capacitance and equivalent output impedance, and do not affect the stability of the loop. Then, we can plot the location of the poles of the proposed regulation circuit as shown in Figure 6. From Equations (9) and (16), it can be seen that both ZC and Po have a first-order linear proportional relationship with IO. When the load changes, ZC can be used to track and compensate for the change of Po linearly. Thus, we can obtain a high-stability loop in a wide current range.     The corresponding zero can be obtained from Equation (15): Compared to the traditional circuit design, in our proposed circuit design, both Po and ZC are in a first-order linear relationship to RL, as indicated by Equations (9) and (16), respectively, realizing the linear tracking and compensation of ZC with a different loading current.

Simulation and Experimental Test Results
The positions of the poles are the outputs of each stage with P1 as the dominant pole and Po as the first nondominant pole. P2 and P3 are far away from P1 due to the small equivalent input capacitance and equivalent output impedance, and do not affect the stability of the loop. Then, we can plot the location of the poles of the proposed regulation circuit as shown in Figure 6. From Equations (9) and (16), it can be seen that both ZC and Po have a first-order linear proportional relationship with IO. When the load changes, ZC can be used to track and compensate for the change of Po linearly. Thus, we can obtain a high-stability loop in a wide current range.    The proposed high−stability regulation circuit was designed in a 180 nm CMOS process. The chip micrograph is shown in Figure 8, and the die size is 400 × 600 µm 2 .
Electronics 2022, 11, x FOR PEER REVIEW 7 of 9 The proposed high−stability regulation circuit was designed in a 180 nm CMOS process. The chip micrograph is shown in Figure 8, and the die size is 400 × 600 μm 2 .      Finally, we compared the performance that can be achieved by the currently reported compensation methods of voltage stabilization loops. The comparison is listed in Table 1 in terms of process, dropout voltage, output capacitor and the maximum output current I o (max). From the comparison result, it is found that within the full load range, the bandwidth change of the regulation circuit proposed in this paper is the smallest, the stability of the system is better and a smaller drop voltage can be achieved.

Conclusions
In summary, an adaptive linear pole-zero tracking compensation was proposed in this paper, by changing the tracking transistor from the traditional saturation region to the triode region for a good linear match to the resistance of the zero-adjusting resistor. The frequency change of the zero and the first nondominant pole was linearly consistent. From the simulation and test results, the bandwidth change range was very small within the full load range, due to the high linearity of the zero and the first nondominant pole with the load change. Further delicate circuit design and engineering will shed more light on this issue towards advanced USB Type-C interface applications.