A Nonisolated Transformerless High-Gain DC–DC Converter for Renewable Energy Applications

: Dc–dc converters with a high gain, continuous input current, and common ground are usually employed in renewable energy applications to boost the generated output voltage of renewable energy sources. In this paper, a high-gain dc–dc converter comprising a voltage multiplier cell (VMC) and a common ground with continuous input current and low-voltage stress across semiconductor devices is proposed. The converter produces a voltage gain of about ten times compared to the conventional boost converter at a duty ratio of 50% by utilizing switched capacitors and switched inductors. The simultaneous operation of both the switches with the same gate pulse offers easy and simple control of the proposed converter with a wide range of operations. The boundary operation of the converter is analyzed and presented in both modes, i.e., continuous conduction mode (CCM) and discontinuous conduction mode (DCM). Ideal and nonideal analysis of the converter is carried out by integrating real models of passive elements and semiconductor devices by using PLECS software. The simulation is also used to calculate the losses and hence the working efﬁciency of the converter. The performance of the converter analyzed in the steady state is compared with various similar converters based on the voltage boosting capability and switching stresses. A hardware prototype is also developed to conﬁrm and validate the theoretical analysis and simulation of the proposed converter.


Introduction
High-gain boost converters have gained prominence in recent times due to their suitability in various applications such as solar PV systems [1], switch-mode power supplies (SMPS), electric vehicles, and aerospace applications.A conventional boost converter has certain shortcomings such as discontinuous input and output currents and increased losses in the system at higher duty cycle operations, which leads to its limited solar PV and fuel cell applications.The traditional quadratic boost converter (TQBC) shown in Figure 1 uses a single switch of high voltage and a current rating which results in low efficiency at higher duty ratios.In the literature, many high-gain dc-dc converters are being published [2,3] to overcome the limitations of the conventional boost and quadratic boost converter.The use of coupled inductors, Z-source converters, switched inductors, switched capacitors, and voltage multiplier cells (VMCs) are popular methods to increase the gain of high-gain dc-dc converters.Isolated step-up quadratic boost converters are implemented in [4,5] with coupled inductors that have a high-voltage gain and low switching stress.The converter in [4] has a voltage doubler cell and produces a higher gain as compared to [5].Soft switched dc-dc converters eliminate the switching losses [6,7] however their hardware implementation and operation are difficult.Various Z-source converters [8][9][10][11] have been proposed in the literature that contains a unique impedance network.In [10], a quasi-Z source converter is implemented using a switched capacitor and switched inductor configuration for achieving a high-voltage gain along with low-voltage stress on capacitors and a continuous input current, but the topology lacks a common ground.In [11], the hybrid quasi-Z source converter is proposed by a combination of traditional Z source converters.
A set of nonisolated switched inductors and switched capacitor converters are discussed in [12][13][14][15][16][17].The converter proposed in [12] has a switched capacitor and quadratic gain with a common ground and low input current ripples.The converter is lightweight due to the absence of a transformer and can be utilized for solar PV applications.In [13], the authors have proposed a switched inductor boost converter that has low current stress in inductors but suffers from a low-voltage gain and high-switch stresses.In [14], the twin duty cycle and three switches configuration add to the complexity of the circuit [14,15] as compared to [16] which has two switches following the same duty cycle.A non-isolated converter is proposed in [17] and has a simple design as compared to [15,16] along with a high gain and reduced voltage stresses on switches, diodes, and capacitors.It has a symmetrical structure that helps to ease the choice of the components and its design.In [18], a single switch nonisolated topology is implemented with low switch stress.In [19], the transformerless converter shown in Figure 2 is proposed.It consists of a VMC, with a gain of six times that of a conventional boost converter with a single switch and two inductors.The converter shown in Figure 2 has a single switch but the converter lacks a common ground.Moreover, the input current pulsates.The converter proposed in this paper has a common ground and continuous input current.Isolated step-up quadratic boost converters are implemented in [4,5] with coupled inductors that have a high-voltage gain and low switching stress.The converter in [4] has a voltage doubler cell and produces a higher gain as compared to [5].Soft switched dc-dc converters eliminate the switching losses [6,7] however their hardware implementation and operation are difficult.Various Z-source converters [8][9][10][11] have been proposed in the literature that contains a unique impedance network.In [10], a quasi-Z source converter is implemented using a switched capacitor and switched inductor configuration for achieving a high-voltage gain along with low-voltage stress on capacitors and a continuous input current, but the topology lacks a common ground.In [11], the hybrid quasi-Z source converter is proposed by a combination of traditional Z source converters.
A set of nonisolated switched inductors and switched capacitor converters are discussed in [12][13][14][15][16][17].The converter proposed in [12] has a switched capacitor and quadratic gain with a common ground and low input current ripples.The converter is lightweight due to the absence of a transformer and can be utilized for solar PV applications.In [13], the authors have proposed a switched inductor boost converter that has low current stress in inductors but suffers from a low-voltage gain and high-switch stresses.In [14], the twin duty cycle and three switches configuration add to the complexity of the circuit [14,15] as compared to [16] which has two switches following the same duty cycle.A non-isolated converter is proposed in [17] and has a simple design as compared to [15,16] along with a high gain and reduced voltage stresses on switches, diodes, and capacitors.It has a symmetrical structure that helps to ease the choice of the components and its design.In [18], a single switch nonisolated topology is implemented with low switch stress.In [19], the transformerless converter shown in Figure 2 is proposed.It consists of a VMC, with a gain of six times that of a conventional boost converter with a single switch and two inductors.The converter shown in Figure 2 has a single switch but the converter lacks a common ground.Moreover, the input current pulsates.The converter proposed in this paper has a common ground and continuous input current.
Isolated step-up quadratic boost converters are implemented in [4,5] with coupled inductors that have a high-voltage gain and low switching stress.The converter in [4] has a voltage doubler cell and produces a higher gain as compared to [5].Soft switched dc-dc converters eliminate the switching losses [6,7] however their hardware implementation and operation are difficult.Various Z-source converters [8][9][10][11] have been proposed in the literature that contains a unique impedance network.In [10], a quasi-Z source converter is implemented using a switched capacitor and switched inductor configuration for achieving a high-voltage gain along with low-voltage stress on capacitors and a continuous input current, but the topology lacks a common ground.In [11], the hybrid quasi-Z source converter is proposed by a combination of traditional Z source converters.
A set of nonisolated switched inductors and switched capacitor converters are discussed in [12][13][14][15][16][17].The converter proposed in [12] has a switched capacitor and quadratic gain with a common ground and low input current ripples.The converter is lightweight due to the absence of a transformer and can be utilized for solar PV applications.In [13], the authors have proposed a switched inductor boost converter that has low current stress in inductors but suffers from a low-voltage gain and high-switch stresses.In [14], the twin duty cycle and three switches configuration add to the complexity of the circuit [14,15] as compared to [16] which has two switches following the same duty cycle.A non-isolated converter is proposed in [17] and has a simple design as compared to [15,16] along with a high gain and reduced voltage stresses on switches, diodes, and capacitors.It has a symmetrical structure that helps to ease the choice of the components and its design.In [18], a single switch nonisolated topology is implemented with low switch stress.In [19], the transformerless converter shown in Figure 2 is proposed.It consists of a VMC, with a gain of six times that of a conventional boost converter with a single switch and two inductors.The converter shown in Figure 2 has a single switch but the converter lacks a common ground.Moreover, the input current pulsates.The converter proposed in this paper has a common ground and continuous input current.In [20], a modified Ćuk converter is proposed with switched capacitors.The authors have proposed a buck-boost converter in [21] for renewable energy applications with continuous input.The converter exhibits high efficiency above 95% around the 56.5% duty cycle; however, the switching stress also increases drastically.In [22], an extendable boost converter employing active-passive inductor cells (APIC) is proposed.The efficiency and voltage gain at a lower duty ratio decrease drastically as the number of APICs is increased.The authors in [23] have introduced an extended boost converter by implanting a cell consisting of switched capacitors and inductors between a conventional boost converter.The converter has the same voltage gain for the complementary duty ratio, which is nearly constant, while the duty ratio is varied from 30% to 70%.A quadratic boost converter is proposed in [24].The gain of the converter is lower as compared to similar topologies.A variety of quadratic boost converters are introduced in [25-30], each with its set of advantages and disadvantages.The authors in [25] have proposed a simple quadratic boost converter, but it lacks a common ground, whereas a modified quadratic boost converter in [26] is implemented, resulting in twice the gain as compared to the quadratic boost converter.The converter proposed in [27] has a common ground but a lower gain as compared to the topology proposed in [28], which lacks a common ground.The quadratic converter proposed by the authors in [29] has more components as compared to [30] but has a higher gain at the cost of a decreased efficiency due to increased heat losses.
In this paper, a new transformerless high-gain dc-dc converter is implemented that employs a VMC to boost the voltage.The attractive features of the proposed topology are

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The converter achieves a high gain of 10 times the conventional boost and 5 times that of the quadratic boost converter at a 50% duty ratio.

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The converter has low voltage stress of 5% of the output voltage across switch S 1 .

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The converter uses the same gate signal for both switches, which leads to its easy operation.

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The topology has a continuous input current and a common ground, making it feasible for PV applications.
The paper discusses the structure of the proposed topology and its detailed ideal analysis in Section 2 followed by the nonideal analysis in Section 3. The comparison of the proposed topology with various similar converters is carried out in Section 4. The simulation and the experimental results are presented in Section 5 along with the efficiency of the proposed converter at different input voltages and power.

Structure of Proposed High-Gain DC-DC Converter Topology
The components of the proposed nonisolated dc-dc converter topology depicted in Figure 3 consist of a fixed DC input voltage source V in ; two switches (MOSFETs) S 1 and S 2 ; three inductors L 1 , L 2 , and L 3 ; seven diodes D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , and and C O ; and a resistive load R O with an output voltage of V O .The circuit also consists of a VMC with elements L 2 , L 3 , C 4 , D 5 , and D 6 .The nonisolated converter does not include a high-frequency transformer and hence contributes to its low bulkiness, size, and cost reduction.This further aids in easier control of the topology as compared to isolated converters.

Operation of the Converter in Continuous Conduction Mode (CCM)
The proposed converter operates in two modes in each cycle while working in the CCM state.Each mode is discussed in detail by providing the voltage and current equations of each component in both modes.
Mode 1 (0 ≤ t ≤ t O ): In mode 1, both switches S 1 and S 2 are turned ON simultaneously, as shown in Figure 4, by applying the appropriate gate pulse.In this mode, diodes

Operation of the Converter in Continuous Conduction Mode (CCM)
The proposed converter operates in two modes in each cycle while working in the CCM state.Each mode is discussed in detail by providing the voltage and current equations of each component in both modes.
Mode 1 ( ≤  ≤   ): In mode 1, both switches  and  are turned ON simultaneously, as shown in Figure 4, by applying the appropriate gate pulse.In this mode, diodes  ,  ,  , and  are forward-biased, whereas the other diodes  ,  , and  are reverse-biased.The inductor  is charged through the input voltage source and the inductors  and  are charged through the capacitor  .The capacitor  is discharged, while the capacitor  is charged in this mode.The output capacitor  discharges and feeds the load to maintain a constant voltage  across the output load resistor.The voltage and current equations across the inductors and capacitors during mode 1 when both switches are ON can be expressed as (1) and (2), respectively.

Operation of the Converter in Continuous Conduction Mode (CCM)
The proposed converter operates in two modes in each cycle while working in the CCM state.Each mode is discussed in detail by providing the voltage and current equations of each component in both modes.
Mode 1 ( ≤  ≤   ): In mode 1, both switches  and  are turned ON simultaneously, as shown in Figure 4, by applying the appropriate gate pulse.In this mode, diodes  ,  ,  , and  are forward-biased, whereas the other diodes  ,  , and  are reverse-biased.The inductor  is charged through the input voltage source and the inductors  and  are charged through the capacitor  .The capacitor  is discharged, while the capacitor  is charged in this mode.The output capacitor  discharges and feeds the load to maintain a constant voltage  across the output load resistor.The voltage and current equations across the inductors and capacitors during mode 1 when both switches are ON can be expressed as (1) and (2), respectively.The voltage and current equations across the inductors and capacitors during mode 1 when both switches are ON can be expressed as (1) and (2), respectively.
Mode 2 (t O ≤ t ≤ T): In mode 2, both switches S 1 and S 2 are turned OFF simultane- ously.In Figure 5, it can be seen that diodes D 1 , D 3 and D O are forward-biased, whereas the remainder of diodes D 2 , D 4 , D 5 and D 6 are reverse-biased.In this mode capacitor, C 3 is charged through capacitors C 1 and C 2 .Inductors L 2 and L 3 along with capacitor C 4 transfer power to load and charge, and capacitor C O maintains a constant voltage V O about the load.The voltage and current equations across the inductors and capacitors during Mode 2 when both switches are OFF can be expressed as ( 3) and (4), respectively.The voltages across the capacitors and inductors (shown in Figure 6) are represented in (9) and can be easily evaluated by applying KVL in respective loops as, The ideal voltage gain (M) can be calculated by using the volt-sec balance principle in an inductor in CCM operation as per the following relation given in ( 5), Applying the volt-sec principle in the inductor Applying the volt-sec balance principle to Equating Equations ( 6) and ( 7) where 'D' denotes the duty cycle for switches S 1 and S 2 .
The voltages across the capacitors and inductors (shown in Figure 6) are represented in (9) and can be easily evaluated by applying KVL in respective loops as, The voltages across the capacitors and inductors (shown in Figure 6) are represented in (9) and can be easily evaluated by applying KVL in respective loops as,

Calculation of Voltage Stress
The voltage stress across the switches as shown in Figure 7 and the diodes shown in Figures 8 and 9 are evaluated at the instance when the switches are not conducting and are in the OFF state.The voltage stress particularly refers to the peak inverse voltage across the switch.

Calculation of Voltage Stress
The voltage stress across the switches as shown in Figure 7 and the diodes shown in Figures 8 and 9 are evaluated at the instance when the switches are not conducting and are in the OFF state.The voltage stress particularly refers to the peak inverse voltage across the switch.The voltage stresses across the switches in the OFF state are given as, The voltage stress across different diodes when they are not conducting can be expressed as in (11): Electronics 2022, 11, 2014 8 of 26

Calculation of Average and RMS Currents
The average currents through the capacitors and switches can be easily determined by applying the current-sec balance principle in capacitors.
The average switch currents (in Figure 10) are given as,   The average inductor currents (in Figure 11) are given as, The RMS values of the switch currents are given as, Electronics 2022, 11, 2014   The RMS values of the various currents through the components are given as,

Design of Inductors and Capacitors
The ripple current in the inductor L 1 can be found as in (17) and rearranged to obtain the critical value of the inductor for CCM operation.
The ripple current and the critical value of the inductors L 2 and L 3 can be found as The peak-to-peak ripple voltages across the capacitors can be given as

Operation of Converter in Discontinuous Conduction Mode (DCM)
The proposed converter can also operate in DCM.This mode consists of three different sub-modes of operation, as depicted in Figure 12.Applying volt-sec balance in inductor L1, we obtain, Applying volt-sec in L2, we obtain, From equating (20) and ( 21), we obtain, Rearranging Equation ( 22), we obtain, Under DCM analysis for inductor  , we have, For DCM operation, From ( 24) and ( 25) we obtain,  The inductors are charged in Mode 1 (from t = 0 to t = DT) and are discharged in Mode 2 (from t = DT to t = D'T).Hence, by applying volt-sec balance across the inductors, we obtain the voltage gain in DCM.
Applying volt-sec balance in inductor L 1 , we obtain, Applying volt-sec in L 2 , we obtain, From Equating (20) and ( 21), we obtain, Rearranging Equation (22), we obtain, Under DCM analysis for inductor L 2 , we have, For DCM operation, From ( 24) and ( 25) we obtain, where τ is the time constant represented as and f s is the switching frequency of the switches.

Converter Operation at Boundary Conditions
The boundary condition represents the critical conduction state of the converter on the boundary of DCM and CCM.The relation for the boundary condition can be easily formulated by equating the voltage gains in the CCM and DCM operations, respectively.The boundary condition is determined by the boundary-normalized time constant of the inductor L 2 , is as shown in Figure 13.The variation in the time constant of the inductor as a function of the duty cycle is represented as Electronics 2022, 11, x FOR PEER REVIEW 12 of 28 where  is the time constant represented as and  is the switching frequency of the switches.Equating ( 25) and ( 26), we obtain, Let  = τ ; then,

Converter Operation at Boundary Conditions
The boundary condition represents the critical conduction state of the converter on the boundary of DCM and CCM.The relation for the boundary condition can be easily formulated by equating the voltage gains in the CCM and DCM operations, respectively.The boundary condition is determined by the boundary-normalized time constant of the inductor  , is as shown in Figure 13.The variation in the time constant of the inductor as a function of the duty cycle is represented as The maximum value of  is 0.00516 obtained at D = 0.55.The converter operates in DCM mode for a time constant less than  and in CCM mode for a time constant more than  .

Nonideal Analysis
The nonideal analysis of the converter accounts for the power loss analysis of the circuit.Thus far, only the ideal lossless analysis of the converter is being considered in the paper, ignoring the parasitic series resistances of the inductors, equivalent series resistance (ESR) of the capacitors, barrier potential voltage and leakage resistances of the diode, and the ON-state resistance of the switches (MOSFET), as shown in Figure 14.The loss analysis is proceeded by the inclusion of the above-mentioned parameters in the ideal The maximum value of K ec is 0.00516 obtained at D = 0.55.The converter operates in DCM mode for a time constant less than K ec and in CCM mode for a time constant more than K ec .

Nonideal Analysis
The nonideal analysis of the converter accounts for the power loss analysis of the circuit.Thus far, only the ideal lossless analysis of the converter is being considered in the paper, ignoring the parasitic series resistances of the inductors, equivalent series resistance (ESR) of the capacitors, barrier potential voltage and leakage resistances of the diode, and the ON-state resistance of the switches (MOSFET), as shown in Figure 14.The loss analysis is proceeded by the inclusion of the above-mentioned parameters in the ideal circuit of the proposed topology.The nonidealities of the elements tend to decrease the voltage gain of the converter and also result in an increase in power losses.The total power loss across all the elements is given as,

Calculation of Losses across Switches
The losses across switches can be either conduction losses that are encountered when the switch is ON and current flows through it, or they may be switching losses that are encountered when the switch is in the transition from the ON state to OFF state or viceversa.
For the conduction loss calculations, the resistance of both switches is assumed to be the same, i.e.,  =  =  .
For the calculation of switching losses for a switch operating at a switching frequency of   , the rise time (  ) and fall time (  ) of the gate pulses are considered.Then, the switching losses can be given as,

Calculation of Losses across Switches
The losses across switches can be either conduction losses that are encountered when the switch is ON and current flows through it, or they may be switching losses that are encountered when the switch is in the transition from the ON state to OFF state or vice-versa.
For the conduction loss calculations, the resistance of both switches is assumed to be the same, i.e., r S 1 = r S 2 = r s .
For the calculation of switching losses for a switch operating at a switching frequency of f s , the rise time (t r ) and fall time (t f ) of the gate pulses are considered.Then, the switching losses can be given as,

Calculation of Losses across Diodes
For the calculation purpose, the cut-in voltage and resistance of all diodes are assumed to be the same, i.e., The losses across different diodes are given as:

Calculation of Losses across Capacitors
For the calculation of conduction loss in capacitors, the parasitic resistances of the capacitors r C1 , r C2 , r C3 , r C4 , and r C5 are assumed to be equal, while the resistance of the capacitor C O is assumed to be r CO

Calculation of Losses across Inductors
The loss calculations for inductors are carried out by ignoring the ripple in the inductor current through the leakage resistances r L1 , r L2 , and r L3 .Inductors L 2 and L 3 have the same design values; hence, their parasitic resistances are assumed to be equal.

Calculation of Efficiency of the Converter in Nonideal Mode
The efficiency of the converter is given as the ratio of the output power transferred to the total input power fed to the circuit, which can be represented as the sum of the output power and the total losses in the converter.The efficiency (η) is given as where K is a constant given simplified as, After substituting the value of K obtained in (45) in (44), we obtain, where,

Calculation of Nonideal Voltage Gain
For the derivation of nonideal voltage gain, all the lossy components of the elements such as the ON-state resistance of diodes and switches, ESRs of the inductor, and capacitor are considered for the analysis.Thus far, the input and output powers are equal due to lossless analysis, whereas, considering the above assumptions, the modified relation between the input and output power can be expressed as: Input Power = Output Power + Losses across elements

Variation in Nonideal Voltage Gain
The nonideal gain (M actual ) of the proposed converter is derived as, From the voltage gain comparison of ideal and nonideal voltage gains of the proposed topology in Figure 15, it is observed that both gains have similar values up to the duty ratio of 0.4, and then the nonideal gain increases until D = 0.7 but deviate from the ideal characteristics.Thereafter, it gradually decreases to zero at the unity duty ratio.

Variation in Nonideal Voltage Gain
The nonideal gain ( ) of the proposed converter is derived as, From the voltage gain comparison of ideal and nonideal voltage gains of the proposed topology in Figure 15, it is observed that both gains have similar values up to the duty ratio of 0.4, and then the nonideal gain increases until D = 0.7 but deviate from the ideal characteristics.Thereafter, it gradually decreases to zero at the unity duty ratio.
The voltage gain of the converter can be affected by the parasitic resistances of different elements of the converter such as the parasitic resistance of inductors, capacitors, and switches.As the parasitic resistances of different elements increase, the voltage gain of the converter decreases gradually.The voltage gain of the converter can be affected by the parasitic resistances of different elements of the converter such as the parasitic resistance of inductors, capacitors, and switches.As the parasitic resistances of different elements increase, the voltage gain of the converter decreases gradually.
From Figure 16, it can be observed that, when the parasitic resistance of the switch is increased while other elements are kept ideal, the voltage gain of the converter decreases.For the parasitic resistance of 0.2% of the load resistance, the maximum gain is at the duty ratio of 0.7 with a gain of 24.18, while it decreases to 15.84 and 11.77 for 4% and 6% of the parasitic resistance, respectively, at D = 0.7.
From Figure 17, it can be observed that, when the parasitic resistance of the inductor is increased while other elements are kept ideal, the voltage gain of the converter decreases.For a parasitic resistance of 0.2% of the load resistance, the maximum gain is at the duty ratio of 0.75 with a gain close to 34, while it decreases to 24.88 and 19.80 for 4% and 6% of the parasitic resistance, respectively, at D = 0.7.
From Figure 18, it can be observed that, when the parasitic resistance of the capacitor is increased while other elements are kept ideal, the voltage gain of the converter decreases.For the parasitic resistance of 0.2% of the load resistance, the maximum gain is at the duty ratio of 0.8 with a gain of 63, while it decreases to around 41 and 21 for 4% and 6% of the parasitic resistance, respectively, at a near-duty ratio of 0.8.
From Figure 16, it can be observed that, when the parasitic resistance of the switch is increased while other elements are kept ideal, the voltage gain of the converter decreases.For the parasitic resistance of 0.2% of the load resistance, the maximum gain is at the duty ratio of 0.7 with a gain of 24.18, while it decreases to 15.84 and 11.77 for 4% and 6% of the parasitic resistance, respectively, at D = 0.7.From Figure 17, it can be observed that, when the parasitic resistance of the inductor is increased while other elements are kept ideal, the voltage gain of the converter decreases.For a parasitic resistance of 0.2% of the load resistance, the maximum gain is at the duty ratio of 0.75 with a gain close to 34, while it decreases to 24.88 and 19.80 for 4% and 6% of the parasitic resistance, respectively, at D = 0.7.From Figure 18, it can be observed that, when the parasitic resistance of the capacitor is increased while other elements are kept ideal, the voltage gain of the converter decreases.For the parasitic resistance of 0.2% of the load resistance, the maximum gain is at From Figure 16, it can be observed that, when the parasitic resistance of the switch is increased while other elements are kept ideal, the voltage gain of the converter decreases.For the parasitic resistance of 0.2% of the load resistance, the maximum gain is at the duty ratio of 0.7 with a gain of 24.18, while it decreases to 15.84 and 11.77 for 4% and 6% of the parasitic resistance, respectively, at D = 0.7.From Figure 17, it can be observed that, when the parasitic resistance of the inductor is increased while other elements are kept ideal, the voltage gain of the converter decreases.For a parasitic resistance of 0.2% of the load resistance, the maximum gain is at the duty ratio of 0.75 with a gain close to 34, while it decreases to 24.88 and 19.80 for 4% and 6% of the parasitic resistance, respectively, at D = 0.7.From Figure 18, it can be observed that, when the parasitic resistance of the capacitor is increased while other elements are kept ideal, the voltage gain of the converter decreases.For the parasitic resistance of 0.2% of the load resistance, the maximum gain is at the duty ratio of 0.8 with a gain of 63, while it decreases to around 41 and 21 for 4% and 6% of the parasitic resistance, respectively, at a near-duty ratio of 0.8.

Comparison of the Proposed Topology
In this section, a comparison between the proposed topology with two traditional topologies and recent topologies is discussed.The topologies are compared based on their voltage gain (MCCM), number of inductors (NL), number of capacitors (NC) and number of

Comparison of the Proposed Topology
In this section, a comparison between the proposed topology with two traditional topologies and recent topologies is discussed.The topologies are compared based on their voltage gain (M CCM ), number of inductors (N L ), number of capacitors (N C ) and number of diodes (N D ) in the converter.The voltage stress appearing across the switches (V si /V in ) is also compared along with the availability of common ground.
For the comparison of the topologies, the graph between the ideal voltage gain and the duty cycle is plotted in Figure 19a.Figure 19b depicts the comparison of the nonideal gain of the converter with the ideal gain of some selected topologies whose gain intersects the nonideal gain plot of the proposed topology.The voltage stress across the switches in the compared converters is shown in Figure 20.It can be observed from Figure 19a that the proposed topology has the highest ideal gain among all the high-gain boost converters compared to all converters.An ideal voltage gain of above 14 is achieved by the proposed topology at a duty ratio of 40% and a gain of 20 is achieved at a duty ratio of 50%.The proposed converter also has a higher nonideal gain, as shown in Figure 19b, as compared to the ideal gain of the similar topologies, as presented in Table 1, until the duty ratio of 60%.The switching stress of the converter is very low as compared to the traditional topologies.In converters [4,5], even with the presence of an isolation transformer/coupled inductor operating at a transformation ratio of one, a lower gain than the proposed topology is produced, which works without a transformer or coupled inductor, hence reducing the overall cost of the topology.For n = 1, the ideal gain of the converter in [4] when compared with the gain of the proposed converter is found to be half.Moreover, the voltage stress across the switch S 1 in [4] increases significantly as shown in Figure 20.
The topology proposed in [16] also has a VMC and two switches and produces a high gain at lower duty ratios with a lower number of components as compared with the proposed topology, but it decreases as the duty ratio is increased above 40%.The proposed converter despite having fewer inductors, switches and diodes than the converter [22] is capable of producing a much higher voltage gain.Although the switch stress across the converter [22] is very low as compared to the proposed one, the converter lacks a common ground that is available in the proposed topology.The converters in [24,25], despite having 2 and 3 inductors respectively and 2 switches which is the same as used in the proposed topology, produce a lower gain than the proposed topology and, concurrently, the voltage stress across the switch.
In the case of the topology shown in [25], the switch stress increases after a conversion gain ratio of 14.The converters in [26,27] also have three inductors but suffer from a low-voltage gain.The switch S 1 of [27] has high-voltage stress after a voltage gain of 8.The quadratic boost converter in [29] has the same inductors as the proposed converter, but the voltage gain is half as compared to the proposed converter, and it has a single switch only.The topology in [29] exhibits high-voltage stress across switch S 2 amongst all the compared topologies.The topology in [30] has the least voltage stress across its switches but suffers from a low ideal voltage gain, which is much lower than the nonideal voltage gain produced by the proposed converter.
From the comparison, it can be inferred that the topology has the highest voltage gain and the switch voltage gain across S 1 is very low.The switch voltage gain across the switch S 2 is found to be high for low-voltage gains, but it does not increase further as the voltage gain increases beyond 15.Hence, the proposed topology can be used at a voltage gain higher than 14, which is easily achieved at any duty ratio beyond 40%.Moreover, continuous input current and common ground are other advantages of the proposed converter.[29] 3 6 1 6

Results
In this section, we discuss the simulation results performed on the Piecewise Linear Electrical Circuit Simulation (PLECS) and the experimental results obtained on hardware set-upfor the proposed topology.

Simulation Results
In this section, the simulation results of the proposed converter are presented.The simulation was carried out in PLECS software at an input voltage of 20 V and switching frequency of 50 kHz.The duty ratio was maintained at 0.4.The value of the inductor was 330 µΩ and its parasitic resistance was maintained at 0.12 Ω, while the value of capacitors was 47 µΩ and its parasitic resistance was kept at 0.1 Ω.The ON-state resistance of the switches was found to be 70 mΩ.With the above parameters, the simulation was performed and the output voltage was found to be V O = 248.08V at a 40% duty ratio with V in = 20 V, which can be seen in Figure 21.
From Figure 23, the peak voltage across switches S1 and S2 was found to be  ( ) = 30.687V and  ( ) = 155.43V, respectively, while the RMS voltage was  ( ) = 23.77V and  ( ) = 120.40V, respectively.From Figure 24, the average capacitor voltages in the simulation were found to be  =  = 27.5209 and  = 58.65 , while from Figure 25, the capacitor voltages were  = −56.58,  = 57.16, and  =  = 248.08.The ripple in capacitor voltages was negligible and, hence, the RMS and average voltages were found to be the same.In Figure 22, the inductor current through inductor L 1 was found to be I L1 = 5.06 A and I L2 = I L3 = 0.58 A for inductor L 2 .The ripple in the current through the inductor was lower and, hence, the average and RMS values were found to be the same.From Figure 23, the peak voltage across switches S 1 and S 2 was found to be V S1(peak) = 30.687V and V S2(peak) = 155.43V, respectively, while the RMS voltage was V S1(rms) = 23.77V. and V S1(rms) = 120.40V, respectively.From Figure 24, the average capacitor voltages in the simulation were found to be V C1 = V C2 = 27.5209V and V C3 = 58.65 V, while from Figure 25, the capacitor voltages were V C4 = −56.58V, V C5 = 57.16V, and V CO = V O = 248.08V.The ripple in capacitor voltages was negligible and, hence, the RMS and average voltages were found to be the same.

Experimental Results
The experimental analysis of the proposed converter was carried out on the same parameters as the simulation procedure.To verify the overall voltage boosting, continuous current, and capacitor voltage handling capability of the proposed converter, a hardware prototype of the proposed converter was tested under standard laboratory conditions with the parameters mentioned in Table 2. To demonstrate the working of the topol-

Experimental Results
The experimental analysis of the proposed converter was carried out on the same parameters as the simulation procedure.To verify the overall voltage boosting, continuous current, and capacitor voltage handling capability of the proposed converter, a hardware prototype of the proposed converter was tested under standard laboratory conditions with parameters mentioned in Table 2. To demonstrate the working of the topology, a converter with an output power of 200 W at a duty ratio of 40% was implemented with a load resistance of 300 Ω.For switches S 1 and S 2 , Power MOSFET with part number SPW52N50C3 provided with a duty cycle (D) of 0.4 operating at a switching frequency (f s ) of 50 kHz was used, whereas diodes (D O − D 6 ) with part number HER806 were used.From Figure 26, a 20 V DC supply was used at the input side and an output of 240 V was obtained for the same with V gs as the gate drive signal.V, respectively, in each cycle, which can be seen in Figure 28.The peak reverse blocking voltage is about 30 V for the switch  and 160 V for switch  for the output voltage of 240 V. Capacitor  has a voltage of 30 V across it, while capacitors C3 and C4 have a voltage of 60 V with very-low-voltage ripples as in Figure 29.The experimental setup is shown in Figure 30.From Figure 27, when the switches are ON, the inductors become charged and the current through them increases.For inductor L 1 , it increases from an initial value of 4.8 A to a peak value of 5.2 A and it increases from an initial value of 0.7 A to a peak value of 1.0 A for inductors L 2 and L 3 .When the switches are OFF, the inductors release their stored energy, and the currents through them decrease back to their initial values.During the OFF state, the switches are reversed-biased and block a peak voltage of 30 V and 160 V, respectively, in each cycle, which can be seen in Figure 28.The peak reverse blocking voltage is about 30 V for the switch S 1 and 160 V for switch S 2 for the output voltage of 240 V. Capacitor C 1 has a voltage of 30 V across it, while capacitors 3 and C 4 have a voltage of 60 V with very-low-voltage ripples as in Figure 29.The experimental setup is shown in Figure 30.
Figure 31 shows the variation in efficiency with the output power as the input voltage is increased.It can be observed that as the input voltage increases, the efficiency of the converter increases.This occurs because with the increase in voltage, the current decreases to conserve the power; hence, the conduction losses across various elements of the converter including switches, diodes, and parasitic resistances of the inductor and capacitor are reduced.
The maximum efficiency of the converter is found as 97.85% at 30 V, 66 W followed by 96.5% for operation at 20 V for the same power.From Figure 32, the majority of the conduction losses i.e., around 39%, occur in the capacitors, out of which 58.5% of the losses in capacitors are due to capacitor C 3 itself.The switches and diodes contribute 40% of the total losses.The losses can be further reduced by using diodes and switches with low parasitic resistance.
Electronics 2022, 11, x FOR PEER REVIEW 24 of 28 V, respectively, in each cycle, which can be seen in Figure 28.The peak reverse blocking voltage is about 30 V for the switch  and 160 V for switch  for the output voltage of 240 V. Capacitor  has a voltage of 30 V across it, while capacitors C3 and C4 have a voltage of 60 V with very-low-voltage ripples as in Figure 29.The experimental setup is shown in Figure 30.V, respectively, in each cycle, which can be seen in Figure 28.The peak reverse blocking voltage is about 30 V for the switch  and 160 V for switch  for the output voltage of 240 V. Capacitor  has a voltage of 30 V across it, while capacitors C3 and C4 have a voltage of 60 V with very-low-voltage ripples as in Figure 29.The experimental setup is shown in Figure 30.Figure 31 shows the variation in efficiency with the output power as the input voltage is increased.It can be observed that as the input voltage increases, the efficiency of the converter increases.This occurs because with the increase in voltage, the current decreases to conserve the power; hence, the conduction losses across various elements of the converter including switches, diodes, and parasitic resistances of the inductor and capacitor are reduced.
The maximum efficiency of the converter is found as 97.85% at 30 V, 66 W followed by 96.5% for operation at 20 V for the same power.From Figure 32, the majority of the conduction losses i.e., around 39%, occur in the capacitors, out of which 58.5% of the losses in capacitors are due to capacitor C3 itself.The switches and diodes contribute 40% of the total losses.The losses can be further reduced by using diodes and switches with low parasitic resistance.Figure 31 shows the variation in efficiency with the output power as the input voltage is increased.It can be observed that as the input voltage increases, the efficiency of the converter increases for the same power output because the conduction losses across various elements of the converter including switches, diodes and parasitic resistances of the inductor and capacitor are reduced.

Conclusion
The converter produces an ideal voltage gain of 11 times at a duty ratio of 30% with an ideal voltage gain of 14.44 at a duty ratio of 40%.The nonideal gain of the proposed converter at a D less than 60% is still found to be higher as compared to the ideal gains of the compared converters.In addition, the voltage stress across the switches is found to be lower than the output voltage and is also much lower than the compared topologies even at higher duty ratios.The voltage stress across S1 is 6.92% of the Vo and across switch S2, it is 46.15% of Vo at the duty ratio of 40%.The maximum efficiency of 97.85% is obtained at 66 W when the input voltage is 30 V, while it is 96.44% at a load of 38 W, keeping the input voltage at 20 V. The efficiency of the prototype model decreases with the power level due to the absence of galvanic isolation and parasitic resistances.The voltage and current stresses across the elements are low, which can be observed from the analysis and the hardware results.The converter has a common ground and operates at continuous input current, making it feasible for low-and medium-power solar and renewable energy PV applications.

Conclusions
The converter produces an ideal voltage gain of 11 times at a duty ratio of 30% with an ideal voltage gain of 14.44 at a duty ratio of 40%.The nonideal gain of the proposed converter at a D less than 60% is still found to be higher as compared to the ideal gains of the compared converters.In addition, the voltage stress across the switches is found to be lower than the output voltage and is also much lower than the compared topologies even at higher duty ratios.The voltage stress across S 1 is 6.92% of the V o and across switch S 2 , it is 46.15% of V o at the duty ratio of 40%.The maximum efficiency of 97.85% is obtained at 66 W when the input voltage is 30 V, while it is 96.44% at a load of 38 W, keeping the input voltage at 20 V. The efficiency of the prototype model decreases with the power level due to the absence of galvanic isolation and parasitic resistances.The voltage and current stresses across the elements are low, which can be observed from the analysis and the hardware results.The converter has a common ground and operates at continuous input current, making it feasible for low-and medium-power solar and renewable energy PV applications.

Figure 4 .
Figure 4. Conduction diagram of the converter in ON-state (Mode 1).

Figure 4 .
Figure 4. Conduction diagram of the converter in ON-state (Mode 1).

Figure 4 .
Figure 4. Conduction diagram of the converter in ON-state (Mode 1).

Figure 5 .
Figure 5. Conduction diagram of the proposed converter in OFF state (Mode 2).

Figure 5 .
Figure 5. Conduction diagram of the proposed converter in OFF state (Mode 2).

(i) Mode 1 :
In this mode, both switches are turned ON for duty cycle D as in the case of CCM.(ii) Mode 2: In this mode, both switches are turned OFF and the inductors start discharging.The inductors discharge through diodes D 1 , D 3 , and D O for a duty cycle D' and the mode ends at D + D'. (iii) Mode 3: In this mode, none of the switches or diodes conduct, and the load is fed entirely through the output capacitor C O .The mode is operated for a duration of 1 − D − D'.

Figure 13 .
Figure 13.Boundary normalized inductor time constant versus the duty ratio.

Figure 13 .
Figure 13.Boundary normalized inductor time constant versus the duty ratio.

Figure 14 .
Figure 14.Nonideal realization of the proposed topology.

Figure 14 .
Figure 14.Nonideal realization of the proposed topology.

Figure 15 .
Figure 15.Comparison of calculated ideal and simulated nonideal voltage gain of the proposed converter.

Figure 15 .
Figure 15.Comparison of calculated ideal and simulated nonideal voltage gain of the proposed converter.

Figure 16 .
Figure 16.Voltage gain variation as per parasitic resistance of the switch.

Figure 17 .
Figure 17.Voltage gain variation as per parasitic resistance of the inductor.

Figure 16 .
Figure 16.Voltage gain variation as per parasitic resistance of the switch.

Figure 16 .
Figure 16.Voltage gain variation as per parasitic resistance of the switch.

Figure 17 .
Figure 17.Voltage gain variation as per parasitic resistance of the inductor.

Figure 17 .
Figure 17.Voltage gain variation as per parasitic resistance of the inductor.

Figure 18 .
Figure 18.Voltage gain variation as per parasitic resistance of the capacitor.

Figure 18 .
Figure 18.Voltage gain variation as per parasitic resistance of the capacitor.

Figure 19 .
Figure 19.(a).Comparison of ideal voltage gain of various similar converters.(b).Comparison of various topologies with the non-ideal voltage gain of the proposed topology

Figure 19 .
Figure 19.(a).Comparison of ideal voltage gain of various similar converters.(b).Comparison of various topologies with the non-ideal voltage gain of the proposed topology

Figure 26 .
Figure 26.Top to bottom: experimental waveforms of output voltage (V O ), input voltage (V in ), and V gs at D = 0.4.

Figure 28 .
Figure 28.Top to bottom: experimental waveforms of output voltage (V O ), voltage across switch S 2 (V S2 ), voltage across switch S 1 (V S1 ), and V gs at D = 0.4.

Figure 29 .
Figure 29.Top to bottom: experimental waveforms of voltage across capacitor C 3 (V C3 ), the voltage across capacitor C 4 (V C4 ), and the voltage across capacitor C 1 (V C1 ) at D = 0.4.

Figure 31 .
Figure 31.Simulated efficiency vs. output power comparison of the proposed converter at different input voltages.

Figure 31 .
Figure 31.Simulated efficiency vs. output power comparison of the proposed converter at different input voltages.

Figure 32 .
Figure 32.Distribution of losses across various elements of the converter.

Figure 32 .
Figure 32.Distribution of losses across various elements of the converter.

Author
Contributions: Conceptualization, writing-original draft preparation, M.Z., I.H.M. and M.T.; supervision, M.Z. and I.A.; writing-review and editing, B.A. and E.M.G.R.; funding acquisition, M.T., B.A. and E.M.G.R.All authors have read and agreed to the published version of the manuscript.Funding: The authors would like to acknowledge the financial support from Taif University Researchers Supporting Project Number (TURSP-2020/278), Taif University, Taif, Saudi Arabia and from the collaborative research grant scheme (CRGS) project, Hardware-In-the-Loop (HIL) Lab, Department of Electrical Engineering, Aligarh Muslim University, India having project numbers CRGS/MOHD TARIQ/01 and CRGS/MOHD TARIQ/02.

Table 1 .
Comparison of proposed topology with certain similar topologies.

Table 2 .
Hardware values of parameters.