A Dual-Buck-Boost DC–DC/AC Universal Converter

: This paper proposes a universal converter that is capable of operating in three modes for generating positive dc voltage, negative dc voltage, and sinusoidal ac voltage. By controlling the duty-cycle of two half-bridges, an inductor is operated at a high frequency to control the voltage across two ﬁlm capacitors that constitute a dual-buck-boost converter. Two additional half-bridges operating at a ﬁxed state or line frequency are used to select the mode of operation. Compared to the latest universal converter in the recent literature, the proposed topology has the same switch count while reducing the number of conducting switches for inductor current and reducing the number of switches operating at high frequency. The operation of the proposed dual-buck-boost dc–dc/ac universal converter is analyzed. Experimental results are presented for validation. The power conversion efﬁciency of the 100 W experimental prototype modeled in PLECS is approximately 98%.


Introduction
Power electronics is the enabling technology for the renewable energy integrated electrical power system. Along with the innovations in power semiconductor devices, there has been a dynamic evolution in power electronics technology. In recent years, the design of converter topologies that can provide a single-stage power conversion with improved compactness and efficiency has become a hot research topic.
Topologies based on the concept of charge pumps [1][2][3] or switched-capacitors (SCs) are popular owing to attractive features, such as voltage boosting with natural voltage balancing, in their capacitors [4]. In [5][6][7], an SC is used to establish the concept of virtual dc-bus that can be discharged to generate a negative voltage across the load. They can generate a symmetric 3-level ac voltage in a single-stage operation. With the ac voltage generation referenced to the negative terminal of the dc source, these topologies provide a common ground for the dc source and the ac output that is effective for mitigating the high-frequency common-mode voltage. On integrating two SCs, one of the SCs can be charged to twice the dc source voltage magnitude to enhance the voltage gain [8]. Recent attempts have been devoted to increasing the generation of the number of levels and further enhancing the voltage gain [9][10][11][12][13][14][15]. However, all the SC topologies suffer from some constraints inherited from the SC circuits. Current spike induced by the charging process of SCs by virtue of their parallel connection with the dc source or other capacitors is a major drawback.
To achieve a wide range of voltage gain without a current spike for charging the switched-capacitors, buck-boost converters are popular and have been widely explored [16]. The conventional buck-boost converter is an inverting topology. Its output voltage is of the opposite polarity to the input dc source. This could be a constraint for some practical applications. Therefore, non-inverting buck-boost dc-dc converters have been developed [17]. Soft-switching techniques are also applied to reduce the converter switching loss [18,19].
In recent years, buck-boost converters capable of generating bipolar output voltage are getting more attention [20,21]. By operating the inductor with a variable duty-cycle, a sinusoidal ac voltage can be generated directly without the need of an additional low-pass filter [22]. Using a similar concept, buck-boost inverter topologies with common ac and dc ground are attempted to mitigate the leakage current for photovoltaic applications [23,24]. These topologies provide a single-stage dc-ac power conversion without using bulky electrolytic capacitor, which is attractive for improving the system reliability [25]. A comprehensive method for deriving common-ground-type buck-boost inverters is presented in [26].
The authors in [27] made the first attempt to develop buck-boost universal converters that can generate either dc or sinusoidal ac voltages. This attractive solution can be applicable for dc and ac microgrids. This new concept has inspired the development of a new topology in this paper. The main contribution of this paper is a novel universal converter topology that uses the same switch count as that used in [27] while reducing the number of conducting switches for inductor current and the number of switches operating at a high frequency. The proposed topology integrates two buck-boost converters into a single-stage topology that can be operated in various modes, which will be thoroughly discussed in Section 2. Section 3 compares the proposed topology with the latest universal converter presented in [27]. Experiment results are discussed in Section 4. Finally, Section 5 concludes the article.

Proposed Universal Converter
The proposed dual-buck-boost dc-dc/ac universal converter is depicted in Figure 1. By controlling the inductor L using two half-bridges, two buck-boost dc voltages V Cp and V Cn can be generated across capacitors C p and C n , respectively. Therefore, this part of the topology is termed as dual-buck-boost converter. It is supplied by a floating dc source. In the remaining circuit of the proposed topology, two low-frequency half-bridges are used to select the operating modes that are elaborated in the following sections.
Electronics 2022, 11, x FOR PEER REVIEW 2 of 12 constraints inherited from the SC circuits. Current spike induced by the charging process of SCs by virtue of their parallel connection with the dc source or other capacitors is a major drawback. To achieve a wide range of voltage gain without a current spike for charging the switched-capacitors, buck-boost converters are popular and have been widely explored [16]. The conventional buck-boost converter is an inverting topology. Its output voltage is of the opposite polarity to the input dc source. This could be a constraint for some practical applications. Therefore, non-inverting buck-boost dc-dc converters have been developed [17]. Soft-switching techniques are also applied to reduce the converter switching loss [18,19].
In recent years, buck-boost converters capable of generating bipolar output voltage are getting more attention [20,21]. By operating the inductor with a variable duty-cycle, a sinusoidal ac voltage can be generated directly without the need of an additional low-pass filter [22]. Using a similar concept, buck-boost inverter topologies with common ac and dc ground are attempted to mitigate the leakage current for photovoltaic applications [23,24]. These topologies provide a single-stage dc-ac power conversion without using bulky electrolytic capacitor, which is attractive for improving the system reliability [25]. A comprehensive method for deriving common-ground-type buck-boost inverters is presented in [26].
The authors in [27] made the first attempt to develop buck-boost universal converters that can generate either dc or sinusoidal ac voltages. This attractive solution can be applicable for dc and ac microgrids. This new concept has inspired the development of a new topology in this paper. The main contribution of this paper is a novel universal converter topology that uses the same switch count as that used in [27] while reducing the number of conducting switches for inductor current and the number of switches operating at a high frequency. The proposed topology integrates two buck-boost converters into a single-stage topology that can be operated in various modes, which will be thoroughly discussed in Section 2. Section 3 compares the proposed topology with the latest universal converter presented in [27]. Experiment results are discussed in Section 4. Finally, Section 5 concludes the article.

Proposed Universal Converter
The proposed dual-buck-boost dc-dc/ac universal converter is depicted in Figure 1. By controlling the inductor L using two half-bridges, two buck-boost dc voltages VCp and VCn can be generated across capacitors Cp and Cn, respectively. Therefore, this part of the topology is termed as dual-buck-boost converter. It is supplied by a floating dc source. In the remaining circuit of the proposed topology, two low-frequency half-bridges are used to select the operating modes that are elaborated in the following sections.   Figure 2 shows the operating principle of the proposed universal converter operating in mode 1 for generating a positive dc voltage. The inductor L is charged by the dc source during state 1 by turning on S1 and S2. Turning off S2 during state 2 charges the capacitor C p . The voltage across the inductor during this state is −V Cp , as shown in Figure 2. During steady-state, the average voltage across the inductor is zero. Therefore, the voltage (V C p ) V Cp can be derived by considering the volt-second balance of the inductor: where d is the duty-cycle of state 1 that charges L and (V dc ) V dc is the dc source voltage. Notice that the voltage gain from buck to boost can be achieved by controlling the dutycycle d, which is similar to the conventional buck-boost converter. The capacitor voltage ripple ∆V C and the inductor current ripple ∆I L are, respectively, written as where I o denotes the average load current supplied by C p , f s = 1/T s is the switching frequency of the converter, and C = C p = C n .
Electronics 2022, 11, x FOR PEER REVIEW 3 of 12 Figure 1. Proposed dual-buck-boost dc-dc/ac universal converter. Figure 2 shows the operating principle of the proposed universal converter operating in mode 1 for generating a positive dc voltage. The inductor L is charged by the dc source during state 1 by turning on S1 and S2. Turning off S2 during state 2 charges the capacitor Cp. The voltage across the inductor during this state is -VCp, as shown in Figure 2. During steady-state, the average voltage across the inductor is zero. Therefore, the voltage (

Mode 1: Generation of a Positive DC Voltage
VCp can be derived by considering the volt-second balance of the inductor: where d is the duty-cycle of state 1 that charges L and ( dc V ) Vdc is the dc source voltage.
Notice that the voltage gain from buck to boost can be achieved by controlling the dutycycle d, which is similar to the conventional buck-boost converter. The capacitor voltage ripple C V Δ and the inductor current ripple L I Δ are, respectively, written as where Io denotes the average load current supplied by Cp, fs = 1/Ts is the switching frequency of the converter, and C = Cp = Cn.

Mode 2: Generation of a Negative DC Voltage
To generate a negative dc voltage, the proposed universal converter is operated in states 3 and 4, as shown in Figure 3. The operation of the inductor in mode 2 is similar to that in mode 1. However, it discharges its energy to capacitor Cn instead of Cp during state 4. Each half-bridge in the proposed topology operates in complementary mode. Therefore, the current is flowing through the on-state power MOSFETs instead of their body diode. The voltage VCn can be calculated by using Equation (1). In this mode, the top switches of both low-frequency half-bridges are turned off. The output terminals are clamped across

Mode 2: Generation of a Negative DC Voltage
To generate a negative dc voltage, the proposed universal converter is operated in states 3 and 4, as shown in Figure 3. The operation of the inductor in mode 2 is similar to that in mode 1. However, it discharges its energy to capacitor C n instead of C p during state 4. Each half-bridge in the proposed topology operates in complementary mode. Therefore, the current is flowing through the on-state power MOSFETs instead of their body diode. The voltage V Cn can be calculated by using Equation (1). In this mode, the top switches of both low-frequency half-bridges are turned off. The output terminals are clamped across the capacitor C n in opposite polarity, thereby generating a negative voltage, the capacitor Cn in opposite polarity, thereby generating a negative voltage, i.e., vo = −VCn = −dVdc/(1 − d).

Mode 3: Generation of a Sinusoidal AC Voltage
A sinusoidal ac voltage can be generated by operating the proposed universal converter in modes 1 and 2 for generating positive and negative half-cycles, respectively. The ac output voltage can be written as where ,1o V denotes the amplitude of the ac voltage. Considering the voltage gain of the buck-boost converter in Equation (1), the following relationship can be obtained: Notice that a sinusoidal ac voltage can be generated directly by controlling the proposed universal converter with a time-varying d written as denotes the voltage gain taking the ratio of the amplitudes of the ac voltage and the dc source voltage. The pulse width modulation (PWM) scheme for mode 3 is summarized in Figure 4. In this figure, G = 1 is considered to show the key waveforms and PWM signals. The feasible range of voltage gain is similar to the conventional buckboost converter with G = 1.5 or 2 commonly reported in the literature. To reduce the voltage ripple in the output voltage, a high switching frequency relative to the output frequency should be considered. In this work, the switching frequency is 10 kHz, which is 200 times higher than the output frequency of 50 Hz.

Mode 3: Generation of a Sinusoidal AC Voltage
A sinusoidal ac voltage can be generated by operating the proposed universal converter in modes 1 and 2 for generating positive and negative half-cycles, respectively. The ac output voltage can be written as whereV o,1 denotes the amplitude of the ac voltage. Considering the voltage gain of the buck-boost converter in Equation (1), the following relationship can be obtained: Notice that a sinusoidal ac voltage can be generated directly by controlling the proposed universal converter with a time-varying d written as where G =V o,1 /V dc denotes the voltage gain taking the ratio of the amplitudes of the ac voltage and the dc source voltage. The pulse width modulation (PWM) scheme for mode 3 is summarized in Figure 4. In this figure, G = 1 is considered to show the key waveforms and PWM signals. The feasible range of voltage gain is similar to the conventional buckboost converter with G = 1.5 or 2 commonly reported in the literature. To reduce the voltage ripple in the output voltage, a high switching frequency relative to the output frequency should be considered. In this work, the switching frequency is 10 kHz, which is 200 times higher than the output frequency of 50 Hz.

Comparison with the Latest Topology
The concept of a buck-boost dc-dc/ac universal converter was first introduced in [27] This latest topology, as depicted in Figure 5, is considered for comparison to justify th advantages of the proposed topology. The switching states of both topologies are summa rized and compared in Table 1. Although the total switch count of both topologies is equa and their operating principle is similar, the proposed topology has a lesser number o conducting switches for the inductor current during states 2 and 4, which implies lowe conduction loss. To charge the inductor during dTs and discharge it for the remaining pe riod (1 − d)Ts, there are four switches in [27] operating at a high frequency. The proposed topology reduces the number of switches operating at a high frequency to only two in both modes 1 and 2. This is advantageous for reducing the switching loss.

Comparison with the Latest Topology
The concept of a buck-boost dc-dc/ac universal converter was first introduced in [27]. This latest topology, as depicted in Figure 5, is considered for comparison to justify the advantages of the proposed topology. The switching states of both topologies are summarized and compared in Table 1. Although the total switch count of both topologies is equal and their operating principle is similar, the proposed topology has a lesser number of conducting switches for the inductor current during states 2 and 4, which implies lower conduction loss. To charge the inductor during dT s and discharge it for the remaining period (1 − d)T s , there are four switches in [27] operating at a high frequency. The proposed topology reduces the number of switches operating at a high frequency to only two in both modes 1 and 2. This is advantageous for reducing the switching loss.

Comparison with the Latest Topology
The concept of a buck-boost dc-dc/ac universal converter was first intr This latest topology, as depicted in Figure 5, is considered for comparison advantages of the proposed topology. The switching states of both topologi rized and compared in Table 1. Although the total switch count of both topo and their operating principle is similar, the proposed topology has a les conducting switches for the inductor current during states 2 and 4, which conduction loss. To charge the inductor during dTs and discharge it for the riod (1 − d)Ts, there are four switches in [27] operating at a high frequency. topology reduces the number of switches operating at a high frequency both modes 1 and 2. This is advantageous for reducing the switching loss.   Table 1. Comparison between the proposed topology and the latest universal converter presented in [27].

Mode
Proposed Topology Topology Presented in [27] Table 1. Comparison between the proposed topology and the latest universal converter presented in [27].

Experimental Results
The proposed topology was implemented as depicted in Figure 6. Experimental tests were carried out in different operating modes. The following parameters were considered: Vdc = 100 V, Cp = Cn = 20 µF, L = 700 µH, fo = 50 Hz, fs = 10 kHz, and load resistance = 100 Ω. The proposed universal converter was constructed using eight silicon carbide power MOSFETs (C3M0120090D) according to the schematic in Figure 1.
Electronics 2022, 11, x FOR PEER REVIEW 6 of 12 Table 1. Comparison between the proposed topology and the latest universal converter presented in [27].

Experimental Results
The proposed topology was implemented as depicted in Figure 6. Experimental tests were carried out in different operating modes. The following parameters were considered: Vdc = 100 V, Cp = Cn = 20 µF, L = 700 µH, fo = 50 Hz, fs = 10 kHz, and load resistance = 100 Ω. The proposed universal converter was constructed using eight silicon carbide power MOSFETs (C3M0120090D) according to the schematic in Figure 1. Table 1. Comparison between the proposed topology and the latest universal converter presented in [27].

Experimental Results
The proposed topology was implemented as depicted in Figure 6. Experimental tests were carried out in different operating modes. The following parameters were considered: Vdc = 100 V, Cp = Cn = 20 µF, L = 700 µH, fo = 50 Hz, fs = 10 kHz, and load resistance = 100 Ω. The proposed universal converter was constructed using eight silicon carbide power MOSFETs (C3M0120090D) according to the schematic in Figure 1.
Electronics 2022, 11, x FOR PEER REVIEW 6 of 12 Table 1. Comparison between the proposed topology and the latest universal converter presented in [27].

Experimental Results
The proposed topology was implemented as depicted in Figure 6. Experimental tests were carried out in different operating modes. The following parameters were considered: Vdc = 100 V, Cp = Cn = 20 µF, L = 700 µH, fo = 50 Hz, fs = 10 kHz, and load resistance = 100 Ω. The proposed universal converter was constructed using eight silicon carbide power MOSFETs (C3M0120090D) according to the schematic in Figure 1.

Experimental Results
The proposed topology was implemented as depicted in Figure 6. Experimental tests were carried out in different operating modes. The following parameters were considered: V dc = 100 V, C p = C n = 20 µF, L = 700 µH, f o = 50 Hz, f s = 10 kHz, and load resistance = 100 Ω. The proposed universal converter was constructed using eight silicon carbide power MOSFETs (C3M0120090D) according to the schematic in Figure 1 The experimental results show a good agreement with the analysis that justifies the operation of the proposed topology. Figures 7 and 8 show the steady-state response of modes 1 and 2 at d = 0.5, respectively. With d = 0.5, the output voltage is 100 V and −100 V for mode 1 and mode 2, respectively. The voltage Cp resembles the output voltage vo in mode 1, while the voltage Cn corresponds in opposite polarity to vo in mode 2. The inductor voltage and the current are the same in both modes.     Figures 9 and 10 show the steady-state response of mode 3 at G = 1 and 1.5, respec tively. By controlling the duty-cycle of the proposed topology dynamically, the voltag across Cp and Cn is controlled to generate positive and negative half-cycles, respectively It can be observed in Figure 9 that the output voltage is sinusoidal, with a peak value o 100 V. For G = 1.5, the voltage and current across the passive components are increased b 1.5 times. The sine waveforms of the output voltage and output current validate the a operation of the proposed topology.   Figures 9 and 10 show the steady-state response of mode 3 at G = 1 and 1.5, respectively. By controlling the duty-cycle of the proposed topology dynamically, the voltage across C p and C n is controlled to generate positive and negative half-cycles, respectively. It can be observed in Figure 9 that the output voltage is sinusoidal, with a peak value of 100 V. For G = 1.5, the voltage and current across the passive components are increased by 1.5 times. The sine waveforms of the output voltage and output current validate the ac operation of the proposed topology.  Figures 9 and 10 show the steady-state response of mode 3 at G = 1 and 1.5, respectively. By controlling the duty-cycle of the proposed topology dynamically, the voltage across Cp and Cn is controlled to generate positive and negative half-cycles, respectively. It can be observed in Figure 9 that the output voltage is sinusoidal, with a peak value of 100 V. For G = 1.5, the voltage and current across the passive components are increased by 1.5 times. The sine waveforms of the output voltage and output current validate the ac operation of the proposed topology.   The transient response of mode 3 from G = 1 to 1.5 is presented in Figure 11. When the gain changes from 1 to 1.5, the converter reacts accordingly and the change in the corresponding voltage and current magnitudes is observed. All experimental results are in good agreement with the theoretical analysis. The voltage stress values of S1 S1 − S2 S2 − , Q1 Q1 − , and Q2 Q2 − half-bridges are Vdc + VCn, Vdc + VCp, Vdc, and Vdc + VCp + VCn, respectively. To analyze the efficiency of the proposed universal converter, therma modeling in PLECS was used to simulate the experimental prototype. The power loss dis tribution of each operating mode is summarized in Figure 12. Due to symmetric operation the same power conversion efficiency of 97.9% is obtained for both modes 1 and 2. The efficiency of mode 3 is 97.6%. Figure 11. Transient response of mode 3 from G = 1 to 1.5. The transient response of mode 3 from G = 1 to 1.5 is presented in Figure 11. When the gain changes from 1 to 1.5, the converter reacts accordingly and the change in the corresponding voltage and current magnitudes is observed. All experimental results are in good agreement with the theoretical analysis. The voltage stress values of S1 − S1, S2 − S2, Q1 − Q1, and Q2 − Q2 half-bridges are V dc + V Cn , V dc + V Cp , V dc , and V dc + V Cp + V Cn , respectively. To analyze the efficiency of the proposed universal converter, thermal modeling in PLECS was used to simulate the experimental prototype. The power loss distribution of each operating mode is summarized in Figure 12. Due to symmetric operation, the same power conversion efficiency of 97.9% is obtained for both modes 1 and 2. The efficiency of mode 3 is 97.6%. The transient response of mode 3 from G = 1 to 1.5 is presented in Figure 11. When the gain changes from 1 to 1.5, the converter reacts accordingly and the change in the corresponding voltage and current magnitudes is observed. All experimental results are in good agreement with the theoretical analysis. The voltage stress values of S1 S1 − , S2 S2 − , Q1 Q1 − , and Q2 Q2 − half-bridges are Vdc + VCn, Vdc + VCp, Vdc, and Vdc + VCp + VCn, respectively. To analyze the efficiency of the proposed universal converter, thermal modeling in PLECS was used to simulate the experimental prototype. The power loss distribution of each operating mode is summarized in Figure 12. Due to symmetric operation, the same power conversion efficiency of 97.9% is obtained for both modes 1 and 2. The efficiency of mode 3 is 97.6%. Figure 11. Transient response of mode 3 from G = 1 to 1.5. Figure 11. Transient response of mode 3 from G = 1 to 1.5.

Conclusions
In this paper, a novel dual-buck-boost dc-dc/ac universal converter is presented. B using two half-bridges, one inductor, and two film capacitors, two buck-boost converte are integrated into a single-stage topology. It can be operated to generate positive dc vo age, negative dc voltage, or sinusoidal ac voltage, with the operating modes selected

Conclusions
In this paper, a novel dual-buck-boost dc-dc/ac universal converter is presented. By using two half-bridges, one inductor, and two film capacitors, two buck-boost converters are integrated into a single-stage topology. It can be operated to generate positive dc voltage, negative dc voltage, or sinusoidal ac voltage, with the operating modes selected by controlling two additional half-bridges. This attractive feature makes the proposed topology suitable for both dc-dc and dc-ac applications at low power levels. Experimental results in both steady-state and transient response have verified the feasibility of the proposed topology. The efficiency of the experimental prototype was analyzed by modeling the power devices in PLECS. High efficiency, of approximately 98%, was achieved for all operating modes.