Reliability Analysis and Fault-Tolerant Operation in a Multilevel Inverter for Industrial Application

: The extensive employment of power semiconductor devices in multilevel inverters (MLIs) has the consequence of increased failure probabilities. With numerous applications demanding highly reliable inverters, several fault-tolerant schemes have been devised to address switch open-circuit faults. This paper analyzes a multilevel inverter topology for IGBT modules undergoing open-circuit faults, a major impediment to reliable operation within a power converter. Reconﬁguration of modulation is performed post-fault. A modulation scheme is implemented across failure modes as a hybrid of nearest level control and selective harmonic elimination. Reliability assessment of the topology is performed, including a comparison with previous literature in terms of component requirements and reliability. Simulation results validate the proposed solutions.


Introduction
The changing global paradigm about the electrical power sector with large scale renewable generation [1], high-voltage DC (HVDC) transmission systems, rapid electrification in automobiles [2], onboard power systems for aviation and marine applications [3,4], and introduction of the smart grid vision has enlarged the role of power electronic converters more than ever.The dc-ac conversion has extensive applications with MLIs (multilevel inverters) being the primary asset.The superiority of MLIs is vindicated by their excellent harmonic profile, lower switching losses and heat generation, and higher efficiency, a requirement of lower size filters with additional benefits of fault tolerance over the earlier established two-level inverters [5][6][7].
Nevertheless, an increased number of power semiconductors and circuit components like dc sources and capacitors cumulatively increase the probability of fault occurrence thus creating reliability issues [8,9].Many applications in harsh environments and long operation hours demand highly reliable converters, e.g., power networks in rural areas, critical medical equipment power supplies, aircraft, and naval power systems from a safety viewpoint, satellite systems with unfeasible maintenance, or a wind farm or solar farm with extensive and widely distributed parts [10][11][12][13].In field systems, it is observed that the power electronic converters are generally the least reliable assemblies and create significant maintenance costs [14].Demonstrably, a survey concludes that inverters are the source for 37% of unexpected maintenance and 59% of maintenance costs during the 5-year life cycle of a 3.5 MW PV system.This validates that reliability performance must be addressed in the design phase with the traditional efficiency and power density issues.

Analysis of the Topology
The schematic structure of the topology is illustrated in Figure 1.The components used comprise 10 unidirectional switches (bidirectional current flow and unidirectional blocking of voltage) and 1 bidirectional switch (consisting of two switches in common emitter configuration) with two pairs of dc voltage sources each of V dc and 3 V dc .Healthy topology operation produces 15 levels 0 to ± 7 V dc of output load voltage.Diodes D 1 , D 2 , D 3 , D 4 , D 5 , and D 6 are present to tackle the flyback effect at the instant of fault occurrence.The switching states with all the redundancies are displayed in Table 1.

Fault-Tolerance Approach
Contrary to topologies developed in [15], the investigated topology does not employ any external relays or redundant switches for fault resilience.The outcome is decreased efficiency and increased cost as the redundant components stand unutilized during healthy operation.Comparatively, all switches of the proposed topology are utilized prefault resulting in 100% utilization.A fault is tolerated on all switches leading to complete fault tolerance.The following section deals with fault conditions and fault mitigation.

Fault Conditions
Open-circuit faults on switches cause unavailability of particular voltage levels.The conditions arising from switch failures are listed in Table 2. Unattended faults lead to poor harmonic profiles but also a dc offset which is unacceptable for any load.For eliminating the dc offset the post-fault output voltage must be symmetric.

Fault-Tolerance Approach
Contrary to topologies developed in [15], the investigated topology does not employ any external relays or redundant switches for fault resilience.The outcome is decreased efficiency and increased cost as the redundant components stand unutilized during healthy operation.Comparatively, all switches of the proposed topology are utilized pre-fault resulting in 100% utilization.A fault is tolerated on all switches leading to complete fault tolerance.The following section deals with fault conditions and fault mitigation.

Fault Conditions
Open-circuit faults on switches cause unavailability of particular voltage levels.The conditions arising from switch failures are listed in Table 2. Unattended faults lead to poor harmonic profiles but also a dc offset which is unacceptable for any load.For eliminating the dc offset the post-fault output voltage must be symmetric.

Fault Correction
Post occurrence of a fault, the waveform distortion is minimized using reconfiguration of the modulation strategy.Unequal voltage levels remain post-fault as in a fault in S4/S6 or S5.
The switching angles obtained after Selective Harmonic Elemination (SHE) are rounded off to the nearest angle for compatibility with Nearest Level Modulation-Pulse Width Modulation (NLM-PWM) scheme.The modulation thus implemented is a combination of Nearest Level Modulation (NLM) and SHE methods.

Simulation Results
The performance of the proposed topology was verified in MATLAB-Simulink™ R2016b and PLECS™ version 4.0.8environment using Intel ® Core™ i5-3210M 2.50 GHz simulation.The associated parameters are listed in Table 3.The modulation scheme executed was nearest level control (NLC) PWM for load voltage control.The NLC causes switching transitions at a low switching frequency, thus minimizing the switching losses and enhancing the inverter reliability.Model parameters are listed in Table 3.The results under healthy operation and faulty conditions are presented.

Healthy Operation
Following the simulation, the output voltage produced exhibits 15 levels with each level of 100 V and a peak of 700 V. Figures 2 and 3 depict the conduction diagram for various states in positive half cycle of operation.The harmonic profile of the waveform conforms to the IEEE 519-2014 standard of generating a total harmonic distortion (THD) below 5% [27].Figure 4 depicts the resultant output waveforms.

Fault-Tolerance
Three situations can ensue from an open-circuit malfunction on an individual switch.However, due to inbuilt fault-tolerant operation, reduced voltage levels and diminished output power continue to be supplied at the load terminals.
The first situation involves preserving every voltage level and consequently the output power rating post-detection and mitigation of fault.This is observed in the case of S1 or S9 fault, where redundant states are employed through modulation reconfiguration following fault detection.As for the second situation, in cases of open-circuited S2, S3, S4, S6, S7, S8, S10, or S11, the peak level 7 V dc is lost additionally, which expedites to decrement in output power rating as well.In case of a fault in S5, level 7 V dc is not lost, thus the output power rating is conserved.

Healthy Operation
Following the simulation, the output voltage produced exhibits 15 levels with e level of 100 V and a peak of 700 V. Figures 2 and 3 depict the conduction diagram various states in positive half cycle of operation.The harmonic profile of the wavefo conforms to the IEEE 519-2014 standard of generating a total harmonic distortion (TH below 5% [27].Figure 4

Fault-Tolerance
Three situations can ensue from an open-circuit malfunction on an individual switch.However, due to inbuilt fault-tolerant operation, reduced voltage levels and diminished output power continue to be supplied at the load terminals.
The first situation involves preserving every voltage level and consequently the output power rating post-detection and mitigation of fault.This is observed in the case of S1 or S9 fault, where redundant states are employed through modulation reconfiguration following fault detection.As for the second situation, in cases of open-circuited S2, S3, S4, S6, S7, S8, S10, or S11, the peak level 7 Vdc is lost additionally, which expedites to decrement in output power rating as well.In case of a fault in S5, level 7 Vdc is not lost, thus the output power rating is conserved.

S9 or S1 Fault
Following an open-circuit fault situation in S9 or S1, the loss of levels ±3 Vdc and ±6 Vdc is mitigated by reconfiguring using redundant states, leading to all seven levels being produced post-fault and the load voltage being unaffected.Figure 5 illustrates the waveforms concerned with the S9 fault which can also represent S1 fault conditions.

S 9 or S 1 Fault
Following an open-circuit fault situation in S 9 or S 1 , the loss of levels ±3 V dc and ±6 V dc is mitigated by reconfiguring using redundant states, leading to all seven levels being produced post-fault and the load voltage being unaffected.Figure 5 illustrates the waveforms concerned with the S 9 fault which can also represent S 1 fault conditions.

S 2 , S 8, S 10, and S 11 Fault
When an open-circuit fault occurs in S 2 or S 8 , the levels ±V dc , ±2 V dc , ±4 V dc , ±5 V dc , and ±7 V dc are lost, and levels ±3 V dc and ±6 V dc can only be regenerated through reconfiguration.Furthermore, for obtaining the ideal switching angles, SHE is executed with the resulting angles being rounded off to the nearest NLC values for a better harmonic profile.The resulting waveforms are illustrated in Figure 6.
thus the output power rating is conserved.

S9 or S1 Fault
Following an open-circuit fault situation in S9 or S1, the loss of levels ±3 Vdc and ±6 Vdc is mitigated by reconfiguring using redundant states, leading to all seven levels being produced post-fault and the load voltage being unaffected.Figure 5 illustrates the waveforms concerned with the S9 fault which can also represent S1 fault conditions.

S2, S8, S10, and S11 Fault
When an open-circuit fault occurs in S2 or S8, the levels ±Vdc, ±2 Vdc, ±4 Vdc, ±5 Vdc, and ±7 Vdc are lost, and levels ±3 Vdc and ±6 Vdc can only be regenerated through reconfiguration.Furthermore, for obtaining the ideal switching angles, SHE is executed with the resulting angles being rounded off to the nearest NLC values for a better harmonic profile.The resulting waveforms are illustrated in Figure 6.

S2, S8, S10, and S11 Fault
When an open-circuit fault occurs in S2 or S8, the levels ±Vdc, ±2 Vdc, ±4 Vdc, ±5 Vdc, and ±7 Vdc are lost, and levels ±3 Vdc and ±6 Vdc can only be regenerated through reconfiguration.Furthermore, for obtaining the ideal switching angles, SHE is executed with the resulting angles being rounded off to the nearest NLC values for a better harmonic profile.The resulting waveforms are illustrated in Figure 6.

S3 or S7 Fault
Open-circuit failure on S3 or S7 leads to loss of all levels except ± Vdc levels.SHE is implemented for the reduction of harmonics post-fault.Minimum power is obtained postfault in this scenario with the THD being the highest among other cases.Although the reduced power is still more useful for a critical load than no power at all. Figure 7 shows the results.

S 3 or S 7 Fault
Open-circuit failure on S3 or S7 leads to loss of all levels except ± Vdc levels.SHE is implemented for the reduction of harmonics post-fault.Minimum power is obtained post-fault in this scenario with the THD being the highest among other cases.Although the reduced power is still more useful for a critical load than no power at all. Figure 7 shows the results.

S4 or S6 Fault
Open-circuit failure in S4 or S6 leads to loss of levels ±5 Vdc, ±6 Vdc, ±7 Vdc with levels ±Vdc, ±2 Vdc, ±3 Vdc, ±4 Vdc prevailing through modulation reconfiguration.The execution of SHE is done post-fault for refining the harmonic profile.The resulting waveforms are displayed in Figures 8 and 9.

S 4 or S 6 Fault
Open-circuit failure in S 4 or S 6 leads to loss of levels ±5 V dc , ±6 V dc , ±7 V dc with levels ±V dc , ±2 V dc , ±3 V dc , ±4 V dc prevailing through modulation reconfiguration.The execution of SHE is done post-fault for refining the harmonic profile.The resulting waveforms are displayed in Figures 8 and 9.

S4 or S6 Fault
Open-circuit failure in S4 or S6 leads to loss of levels ±5 Vdc, ±6 Vdc, ±7 Vdc with levels ±Vdc, ±2 Vdc, ±3 Vdc, ±4 Vdc prevailing through modulation reconfiguration.The execution of SHE is done post-fault for refining the harmonic profile.The resulting waveforms are displayed in Figures 8 and 9.

S5 Fault
An open-circuit fault in S5 leads to loss of levels ±2 Vdc, Vdc, Vdc with levels ±Vdc, ±5 Vdc, ±6 Vdc, ±7 Vdc being generated by the application of modulation reconfiguration.The dc component remains zero during fault; therefore, the root mean square (RMS) value of load voltage is also required for fault detection.SHE is applied for obtaining the optimum waveform to minimize the lower-order harmonics.The resulting waveforms are discussed in Figure 10.

S 5 Fault
An open-circuit fault in S 5 leads to loss of levels ±2 V dc , V dc , V dc with levels ±V dc , ±5 V dc , ±6 V dc , ±7 V dc being generated by the application of modulation reconfiguration.The dc component remains zero during fault; therefore, the root mean square (RMS) value of load voltage is also required for fault detection.SHE is applied for obtaining the optimum waveform to minimize the lower-order harmonics.The resulting waveforms are discussed in Figure 10.

S5 Fault
An open-circuit fault in S5 leads to loss of levels ±2 Vdc, Vdc, Vdc with levels ±Vdc, ±5 Vdc, ±6 Vdc, ±7 Vdc being generated by the application of modulation reconfiguration.The dc component remains zero during fault; therefore, the root mean square (RMS) value of load voltage is also required for fault detection.SHE is applied for obtaining the optimum waveform to minimize the lower-order harmonics.The resulting waveforms are discussed in Figure 10.

Reliability Analysis
Semiconductor devices are majorly prone to faults in an MLI.Nonetheless, the inherent fault-tolerant capabilities of the MLI amplify its reliability due to the provision of continued operation after the fault.

Component Failure Rate Evaluation
The failure rate of the various components depends on multiple factors derived from MIL-HDBK-217F [28], like voltage rating, application, thermal characteristics, etc.The failure rate of a semiconductor switch is derived as: where λ b is the base failure rate being equal to 0.00074.π T is the junction temperature factor and π R is the power rating factor and are both dependent on switch power loss values.The application factor π A corresponds to switching.The quality factor is taken for JANTX quality, and the analysis is done for a benign ground environment.

Power Loss Analysis
Switching losses and conduction losses are the two parts of the device losses.Conduction losses in an IGBT can be evaluated using (2) and a diode using (3).The fundamental period observes a total conduction loss of magnitude equal to (4).The various constants are determined by the datasheet of the device.
Above, V sw represents the voltage drop across the switch when it is ON and V D represents voltage drop across a diode.Non-ideal switching transitions give rise to switching losses in the circuit.With a linear assumption of current and voltage variation during switching, we arrive at the following relation for switching loss The number of switching transitions to ON and OFF states of the switches respectively is stood for by N ON k and N OFF k with E ON k and E OFF k correspondingly equal to the associated energy losses for the kth device, f is the fundamental frequency.The sum total loss is: With the power loss of every device known beforehand, the steady-state junction temperature of every switch can be determined.Thermal modeling analysis was implemented in PLECS software with the load as 50 + 50j Ω. IGBT with diode IKW40N65ES5 data was used for thermal modeling.The thermal description of the joule losses for the IGBT and Diode is given in Figures 11 and 12. Respectively.The calculated values of π R , π T, and π S are given in Table 4.

Derivation of the Reliability Function
The reliability function for a device, according to [28] is defined as where f (t) is the probability of failure of a device in a given period.The reliability function of the topology is derived using Equations ( 7) and ( 8) and is represented by Equation ( 9).The first term of the equation reflects the healthy mode of operation with the succeeding terms added for various cases of fault tolerance through modulation reconfiguration for fault in any one switch.
The fault in S 1 /S 9 is represented by the second term.The equation's third term reflects fault in S 2 /S 8 .The fourth term of the above equation reflects fault in S 3 /S 7 .Similarly, sixth seventh, and eighth terms represent a fault in S 4 /S 6 , S 5 , and S 10 /S 11 respectively.The reliability curve and its comparison with previous topologies are depicted in Figure 13 for 20 years.It is recognizable that the proposed topology has higher reliability than topologies introduced in [15,16,20,24,25,29].

Derivation of the Reliability Function
The reliability function for a device, according to [28] is defined as where () is the probability of failure of a device in a given period.The reliability function of the topology is derived using Equations ( 7) and ( 8) and is represented by Equation ( 9).The first term of the equation reflects the healthy mode of operation with the succeeding terms added for various cases of fault tolerance through modulation reconfiguration for fault in any one switch.
The fault in S1/S9 is represented by the second term.The equation's third term reflects fault in S2/S8.The fourth term of the above equation reflects fault in S3/S7.Similarly, sixth seventh, and eighth terms represent a fault in S4/S6, S5, and S10/S11 respectively.The reliability curve and its comparison with previous topologies are depicted in Figure 13 for 20 years.It is recognizable that the proposed topology has higher reliability than topologies introduced in [15,16,20,24,25,29].
depicts the resultant output waveforms.

Figure 4 .
Figure 4. Simulation results of the proposed structure during healthy operation comprising (a) load voltage, (b) magnified view of load voltage, (c) load current, (d) magnified view of load current, (e) voltage harmonic characteristics acquired from Fourier analysis, and (f) current harmonic characteristics.

Figure 5 .
Figure 5. Simulation results for S9 fault for (a) load voltage, (b) load current, (c) fault detection signal, and (d) voltage harmonics profile.

Figure 7 .
Figure 7. Simulation results for S 3 fault for (a) load voltage, (b) load current, (c) fault detection signal, (d) voltage harmonics profile, (e) diode current, and (f) current harmonics profile.

Figure 8 .
Figure 8. Simulation results for S 6 fault for (a) load voltage, (b) load current, (c) fault detection signal, and (d) voltage harmonics profile.

Figure 9 .
Figure 9. Simulation results for S 6 fault for (a) diode current and (b) current harmonic profile.

FundamentalFigure 10 .
Figure 10.Simulation results for S5 fault for (a) load voltage, (b) load current, (c) fault detection signal, (d) voltage harmonics profile, and (e) current harmonics profile.Figure 10.Simulation results for S 5 fault for (a) load voltage, (b) load current, (c) fault detection signal, (d) voltage harmonics profile, and (e) current harmonics profile.

Figure 10 .
Figure 10.Simulation results for S5 fault for (a) load voltage, (b) load current, (c) fault detection signal, (d) voltage harmonics profile, and (e) current harmonics profile.Figure 10.Simulation results for S 5 fault for (a) load voltage, (b) load current, (c) fault detection signal, (d) voltage harmonics profile, and (e) current harmonics profile.

Figure 12 .
Figure 12.Diode thermal description corresponding to (a) Turn OFF losses and (b) conduction losses.

Figure 13 .
Figure 13.Reliability comparison with previous literature.

Figure 13 .
Figure 13.Reliability comparison with previous literature.

Table 1 .
Fault management for each switch.

Table 2 .
Fault management for each switch.