Development of a Digitally Controlled Inductive Power Transfer System with Post-Regulation for Variable Load Demand

Inductive Power Transfer (IPT) is an emerging technology enabling a contactless charging process in manifold applications such as electric vehicles, wearable and portable devices, or biomedical applications. Such technology can be profitably used to develop enhanced electronic solutions in the framework of smart cities, homes and smart workplaces. This paper presents the development and realization of a series–series compensated IPT System (IPTS) followed by a post-regulator implemented by means of a DC–DC converter. Such a system is modeled through a first harmonic approximation method, and a sensitivity analysis of the IPTS performance is carried out with respect to the variations of the primary inverter switching frequency and phase-shift angle. As an element of novelty of this work, the bias points are determined which allow the efficiency maximization while ensuring system controllability. An enhanced dynamic modeling of the system is then performed by means of a coupled mode theory, including the inverter phase-shift modulation and extending its validity to whatever operating frequency. A digital control of the post-regulator is implemented by means of a commercial low-cost microcontroller enabling the output voltage regulation under both fixed and variable load conditions through a voltage mode control technique. An IPTS prototype is eventually realized, which is able to correctly perform the output voltage regulation at the desired nominal value of 12 V for static resistive loads in the range [5, 24] Ω, yielding the output power in the range [6, 28.8] W and the experimental efficiencies going from 72.1% (for 24 Ω) to 91.7% (for 5 Ω). The developed system can also be effectively used to deliver up to 35 W output power to variable loads, as demonstrated during the battery charging test. Finally, an excellent output voltage regulation is ascertained for load transients between 5 Ω and 24 Ω, with limited over- and undershoot amplitudes (less than 3% of the nominal output voltage), thus enabling the use of the proposed system for both fixed and variable loads in the framework of smart homes and workplaces applications.


Introduction
The wireless charging of electric and electronic devices and systems has become increasingly popular in everyday life since it allows for a contactless power transfer between a stationary primary source and one or more stationary or movable secondary loads. In this framework, Inductive Power Transfer (IPT) allows for a safe, reliable and cost-effective charging process over relatively large air-gaps via magnetic coupling between the primary transmitting and the secondary receiving coil, by exploiting the same operation principle as that of transformers and coupled inductors but with weaker coupling. Today, IPT Systems (IPTSs) are used in manifold applications such as charging electric vehicles [1], as with respect to the duty-cycle, which may lead to system instability for certain parameters and component values. Hence, feasible operating regions have been determined wherein the system controllability is ascertained.
As a third element of novelty, we have performed the dynamic modeling of the postregulated IPTS by means of Coupled Mode Theory (CMT). In this regard, we have enhanced the original CMT modeling procedure by including the inverter phase-shift modulation and by extending its validity to whatever operating frequency. As a result, the control-to-output transfer function of the post-regulator has been obtained, enabling the digital controller design needed for the output voltage regulation.
An experimental prototype of the IPTS has been eventually developed to be able to deliver up to 35 W output power at the maximum efficiency of 91.7%. The article is arranged as follows: in the next sub-section, an overview of different IPTS architectures and control techniques is provided; in Section 2, the static system-level modeling of the presented IPTS is discussed, followed by the dynamic modeling and digital controller design presented in Section 3. The experimental prototype of the proposed IPTS is described in Section 4, and the measurements results are provided and discussed. Eventually, the conclusions are drawn in Section 5. Figure 1 depicts one of the most commonly used architectures of the IPT systems based on the S-S compensation topology and using a full-bridge inverter on the transmitting (TX) side and a passive diode-bridge rectifier on the receiving (RX) side. The primary inverter converts the DC voltage and current waveforms of the source into the AC waveforms applied to the primary resonant tank, which is composed of a primary IPT coil and the respective resonant capacitor. The power is wirelessly transferred between the primary and the secondary coil by means of mutual coupling, and the resulting AC voltage and current waveforms of the secondary resonant tank are rectified by the diode-bridge and delivered to the load. For such IPTS topology, it is not possible to realize the output voltage regulation entirely on the RX side, since the diodes are automatically turned on and off depending on the secondary coil current direction. The research presented in [13] proposed a control scheme to regulate the output voltage of the S-S IPTS with passive rectification by controlling the switching frequency or the phase-shift angle of the full-bridge inverter. A detailed dynamic analysis based on the extended describing function technique was presented and the small-signal model of the system derived including both the frequency and the phase-shift control. However, such a control strategy requires the presence of a communication link between the TX and RX sides, which introduces a delay in the control loop and thus limits the dynamic performances of the proposed control scheme.

Overview of IPTS Architectures and Control Techniques
Electronics 2022, 11, 58 3 of 35 As a second element of novelty, we have investigated the controllability issues of the buck post-regulator cascaded to the IPTS using the developed FHA static model. In this regard, we have shown that the buck output voltage can present a non-monotonic behavior with respect to the duty-cycle, which may lead to system instability for certain parameters and component values. Hence, feasible operating regions have been determined wherein the system controllability is ascertained.
As a third element of novelty, we have performed the dynamic modeling of the postregulated IPTS by means of Coupled Mode Theory (CMT). In this regard, we have enhanced the original CMT modeling procedure by including the inverter phase-shift modulation and by extending its validity to whatever operating frequency. As a result, the control-to-output transfer function of the post-regulator has been obtained, enabling the digital controller design needed for the output voltage regulation.
An experimental prototype of the IPTS has been eventually developed to be able to deliver up to 35 W output power at the maximum efficiency of 91.7%. The article is arranged as follows: in the next sub-section, an overview of different IPTS architectures and control techniques is provided; in Section 2, the static system-level modeling of the presented IPTS is discussed, followed by the dynamic modeling and digital controller design presented in Section 3. The experimental prototype of the proposed IPTS is described in Section 4, and the measurements results are provided and discussed. Eventually, the conclusions are drawn in Section 5. Figure 1 depicts one of the most commonly used architectures of the IPT systems based on the S-S compensation topology and using a full-bridge inverter on the transmitting (TX) side and a passive diode-bridge rectifier on the receiving (RX) side. The primary inverter converts the DC voltage and current waveforms of the source into the AC waveforms applied to the primary resonant tank, which is composed of a primary IPT coil and the respective resonant capacitor. The power is wirelessly transferred between the primary and the secondary coil by means of mutual coupling, and the resulting AC voltage and current waveforms of the secondary resonant tank are rectified by the diode-bridge and delivered to the load. For such IPTS topology, it is not possible to realize the output voltage regulation entirely on the RX side, since the diodes are automatically turned on and off depending on the secondary coil current direction. The research presented in [13] proposed a control scheme to regulate the output voltage of the S-S IPTS with passive rectification by controlling the switching frequency or the phase-shift angle of the fullbridge inverter. A detailed dynamic analysis based on the extended describing function technique was presented and the small-signal model of the system derived including both the frequency and the phase-shift control. However, such a control strategy requires the presence of a communication link between the TX and RX sides, which introduces a delay in the control loop and thus limits the dynamic performances of the proposed control scheme.  An active rectification scheme replaces rectifier diodes with power MOSFETs, thus allowing to control their switching process and directly regulate the output voltage on the RX side, without using any communication link with the TX side. In [14], a fixed-frequency phase-shift control strategy was proposed for dual active IPTS including full-bridge inverter and rectifier. In such a scheme, the secondary phase-shift angle is controlled to regulate the system output voltage, while the primary phase-shift angle is adjusted to achieve the Electronics 2022, 11, 58 4 of 35 minimum duty-cycle needed for zero-voltage switching (ZVS). The complication of the proposed scheme is that the current phase detection circuits are required on both the TX and RX sides to realize the proposed control strategy.

Overview of IPTS Architectures and Control Techniques
A similar bidirectional S-S IPTS with a double active bridge configuration was presented in [17], with the difference that two cascaded contactless transformers have been adopted for energy charging between electric vehicles. Two control strategies were implemented: the Primary Phase-Locked Loop (P-PLL) and Pulse-Width Modulation (PWM) control (P-PLL&PWM) and the Primary Constant Frequency plus Secondary PWM control (P-CF+S-PWM). In the P-PLL&PWM control scheme depicted in Figure 2, the PWM controller regulates the pulse width of the primary full-bridge inverter to regulate the output voltage, and the PLL control strategy regulates the frequency of the inverter to the achieve the ZVS of power devices on the primary side, while the active bridge rectifier on the RX side works as a conventional rectifier circuit. In the P-CF+S-PWM scheme shown in Figure 3, the primary inverter provides a full square-wave voltage having a constant switching frequency, while the output voltage regulation is realized entirely on the RX side by controlling the rectifier pulse-width duration. Hence, the second approach does not require a communication link between the TX and RX side. The experimental results suggest that the P-CF+S-PWM control has higher efficiency. However, such a strategy does not consider the efficiency maximization and can therefore be improved.
An active rectification scheme replaces rectifier diodes with power MOSFETs, thus allowing to control their switching process and directly regulate the output voltage on the RX side, without using any communication link with the TX side. In [14], a fixed-frequency phase-shift control strategy was proposed for dual active IPTS including fullbridge inverter and rectifier. In such a scheme, the secondary phase-shift angle is controlled to regulate the system output voltage, while the primary phase-shift angle is adjusted to achieve the minimum duty-cycle needed for zero-voltage switching (ZVS). The complication of the proposed scheme is that the current phase detection circuits are required on both the TX and RX sides to realize the proposed control strategy.
A similar bidirectional S-S IPTS with a double active bridge configuration was presented in [17], with the difference that two cascaded contactless transformers have been adopted for energy charging between electric vehicles. Two control strategies were implemented: the Primary Phase-Locked Loop (P-PLL) and Pulse-Width Modulation (PWM) control (P-PLL&PWM) and the Primary Constant Frequency plus Secondary PWM control (P-CF+S-PWM). In the P-PLL&PWM control scheme depicted in Figure 2, the PWM controller regulates the pulse width of the primary full-bridge inverter to regulate the output voltage, and the PLL control strategy regulates the frequency of the inverter to the achieve the ZVS of power devices on the primary side, while the active bridge rectifier on the RX side works as a conventional rectifier circuit. In the P-CF+S-PWM scheme shown in Figure 3, the primary inverter provides a full square-wave voltage having a constant switching frequency, while the output voltage regulation is realized entirely on the RX side by controlling the rectifier pulse-width duration. Hence, the second approach does not require a communication link between the TX and RX side. The experimental results suggest that the P-CF+S-PWM control has higher efficiency. However, such a strategy does not consider the efficiency maximization and can therefore be improved.   An active rectification scheme replaces rectifier diodes with power MOSFETs, thus allowing to control their switching process and directly regulate the output voltage on the RX side, without using any communication link with the TX side. In [14], a fixed-frequency phase-shift control strategy was proposed for dual active IPTS including fullbridge inverter and rectifier. In such a scheme, the secondary phase-shift angle is controlled to regulate the system output voltage, while the primary phase-shift angle is adjusted to achieve the minimum duty-cycle needed for zero-voltage switching (ZVS). The complication of the proposed scheme is that the current phase detection circuits are required on both the TX and RX sides to realize the proposed control strategy.
A similar bidirectional S-S IPTS with a double active bridge configuration was presented in [17], with the difference that two cascaded contactless transformers have been adopted for energy charging between electric vehicles. Two control strategies were implemented: the Primary Phase-Locked Loop (P-PLL) and Pulse-Width Modulation (PWM) control (P-PLL&PWM) and the Primary Constant Frequency plus Secondary PWM control (P-CF+S-PWM). In the P-PLL&PWM control scheme depicted in Figure 2, the PWM controller regulates the pulse width of the primary full-bridge inverter to regulate the output voltage, and the PLL control strategy regulates the frequency of the inverter to the achieve the ZVS of power devices on the primary side, while the active bridge rectifier on the RX side works as a conventional rectifier circuit. In the P-CF+S-PWM scheme shown in Figure 3, the primary inverter provides a full square-wave voltage having a constant switching frequency, while the output voltage regulation is realized entirely on the RX side by controlling the rectifier pulse-width duration. Hence, the second approach does not require a communication link between the TX and RX side. The experimental results suggest that the P-CF+S-PWM control has higher efficiency. However, such a strategy does not consider the efficiency maximization and can therefore be improved.   A more complex IPTS scheme with active rectification and a post-regulator on the RX side depicted in Figure 4 was proposed in [18] with the scope to maximize the efficiency as well as increase the amount of extractable power while operating in non-resonant conditions. The proposed method is based on actively modifying the equivalent secondaryside load impedance Z L seen at the rectifier input, by controlling the phase-shift ϕ of the active rectifier and its output voltage level V r . This parameter can be controlled by either adjusting the duty-cycle D of the post-regulator or by varying the duty-cycle δ of the active rectifier, as shown in Figure 5. The phase-shift ϕ between the secondary voltage V L and current I L is realized by inserting a time delay between the primary and secondary side control signals, which is achieved by using a communication link between the primary and secondary side controllers. The proposed scheme considers a constant battery voltage at the IPTS output and does not perform the output voltage regulation, which could be a drawback for different types of load.
A more complex IPTS scheme with active rectification and a post-regulator on the RX side depicted in Figure 4 was proposed in [18] with the scope to maximize the efficiency as well as increase the amount of extractable power while operating in non-resonant conditions. The proposed method is based on actively modifying the equivalent secondaryside load impedance ZL seen at the rectifier input, by controlling the phase-shift φ of the active rectifier and its output voltage level Vr. This parameter can be controlled by either adjusting the duty-cycle D of the post-regulator or by varying the duty-cycle δ of the active rectifier, as shown in Figure 5. The phase-shift φ between the secondary voltage VL and current IL is realized by inserting a time delay between the primary and secondary side control signals, which is achieved by using a communication link between the primary and secondary side controllers. The proposed scheme considers a constant battery voltage at the IPTS output and does not perform the output voltage regulation, which could be a drawback for different types of load. To enhance regulation capabilities of the IPTS schemes with passive rectification such as the one depicted in Figure 1, pre-or post-regulators can be adopted. Some of the papers introducing IPTSs with post-regulating DC/DC converters have used the perturb-and-observe (P&O) techniques to achieve maximum system efficiency. The research presented in [19] proposed the S-S IPTS using a passive diode-bridge rectifier followed by a cascaded boost-buck converter. A P&O technique was adopted which searches for the optimal postregulator duty-cycle value maximizing the overall system efficiency obtained at the IPT resonant frequency. Similarly to the work presented in [18], no regulation of the output voltage was included in the above control scheme. In [20], a method for automatic maximum efficiency point tracking of the IPTS followed by a buck-boost converter was proposed. The presented algorithm searches for the minimum input power operating point for a given output power by varying the phase-shift of the inverter, while the PI controller of the buck-boost adjusts the output voltage. Because the searching process is carried out on the TX side, the proposal does not require any feedback from the RX side. The research in [21] proposes some improvements with respect to [20], by adopting a Discrete Sliding Mode Control (DSMC) scheme for the buck-boost post-regulator. The TX side of the A more complex IPTS scheme with active rectification and a post-regulator on the RX side depicted in Figure 4 was proposed in [18] with the scope to maximize the efficiency as well as increase the amount of extractable power while operating in non-resonant conditions. The proposed method is based on actively modifying the equivalent secondaryside load impedance ZL seen at the rectifier input, by controlling the phase-shift φ of the active rectifier and its output voltage level Vr. This parameter can be controlled by either adjusting the duty-cycle D of the post-regulator or by varying the duty-cycle δ of the active rectifier, as shown in Figure 5. The phase-shift φ between the secondary voltage VL and current IL is realized by inserting a time delay between the primary and secondary side control signals, which is achieved by using a communication link between the primary and secondary side controllers. The proposed scheme considers a constant battery voltage at the IPTS output and does not perform the output voltage regulation, which could be a drawback for different types of load. To enhance regulation capabilities of the IPTS schemes with passive rectification such as the one depicted in Figure 1, pre-or post-regulators can be adopted. Some of the papers introducing IPTSs with post-regulating DC/DC converters have used the perturb-and-observe (P&O) techniques to achieve maximum system efficiency. The research presented in [19] proposed the S-S IPTS using a passive diode-bridge rectifier followed by a cascaded boost-buck converter. A P&O technique was adopted which searches for the optimal postregulator duty-cycle value maximizing the overall system efficiency obtained at the IPT resonant frequency. Similarly to the work presented in [18], no regulation of the output voltage was included in the above control scheme. In [20], a method for automatic maximum efficiency point tracking of the IPTS followed by a buck-boost converter was proposed. The presented algorithm searches for the minimum input power operating point for a given output power by varying the phase-shift of the inverter, while the PI controller of the buck-boost adjusts the output voltage. Because the searching process is carried out on the TX side, the proposal does not require any feedback from the RX side. The research in [21] proposes some improvements with respect to [20], by adopting a Discrete Sliding Mode Control (DSMC) scheme for the buck-boost post-regulator. The TX side of the To enhance regulation capabilities of the IPTS schemes with passive rectification such as the one depicted in Figure 1, pre-or post-regulators can be adopted. Some of the papers introducing IPTSs with post-regulating DC/DC converters have used the perturb-andobserve (P&O) techniques to achieve maximum system efficiency. The research presented in [19] proposed the S-S IPTS using a passive diode-bridge rectifier followed by a cascaded boost-buck converter. A P&O technique was adopted which searches for the optimal post-regulator duty-cycle value maximizing the overall system efficiency obtained at the IPT resonant frequency. Similarly to the work presented in [18], no regulation of the output voltage was included in the above control scheme. In [20], a method for automatic maximum efficiency point tracking of the IPTS followed by a buck-boost converter was proposed. The presented algorithm searches for the minimum input power operating point for a given output power by varying the phase-shift of the inverter, while the PI controller of the buck-boost adjusts the output voltage. Because the searching process is carried out on the TX side, the proposal does not require any feedback from the RX side. The research in [21] proposes some improvements with respect to [20], by adopting a Discrete Sliding Mode Control (DSMC) scheme for the buck-boost post-regulator. The TX side of the adopted IPTS comprises a phase-shift full-bridge inverter, which incorporates the hill-climbing-search-based phase angle control for achieving minimum input current injection from its DC source, thereby attaining minimum the input power operation. The buck-boost converter realizes the output voltage regulation by means of the proposed DSMC scheme, which outperforms classical PI controller-based schemes in terms of better dynamic performances. The S-S IPTS with a passive rectifier and a Single-Ended Primary Inductor Converter (SEPIC) depicted in Figure 6 was proposed in [22]. The SEPIC topology offers several benefits in switching power supplies thanks to its non-inverting step-up/step-down conversion ratio, to the possibility of reducing the size of magnetic components by using coupled inductors and to its loss-less resistor behavior in power factor pre-regulation applications [23]. A phase-shift control of the primary inverter was designed to regulate the primary coil current at a given reference value, in order to optimize the equivalent load resistance seen at the post-regulator input for maximum energy efficiency. A peak-current-control of the SEPIC was configured to guarantee the output voltage regulation under different load conditions. A disadvantage of the proposed approach consists of utilizing a refence value for the primary current (to achieve the optimal load conditions) which is very sensitive to the coupling coefficient and system component variations.
adopted IPTS comprises a phase-shift full-bridge inverter, which incorporates the hillclimbing-search-based phase angle control for achieving minimum input current injection from its DC source, thereby attaining minimum the input power operation. The buckboost converter realizes the output voltage regulation by means of the proposed DSMC scheme, which outperforms classical PI controller-based schemes in terms of better dynamic performances.
The S-S IPTS with a passive rectifier and a Single-Ended Primary Inductor Converter (SEPIC) depicted in Figure 6 was proposed in [22]. The SEPIC topology offers several benefits in switching power supplies thanks to its non-inverting step-up/step-down conversion ratio, to the possibility of reducing the size of magnetic components by using coupled inductors and to its loss-less resistor behavior in power factor pre-regulation applications [23]. A phase-shift control of the primary inverter was designed to regulate the primary coil current at a given reference value, in order to optimize the equivalent load resistance seen at the post-regulator input for maximum energy efficiency. A peak-current-control of the SEPIC was configured to guarantee the output voltage regulation under different load conditions. A disadvantage of the proposed approach consists of utilizing a refence value for the primary current (to achieve the optimal load conditions) which is very sensitive to the coupling coefficient and system component variations. A more complicated control scheme for the IPTS with a passive rectification and a buck-boost post-regulator was proposed in [24] with the aim of maximizing the overall system efficiency while maintaining a constant output power level. In such a scheme, a primary-to-secondary voltage ratio is regulated through the buck-boost duty-cycle control to reach the maximum efficiency under resonance conditions, while the IPTS input voltage is adjusted to yield the target output power to the load. Such a control scheme requires a pre-regulator (e.g., a boost converter) to change the IPTS input voltage, which ends up being complicated for practical implementations; moreover, the proposed voltage ratio control criterion is only valid under given resonance conditions. Finally, the output voltage regulation is not included in the above control scheme.
The authors in [25] presented a Maximum Efficiency Point (MEP) tracking method for IPTSs whose RX side contains either a passive rectifier with post-regulator or a regulating rectifier. This last rectification topology uses two additional MOSFETs at the input of the diode bridge which are periodically turned on and off to regulate the IPTS output voltage. It is proven that, under resonance conditions, at the MEP, the derivative of postregulator duty-cycle D with respect to the inverter DC input voltage Vin is equal to or smaller than a constant β determined by the system parameters, namely dD/dVin ≤ β. It is also shown that increasing Vin allows to reach the MEP as soon as dD/dVin becomes equal to or lower than β. Thus, the MEP can be tracked without a power or current sensor.
Four different IPTS schemes and relative control techniques were analyzed and compared in [16], with the scope to achieve the output voltage regulation: Lower-side Frequency Control (LFC), Higher-side Frequency Control (HFC), pre-regulation, and post- A more complicated control scheme for the IPTS with a passive rectification and a buck-boost post-regulator was proposed in [24] with the aim of maximizing the overall system efficiency while maintaining a constant output power level. In such a scheme, a primary-to-secondary voltage ratio is regulated through the buck-boost duty-cycle control to reach the maximum efficiency under resonance conditions, while the IPTS input voltage is adjusted to yield the target output power to the load. Such a control scheme requires a pre-regulator (e.g., a boost converter) to change the IPTS input voltage, which ends up being complicated for practical implementations; moreover, the proposed voltage ratio control criterion is only valid under given resonance conditions. Finally, the output voltage regulation is not included in the above control scheme.
The authors in [25] presented a Maximum Efficiency Point (MEP) tracking method for IPTSs whose RX side contains either a passive rectifier with post-regulator or a regulating rectifier. This last rectification topology uses two additional MOSFETs at the input of the diode bridge which are periodically turned on and off to regulate the IPTS output voltage. It is proven that, under resonance conditions, at the MEP, the derivative of post-regulator duty-cycle D with respect to the inverter DC input voltage V in is equal to or smaller than a constant β determined by the system parameters, namely dD/dV in ≤ β. It is also shown that increasing V in allows to reach the MEP as soon as dD/dV in becomes equal to or lower than β. Thus, the MEP can be tracked without a power or current sensor.
Four different IPTS schemes and relative control techniques were analyzed and compared in [16], with the scope to achieve the output voltage regulation: Lower-side Frequency Control (LFC), Higher-side Frequency Control (HFC), pre-regulation, and post-regulation. The first two techniques are based on the behavior of an open-loop IPTS which presents two peaks near the split frequencies in the "over coupled" region, as depicted in Figure 7. In particular, LFC (HFC) controls the inverter switching frequency on the left (right) side of the low (high) split frequency to regulate the IPTS output voltage. Conversely, the pre-(post-) regulation scheme adopts a DC/DC converter on the primary (secondary) IPT side to regulate the output voltage by fixing the switching frequency and controlling the converter duty-cycle. A Maximum Efficiency Point Tracking (MEPT) control scheme was proposed regulation. The first two techniques are based on the behavior of an open-loop IPTS which presents two peaks near the split frequencies in the "over coupled" region, as depicted in Figure 7. In particular, LFC (HFC) controls the inverter switching frequency on the left (right) side of the low (high) split frequency to regulate the IPTS output voltage. Conversely, the pre-(post-) regulation scheme adopts a DC/DC converter on the primary (secondary) IPT side to regulate the output voltage by fixing the switching frequency and controlling the converter duty-cycle. A Maximum Efficiency Point Tracking (MEPT) control scheme was proposed based on the use of a both pre-and post-regulating DC/DC converter (see Figure 8), where the output voltage regulation is accomplished by the postregulator controller, while the maximum efficiency is achieved by the pre-regulator controller. Figure 7. Illustration of the IPTS voltage gain and efficiency including split frequencies [16]. Eventually, Ref. [26] presented an MEPT algorithm for the post-regulated IPTS to match the load impedance to that of the source impedance. The proposed algorithm varies both the switching frequency and the phase-shift of the inverter to minimize the input power, whereas the output power is kept constant by a buck converter, which is used to regulate the battery voltage and current. The drawback of the proposed study is that, during the buck controller design, the influence of the IPTS on the duty-to-output transfer function of the buck converter is not taken into account.
In this paper, we overcome such a limitation by correctly modeling the post-regulator dynamics accounting for the IPTS connected to its input. To this end, we exploit the findings of [27] which used Coupled-Mode Theory (CMT) to deal with the dynamic modeling of the IPTS pre-regulated by a buck converter. Such an approach uses slowly varying amplitudes and phases of coupled modes, rather than resonant currents and voltages, to model the coupled resonances of the IPT stage. It also includes the non-linearities of the inverter and rectifier stages operating at a full square-wave voltage under IPTS resonant conditions. A continuation of [27] can be found in [28], where the steady-state and dynamic characteristics of an open-loop IPTS post-regulated by a buck-boost converter are investigated by means of the CMT. It is shown that, for certain operating conditions and system component values, the steady-state control-to-output curve of the post-regulator can be non-monotonic, since its static and dynamic characteristics are tightly coupled to the IPT stage. In particular, when the control-to-output curve changes its slope and starts regulation. The first two techniques are based on the behavior of an open-loop IPTS which presents two peaks near the split frequencies in the "over coupled" region, as depicted in Figure 7. In particular, LFC (HFC) controls the inverter switching frequency on the left (right) side of the low (high) split frequency to regulate the IPTS output voltage. Conversely, the pre-(post-) regulation scheme adopts a DC/DC converter on the primary (secondary) IPT side to regulate the output voltage by fixing the switching frequency and controlling the converter duty-cycle. A Maximum Efficiency Point Tracking (MEPT) control scheme was proposed based on the use of a both pre-and post-regulating DC/DC converter (see Figure 8), where the output voltage regulation is accomplished by the postregulator controller, while the maximum efficiency is achieved by the pre-regulator controller. Figure 7. Illustration of the IPTS voltage gain and efficiency including split frequencies [16]. Eventually, Ref. [26] presented an MEPT algorithm for the post-regulated IPTS to match the load impedance to that of the source impedance. The proposed algorithm varies both the switching frequency and the phase-shift of the inverter to minimize the input power, whereas the output power is kept constant by a buck converter, which is used to regulate the battery voltage and current. The drawback of the proposed study is that, during the buck controller design, the influence of the IPTS on the duty-to-output transfer function of the buck converter is not taken into account.
In this paper, we overcome such a limitation by correctly modeling the post-regulator dynamics accounting for the IPTS connected to its input. To this end, we exploit the findings of [27] which used Coupled-Mode Theory (CMT) to deal with the dynamic modeling of the IPTS pre-regulated by a buck converter. Such an approach uses slowly varying amplitudes and phases of coupled modes, rather than resonant currents and voltages, to model the coupled resonances of the IPT stage. It also includes the non-linearities of the inverter and rectifier stages operating at a full square-wave voltage under IPTS resonant conditions. A continuation of [27] can be found in [28], where the steady-state and dynamic characteristics of an open-loop IPTS post-regulated by a buck-boost converter are investigated by means of the CMT. It is shown that, for certain operating conditions and system component values, the steady-state control-to-output curve of the post-regulator can be non-monotonic, since its static and dynamic characteristics are tightly coupled to the IPT stage. In particular, when the control-to-output curve changes its slope and starts Eventually, Ref. [26] presented an MEPT algorithm for the post-regulated IPTS to match the load impedance to that of the source impedance. The proposed algorithm varies both the switching frequency and the phase-shift of the inverter to minimize the input power, whereas the output power is kept constant by a buck converter, which is used to regulate the battery voltage and current. The drawback of the proposed study is that, during the buck controller design, the influence of the IPTS on the duty-to-output transfer function of the buck converter is not taken into account.
In this paper, we overcome such a limitation by correctly modeling the post-regulator dynamics accounting for the IPTS connected to its input. To this end, we exploit the findings of [27] which used Coupled-Mode Theory (CMT) to deal with the dynamic modeling of the IPTS pre-regulated by a buck converter. Such an approach uses slowly varying amplitudes and phases of coupled modes, rather than resonant currents and voltages, to model the coupled resonances of the IPT stage. It also includes the non-linearities of the inverter and rectifier stages operating at a full square-wave voltage under IPTS resonant conditions. A continuation of [27] can be found in [28], where the steady-state and dynamic characteristics of an open-loop IPTS post-regulated by a buck-boost converter are investigated by means of the CMT. It is shown that, for certain operating conditions and system component values, the steady-state control-to-output curve of the post-regulator can be non-monotonic, since its static and dynamic characteristics are tightly coupled to the IPT stage. In particular, when the control-to-output curve changes its slope and starts decreasing, the system runs into positive feedback and goes out of control. In this paper, we enhance the modeling procedure proposed in [27,28] by including the inverter phase-shift modulation and by extending its validity to whatever operating frequency. Such an enhanced procedure is herein formulated for the buck post-regulator, but its findings are general and can also be applied to other basic converter topologies (e.g., boost, buck-boost, etc.).
A comparison between the main IPTS solutions discussed previously and the system developed in this work is subsequently provided in the Section 4.4, highlighting their relevant features and specifications. Figure 9 shows a schematic of a Post-Regulated IPTS (PR-IPTS) using a series-series compensation topology. The coupling coils, represented by the self-inductances L 1 and L 2 , are compensated with the series capacitors C 1 and C 2 . The magnetic coupling between the coils is represented by their mutual inductance M. The TX coil is connected to the source through a MOSFET full-bridge inverter implementing a phase-shift and frequency modulation, with the objective of maximizing the overall system efficiency. The phaseshift modulation consists of modulating the phase angle α between the complementary square-wave gate signal pairs used to control the MOSFETs of the two inverter legs, as depicted in Figure 10. As a result, a modified square-wave voltage v 1 (t) is obtained at the inverter output (indicated by the green waveform in Figure 10). The resistor R 1 includes the equivalent resistances of L 1 , C 1 and of the two inverter MOSFETs conducting simultaneously.

Post-Regulated IPTS (PR-IPTS)
shift modulation and by extending its validity to whatever operating frequency. Such an enhanced procedure is herein formulated for the buck post-regulator, but its findings are general and can also be applied to other basic converter topologies (e.g., boost, buckboost, etc.).
A comparison between the main IPTS solutions discussed previously and the system developed in this work is subsequently provided in the Section 4.4, highlighting their relevant features and specifications. Figure 9 shows a schematic of a Post-Regulated IPTS (PR-IPTS) using a series-series compensation topology. The coupling coils, represented by the self-inductances L1 and L2, are compensated with the series capacitors C1 and C2. The magnetic coupling between the coils is represented by their mutual inductance M. The TX coil is connected to the source through a MOSFET full-bridge inverter implementing a phase-shift and frequency modulation, with the objective of maximizing the overall system efficiency. The phase-shift modulation consists of modulating the phase angle α between the complementary squarewave gate signal pairs used to control the MOSFETs of the two inverter legs, as depicted in Figure 10. As a result, a modified square-wave voltage v1(t) is obtained at the inverter output (indicated by the green waveform in Figure 10). The resistor R1 includes the equivalent resistances of L1, C1 and of the two inverter MOSFETs conducting simultaneously.  The RX coil is connected to the resistive load RL through a MOSFET full-bridge rectifier followed by a buck DC/DC converter implementing a duty-cycle D control at a fixed switching frequency fBuck. Such control aims to regulate the system output voltage Vo at a desired nominal value Vo,nom, under both static and dynamic load conditions. As a result shift modulation and by extending its validity to whatever operating frequency. Such an enhanced procedure is herein formulated for the buck post-regulator, but its findings are general and can also be applied to other basic converter topologies (e.g., boost, buckboost, etc.).

Post-Regulated IPTS (PR-IPTS)
A comparison between the main IPTS solutions discussed previously and the system developed in this work is subsequently provided in the Section 4.4, highlighting their relevant features and specifications. Figure 9 shows a schematic of a Post-Regulated IPTS (PR-IPTS) using a series-series compensation topology. The coupling coils, represented by the self-inductances L1 and L2, are compensated with the series capacitors C1 and C2. The magnetic coupling between the coils is represented by their mutual inductance M. The TX coil is connected to the source through a MOSFET full-bridge inverter implementing a phase-shift and frequency modulation, with the objective of maximizing the overall system efficiency. The phase-shift modulation consists of modulating the phase angle α between the complementary squarewave gate signal pairs used to control the MOSFETs of the two inverter legs, as depicted in Figure 10. As a result, a modified square-wave voltage v1(t) is obtained at the inverter output (indicated by the green waveform in Figure 10). The resistor R1 includes the equivalent resistances of L1, C1 and of the two inverter MOSFETs conducting simultaneously.  The RX coil is connected to the resistive load RL through a MOSFET full-bridge rectifier followed by a buck DC/DC converter implementing a duty-cycle D control at a fixed switching frequency fBuck. Such control aims to regulate the system output voltage Vo at a desired nominal value Vo,nom, under both static and dynamic load conditions. As a result The RX coil is connected to the resistive load R L through a MOSFET full-bridge rectifier followed by a buck DC/DC converter implementing a duty-cycle D control at a fixed switching frequency f Buck . Such control aims to regulate the system output voltage V o at a desired nominal value V o,nom , under both static and dynamic load conditions. As a result of the presence of the buck converter, the equivalent DC resistance seen at the rectifier output is given by (1):

Post-Regulated IPTS (PR-IPTS)
where M(D) = V o /V 2dc = D represents the buck conversion ratio while V 2dc is the intermediate bus voltage between the rectifier and the buck. The resistor R 2 includes the equivalent resistances of L 2 , C 2 and of the two rectifier MOSFETs conducting simultaneously. A synchronous rectification scheme has been herein adopted for the full-bridge rectifier, in which each MOSFET is turned on after a short conduction of the relative body-diode (as soon as its drain-source voltage decreases below a given negative threshold), and is turned off when its drain-source voltage exceeds the threshold [29]. Thus, the conduction losses can be reduced as compared to the passive diode bridge configuration [30].

Static Modeling of PR-IPTS
The above PR-IPTS has been modeled using an FHA method, since the primary and the secondary coil currents are nearly sinusoidal, and only the first harmonics of the voltages (v 1 (t), v 2 (t)) and currents (i L1 (t), i L2 (t)) contribute to the power transfer. Such FHA quantities can be represented through their respective phasors As a result of the phase-shift modulation, the peak amplitude of the primary voltage phasor is given by (2): The FHA allows to model the power electronics connected to the RX side with an equivalent AC resistance R ac , expressed as the ratio between the amplitudes of the first harmonics of voltage and current at the input of the rectifier bridge [1]: Under FHA assumption, the analyzed IPTS can be described with the following phasor equation system (4): where ω s = 2πf s represents the angular switching frequency of the inverter. For a certain value of the intermediate bus voltage V 2dc , the equivalent resistance R ac , seen by the IPT secondary side, can be evaluated using (1) and (3), while the peak amplitude of the secondary voltage first harmonic is given by (5): If the phase φ V2 is taken as a zero reference for the phase angles, the phasor V 2 = V 2 is known, and the equation system (4) can be solved to obtain the remaining phasors, as given in (6): Starting from (6), it is possible to evaluate the peak amplitude of the primary voltage first harmonic V 1 , and estimate the resulting phase-shift α by inverting (2): If the resulting α value is real and included in the range [0, π], the analyzed operating condition (relative to the considered V 2dc value) is feasible, and the primary and secondary IPT average powers P 1 and P 2 can be evaluated according to (8): Note that such average powers do not take into account the inverter switching losses, the coils ferrite core losses and the post-regulator losses, since simplified FHA modeling do not allow for including such loss contributions. However, the above approach does enable the evaluation of the overall system behavior under different operating conditions of f s and V 2dc , which are the two main parameters used herein to optimize the IPTS efficiency η = P 2 /P 1 .

Compensation Capacitors Selection
For a given TX and RX coil set, the IPTS power and efficiency levels depend on the selected values of the compensation capacitors C 1 and C 2 , as highlighted by the IPTS modeling solution (5)- (8). Given the IPTS operating parameters and component values listed in Table 1, Equations (5) Table 1 will be subsequently described. Note that the analyzed IPTS has been herein designed to deliver an average output power of approximately 20 W at a regulated output voltage of 12 V to a resistive load of 7 Ω, but different output power levels are also feasible and will be tested in the experimental section of this paper. Figure 11 depicts the simulated IPTS efficiency η (Figure 11a), the primary coil rms current I L1rms = I L1 / √ 2 (Figure 11b), and the normalized phase-shift d = α/π (Figure 11c,d)), for C 1 = 100 nF (solid lines) and C 1 = 200 nF (dashed lines). Note that only the TX coil rms current is shown in Figure 11b, since the RX coil current does not depend on the C 1 , C 2 and f s values. The plots of Figure 11c,d highlight the fact that the phase-shift changes with both C 1 and C 2 , since it is dependent on the V 1 solution in (6). The points with d = 0 represent unfeasible operating conditions for which the output voltage regulation cannot be achieved. The plots of Figure 11a,b show that η and I 1rms levels only depend on C 2 , while C 1 determines the operating ranges wherein the IPTS modeling solution is feasible (α ∈ [0, π] or d ∈ [0, 1]). The capacitor values C 1 = 100 nF and C 2 = 50 nF enable achieving the highest simulated efficiency (red solid curve in Figure 11a) at high frequencies, where the converters switching losses and the coils ferrite losses are likely to become high. For this reason, the optimal choice is C 2 = 100 nF (green curve) allowing to maximize the efficiency at~120 kHz, with both C 1 = 100 nF and 200 nF.

Static Modeling Results
Once the optimal compensation capacitor values have been selected, the IPTS modeling solution (5)- (8) has been evaluated over the ranges V2dc = [14,20] V and fs = [60, 160] kHz, in order to determine the optimal parameter values maximizing the overall IPTS efficiency. Note that, in practice, a certain value of V2dc can be achieved through the inverter phase-shift modulation (for a given value of fs), either in an open-loop fashion or through the closed-loop feedback control. However, the latter would require a communication link between the IPT primary and secondary side; therefore, the open-loop strategy has been adopted herein.
Two different capacitor set-ups, identified as the optimal ones in the previous subsection, have been analyzed and compared: {C1 = 100 nF, C2 = 100 nF} and {C1 = 200 nF, C2 = 100 nF}. Figure 12 depicts the simulated IPTS efficiency η (Figure 12a), the rms currents IL1rms (solid lines) and IL2rms (dashed lines) of the TX and RX coil, respectively (Figure 12b), the IPT stage voltage gain V2/V1 (Figure 12c) and the normalized phase-shift d (Figure 12d), for the first capacitor set-up {C1 = 100 nF, C2 = 100 nF}. The plot of Figure 12a highlights that, for different frequencies, the simulated efficiency can be maximized at different levels of V2dc (different line colors in the plots). For this set-up, the maximum value ηmax = 0.9845 has been obtained at V2dc = 15 V and fs = 115 kHz. Figure 12b shows that the secondary coil rms current level (dashed lines) does not depend on the frequency, since it only depends on V2dc and Rac values, as described by (6). Figure 12c highlights the fact that the IPTS voltage gain is independent of V2dc (and hence of Rac) at two split frequencies [28]:

Static Modeling Results
Once the optimal compensation capacitor values have been selected, the IPTS modeling solution (5)- (8) has been evaluated over the ranges V 2dc = [14,20] V and f s = [60, 160] kHz, in order to determine the optimal parameter values maximizing the overall IPTS efficiency. Note that, in practice, a certain value of V 2dc can be achieved through the inverter phaseshift modulation (for a given value of f s ), either in an open-loop fashion or through the closed-loop feedback control. However, the latter would require a communication link between the IPT primary and secondary side; therefore, the open-loop strategy has been adopted herein.
Two different capacitor set-ups, identified as the optimal ones in the previous subsection, have been analyzed and compared: {C 1 = 100 nF, C 2 = 100 nF} and {C 1 = 200 nF, C 2 = 100 nF}. Figure 12 depicts the simulated IPTS efficiency η (Figure 12a), the rms currents I L1rms (solid lines) and I L2rms (dashed lines) of the TX and RX coil, respectively (Figure 12b), the IPT stage voltage gain V 2 /V 1 (Figure 12c) and the normalized phase-shift d (Figure 12d), for the first capacitor set-up {C 1 = 100 nF, C 2 = 100 nF}. The plot of Figure 12a highlights that, for different frequencies, the simulated efficiency can be maximized at different levels of V 2dc (different line colors in the plots). For this set-up, the maximum value η max = 0.9845 has been obtained at V 2dc = 15 V and f s = 115 kHz. Figure 12b shows that the secondary coil rms current level (dashed lines) does not depend on the frequency, since it only depends on V 2dc and R ac values, as described by (6). Figure 12c highlights the fact that the IPTS voltage gain is independent of V 2dc (and hence of R ac ) at two split frequencies [28]: where ω 1 = 2πf 1 = 1/ √ L 1 C 1 and ω 2 = 2πf 2 = 1/ √ L 2 C 2 are the primary and the secondary side angular resonant frequencies. For the capacitor set-up of Figure 12, the split frequencies are located in f L = 85 kHz and f R = 153 kHz. As will be explained in the next section, operating at the right-side split frequency f R can be beneficial in terms of better controllability of the post-regulated IPTS, while maintaining high efficiency due to the ZVS inverter operation [31]. Finally, the blue rectangle in Figure 12d highlights a frequency region (from approximately 95 kHz to approximately 125 kHz) wherein the V 2dc voltage decreases as the normalized phase-shift d increases. This behavior could determine an instable operation region for the buck controller wherein the regulation of the buck output voltage could be lost, as will be explained hereafter. Hence, it could be impossible to exploit the maximum efficiency over such a frequency range, while operating the IPTS at higher frequencies could lead to decreased efficiency due to the increasing switching and ferrite losses.
where ω1 = 2πf1 = 1/√ 1 1 and ω2 = 2πf2 = 1/√ 2 2 are the primary and the secondary side angular resonant frequencies. For the capacitor set-up of Figure 12, the split frequencies are located in fL = 85 kHz and fR = 153 kHz. As will be explained in the next section, operating at the right-side split frequency fR can be beneficial in terms of better controllability of the post-regulated IPTS, while maintaining high efficiency due to the ZVS inverter operation [31]. Finally, the blue rectangle in Figure 12d highlights a frequency region (from approximately 95 kHz to approximately 125 kHz) wherein the V2dc voltage decreases as the normalized phase-shift d increases. This behavior could determine an instable operation region for the buck controller wherein the regulation of the buck output voltage could be lost, as will be explained hereafter. Hence, it could be impossible to exploit the maximum efficiency over such a frequency range, while operating the IPTS at higher frequencies could lead to decreased efficiency due to the increasing switching and ferrite losses.    (Figure 13a), the rms currents I L1rms (solid lines) and the I L2rms (dashed lines) of the TX and RX coils, respectively (Figure 13b), the IPTS voltage gain V 2 /V 1 (Figure 13c) and the normalized phase-shift d (Figure 13d), for the second capacitor set-up {C 1 = 200 nF, C 2 = 100 nF}. Also for this configuration, the maximum value η max = 0.9845 has been obtained at V 2dc = 15 V and f s = 115 kHz, since C 1 does not influence the maximum efficiency but the feasible frequency range over which such efficiency can be obtained. The split frequencies, for which the IPTS voltage gain is independent of the load, are now located in f L = 68 kHz and f R = 135 kHz. Again, the blue rectangle in Figure 13d highlights a frequency region (from approximately 70 kHz to approximately 100 kHz), wherein the V 2dc voltage decreases as the normalized phaseshift d increases, over which the buck controller could lose the capability of regulating the output voltage, as explained in the following section. However, compared to the capacitor set-up of Figure 12, now such a critical frequency region is shifted to the left, thus allowing to exploit the maximum efficiency operating conditions around the f s = 115 kHz point. Hence, the optimal compensation capacitor set-up selected herein is {C 1 = 200 nF, C 2 = 100 nF}, resulting in the following values of the primary and secondary resonant frequencies f 1 = 74 kHz and f 2 = 105 kHz.

PR-IPTS Controllability Assessment
The modeling results presented in the previous section are based on the assumption that the buck converter correctly regulates its output voltage for all the analyzed conditions of the inverter switching frequency fs and the intermediate bus voltage V2dc. However, the control characteristics of a post-regulator cascaded to an IPTS are quite different from a standalone DC/DC converter [28]. This is due to the fact that, as the post-regulator duty-cycle D increases, the equivalent resistance Rac seen by the IPT stage decreases, and the intermediate bus voltage

PR-IPTS Controllability Assessment
The modeling results presented in the previous section are based on the assumption that the buck converter correctly regulates its output voltage for all the analyzed conditions of the inverter switching frequency f s and the intermediate bus voltage V 2dc . However, the control characteristics of a post-regulator cascaded to an IPTS are quite different from a standalone DC/DC converter [28]. This is due to the fact that, as the post-regulator duty-cycle D increases, the equivalent resistance R ac seen by the IPT stage decreases, and the intermediate bus voltage V 2dc can either increase or decrease in function of the IPTS response to the equivalent load variation. Hence, the converter output voltage V o = V 2dc ·M(D) can increase or decrease with the duty-cycle, in function of the amount of V 2dc · and M(D) variation with D. Under certain operating conditions, the output voltage can become non-monotonic with respect to the duty-cycle, which means that the resulting Bode diagram varies significantly with the operating point. This may lead to difficulties in closed-loop control. In this section, we solve the PR-IPTS equations with the buck converter operating in open-loop and show that the non-monotonic behavior of the output voltage with duty-cycle occurs within the operating regions highlighted with blue rectangles in Figures 12d and 13d.
Let us assume that the PR-IPTS is operating in open loop with the buck duty-cycle varying in the range D = [0.1, 0.9]. The system equation (4) is still valid, but the output voltage V o is no more regulated at its nominal value. The equivalent AC resistance R ac seen at the rectifier input changes with the duty-cycle according to (1) and (3), thus varying the IPTS operating point. Let us also assume that the inverter normalized phase-shift d is varied in the range d = [0. 1,1]. For each value of d, the primary voltage peak V 1 is given by (2) and, if the phase φ V1 is taken as a zero reference for the phase angles, the phasor V 1 = V 1 is known, and the equation system (4) can be solved to obtain the remaining phasors, as given in (10): Starting from the result of (10), the voltage V 2dc can be estimated by inverting (5), and the resulting output voltage can be obtained for each analyzed value of D as V o = V 2dc ·D. Figure 14 shows the values of V o and V 2dc for the capacitor set-up {C 1 = 200 nF, C 2 = 100 nF}, obtained over the given ranges of D and d for f s values in the interval [70, 135] kHz. It can be observed that at f s = 70 kHz (Figure 14a), V o is non-monotonic with respect to D, while V 2dc reaches very high levels for low duty-cycle values (high R ac ). Such a condition could result in an unstable controller behavior within the positive feedback region located at the right-hand-side of the V o vs. D curve peak. In this region, an increase in D would result in a decrease in V o , and the controller would try to further increase D until saturating its value at the maximum allowed limit. Hence, the output voltage regulation would be lost. Similarly, a decrease in D would cause an increase in V o , and the controller would try to further decrease the duty-cycle, until reaching the V o vs. D curve peak and going to the negative feedback region. In principle, in such a region the controller could be able to guarantee the output voltage regulation, but V 2dc may increase to very high levels, causing possible component failures (such as capacitors, buck converter MOSFETs and relative gate drivers, etc.). Hence, the system operation under conditions resulting in a non-monotonic control-to-output characteristic should be avoided. At f s = 90 kHz (Figure 14b), V o is still non-monotonic with respect to D but V 2dc assumes lower values, while at f s = 110 kHz (Figure 14c), V o becomes monotonic resulting in a correct controller behavior. These findings are in agreement with the results of Figure 13d, where the IPTS operation in the range [70, 100] kHz is not recommended because of the inversion of the V 2dc vs. d trend. Eventually, the plots of Figure 14d depict V o and V 2dc for f s = 135 kHz (corresponding to the right-hand-side split frequency f R ), highlighting that V 2dc (and consequently, the IPTS gain V 2 /V 1 ) is independent of the duty-cycle D (or, equivalently, of R ac ), which is in agreement with the results of Figure 13c. Hence, operating IPTS at f R can be convenient if the load variations occur, but the overall system efficiency may decrease somewhat (as can be seen in Figure 13a). To maximize the efficiency, IPTS should be operated at f s = 115 kHz, which is still a feasible condition located in the stable frequency region, as previously shown in Figure 13d. in Figure 13a). To maximize the efficiency, IPTS should be operated at fs = 115 kHz, which is still a feasible condition located in the stable frequency region, as previously shown in Figure 13d.

Dynamic Modeling and Control of PR-IPTS
In this section, we describe the dynamic modeling of the PR-IPTS based on CMT, similarly to the research developed in [27]. In contrast to the findings of [27], which are valid for a full square-wave inverter operation under resonance conditions, we propose the modified modeling including the inverter phase-shift modulation which is valid for whatever switching frequency. As one of the modeling outputs, we obtained the duty-tooutput transfer function of the post-regulator, necessary for the design of the digital controller as discussed hereafter. Figure 15 shows the AC equivalent circuit of the IPT stage of Figure 9, where v1 and v2 are considered to be the exciting source and sink, respectively. The dynamics of such an equivalent circuit can be described by the equation system (11):

Dynamic Modeling and Control of PR-IPTS
In this section, we describe the dynamic modeling of the PR-IPTS based on CMT, similarly to the research developed in [27]. In contrast to the findings of [27], which are valid for a full square-wave inverter operation under resonance conditions, we propose the modified modeling including the inverter phase-shift modulation which is valid for whatever switching frequency. As one of the modeling outputs, we obtained the dutyto-output transfer function of the post-regulator, necessary for the design of the digital controller as discussed hereafter. Figure 15 shows the AC equivalent circuit of the IPT stage of Figure 9, where v 1 and v 2 are considered to be the exciting source and sink, respectively. The dynamics of such an equivalent circuit can be described by the equation system (11): As a result of the phase-shift modulation (see Figure 10), the inverter output voltage v1(t) can be described by (12): As a result of the phase-shift modulation (see Figure 10), the inverter output voltage v 1 (t) can be described by (12):

Dynamic Modeling of IPT Stage
The rectifier input voltage v 2 (t) is determined by the secondary coil current direction: According to the CMT, the IPT coil currents i Ln (t) and the compensation capacitor voltages v Cn (t) (n = 1, 2) can be represented as given in (14): L n a n sin(ω s t + θ n ) (14b) where a n and θ n are the amplitudes and phases of the coupled modes representing the state of the primary and secondary resonators. Such variables are assumed to vary slowly with time. Let us note that (14b) has been modified compared to the formulation given in [27], so as to extend its validity to whatever operating frequency. Using (14), the derivatives of the resonant voltages and currents become: dt cos(ω s t + θ n ) − a n ω s + dθ n dt sin(ω s t + θ n ) dv Cn dt = 2 C n da n dt sin(ω s t + θ n ) + a n ω s + dθ n dt cos(ω s t + θ n ) By substituting (15) into (11), it is possible to derive the dynamic equations of the amplitudes and phases of the coupled modes: Note that (12) and (13) should be used in (16) to describe v 1 (t) and v 2 (t), respectively. Assuming that the slowly varying variables in (16)-a n and θ n (n = 1, 2)-are constant during a buck switching period T Buck = 1/f Buck , the time-invariant averaged model can be obtained by taking the average values of both sides of (16) over T Buck : while the " · " operator denotes the averaged values of the relevant quantities over T Buck . The averaged model (17) can be represented in a more compact form (18): where: and f n (n = 1, . . . , 4) is the right-hand-side expression of the n-th equation in (17). The averaged value over T Buck of the current at the diode bridge output is given by (20): Denoting the small-signal variations of the state variables and of the IPT input and output voltages asâ n ,θ n andv n (n = 1, 2), the linearized small-signal model of the IPT stage can be described by (21): where:x According to (20), the small signal variation of the IPT stage output current is:

Small-Signal Modeling of PR-IPTS
Using the IPTS dynamic model presented thus far, it is possible to develop a systemlevel PR-IPTS model by combining Equations (18)-(23) with the differential equations of the post-regulator. Figure 16 depicts an averaged small-signal equivalent circuit of the buck converter, where the PWM switching cell is replaced with an equivalent two-port AC model described by (24):î The small-signal variation of the buck output voltage can be described by (25): which yields (26): Using (23) and (24a), the dynamic equation of the intermediate bus capacitor Cf can be expressed as given in (27): Using (26), the dynamic equation of the buck output capacitor Co can be expressed as given in (28): Using (24b) and (27), the dynamic equation of the buck inductor Lo can be obtained: By combining the IPTS dynamic model (21) with Equations (26)- (29), the seventhorder small-signal model of the PR-IPTS is developed: where: Figure 16. Averaged small-signal equivalent circuit of the buck converter.
The "ˆ" operator in (24) denotes the small-signal variations of the considered quantities (note that the duty-cycle variationd is different from the normalized phase-shift d used previously).
The small-signal variation of the buck output voltage can be described by (25): which yields (26): (26) Using (23) and (24a), the dynamic equation of the intermediate bus capacitor C f can be expressed as given in (27): Using (26), the dynamic equation of the buck output capacitor C o can be expressed as given in (28): Using (24b) and (27), the dynamic equation of the buck inductor L o can be obtained: By combining the IPTS dynamic model (21) with Equations (26)- (29), the seventh-order small-signal model of the PR-IPTS is developed: where: Note that in (30), the IPTS input voltage is considered constant with time (v in = 0). From (30), the state-space solution of the system can be obtained aŝ The steady-state operating point of the IPT stage, needed to evaluate (32), can be obtained from the FHA modeling solution (6) presented in the previous section, according to (33): where I L1 , I L2 , φ IL1 and φ IL2 are the amplitudes and phases of the primary and secondary current phasors I L1 and I L2 in (6). Let us note that, to evaluate the phase angles θ 1 and θ 2 , all the phase angles obtained from (6) should be decremented by φ V1 (i.e., the phase of the primary voltage phasor V 1 ), since in the CMT formulation such φ V1 term is considered null. Equation (32b) allows to evaluate the duty-to-output transfer function of the buck converter connected to the IPTS: As previously discussed, under certain operating conditions, the buck output voltage can become non-monotonic with respect to the duty-cycle, leading to difficulties in the closed-loop control. Figure 17 depicts the Bode plot of G vd (s) for the operating point {f s = 70 kHz, V 2dc = 14 V} located in the unstable region highlighted in Figure 13d, for the buck parameters listed in Table 2. Indeed, the resulting phase of G vd (s) is close to −180 • at low frequencies, because of the negative static gain G vd0 . This means that the increase in the duty-cycle will lead to the decrease in the output voltage, which is in agreement with the plot of Figure 14a highlighting a non-monotonic V o vs. D static characteristic. Figure 18 depicts the Bode plot of G vd (s) for the operating point {f s = 110 kHz, V 2dc = 14 V} located in the stable region of Figure 13d. Under such conditions, the static gain G vd0 is positive, and the V o vs. D static characteristic is monotonic (see Figure 14c). Hence, this last operating point is feasible for the practical controller design discussed hereafter.

Digital Voltage Mode Control Design of Post-Regulator
To achieve the buck output voltage regulation, a Digital Voltage Mode Control (DVMC) has been adopted, whose functional schematic is shown in Figure 19. To properly design the DVMC, the analog version of the controller has been first developed and subsequently transformed into its digital version. The block diagram representation of the analog VMC is shown in Figure 20, which utilizes a single feedback loop to regulate the output voltage at the desired reference value. The blue box represents the dynamic model of the buck converter including its main transfer functions. The controlto-output transfer function Gvd(s) is provided in (34), while the transfer functions Gvi(s) and Zo(s) can be obtained through the same modeling procedure. The block Gpwm = 1/Vpp represents the PWM gain, where Vpp is the peak-to-peak amplitude of the PWM sawtooth signal (herein, Vpp = 1 V has been used).
The analog controller Gva(s) has been designed by the K-factor method [32], to obtain a given phase margin of the compensated loop transfer function Tc(s) = Gva(s)·Gpwm·G vd(s) at the desired crossover frequency, ensuring the closed-loop system stability.

Digital Voltage Mode Control Design of Post-Regulator
To achieve the buck output voltage regulation, a Digital Voltage Mode Control (DVMC) has been adopted, whose functional schematic is shown in Figure 19. To properly design the DVMC, the analog version of the controller has been first developed and subsequently transformed into its digital version. The block diagram representation of the analog VMC is shown in Figure 20, which utilizes a single feedback loop to regulate the output voltage at the desired reference value. The blue box represents the dynamic model of the buck converter including its main transfer functions. The controlto-output transfer function Gvd(s) is provided in (34), while the transfer functions Gvi(s) and Zo(s) can be obtained through the same modeling procedure. The block Gpwm = 1/Vpp represents the PWM gain, where Vpp is the peak-to-peak amplitude of the PWM sawtooth signal (herein, Vpp = 1 V has been used).
The analog controller Gva(s) has been designed by the K-factor method [32], to obtain a given phase margin of the compensated loop transfer function Tc(s) = Gva(s)·Gpwm·G vd(s) at the desired crossover frequency, ensuring the closed-loop system stability.

Digital Voltage Mode Control Design of Post-Regulator
To achieve the buck output voltage regulation, a Digital Voltage Mode Control (DVMC) has been adopted, whose functional schematic is shown in Figure 19. To properly design the DVMC, the analog version of the controller has been first developed and subsequently transformed into its digital version. The block diagram representation of the analog VMC is shown in Figure 20, which utilizes a single feedback loop to regulate the output voltage at the desired reference value. The blue box represents the dynamic model of the buck converter including its main transfer functions. The controlto-output transfer function G vd (s) is provided in (34), while the transfer functions G vi (s) and Z o (s) can be obtained through the same modeling procedure. The block G pwm = 1/V pp represents the PWM gain, where V pp is the peak-to-peak amplitude of the PWM sawtooth signal (herein, V pp = 1 V has been used).
The analog controller G va (s) has been designed by the K-factor method [32], to obtain a given phase margin of the compensated loop transfer function T c (s) = G va (s)·G pwm ·G vd (s) at the desired crossover frequency, ensuring the closed-loop system stability.  Referring to the duty-to-output transfer function of Figure 18, a crossover frequency of fBuck/20 = 5 kHz and a phase margin of 52° have been set, yielding the third-order controller (35) whose coefficients are listed in Table 3: To obtain the digital version of such a controller, the Tustin transform (36) has been adopted: where the sampling frequency fsamp has been set equal to the buck switching frequency fBuck, so as to synchronize the sampling process with respect to the switching of the converter. Substituting (36) into (35) provides the digital controller transfer function Gva(z) given in (37), whose coefficients are listed in Table 4: Figure 19. DVMC of the buck converter.  Referring to the duty-to-output transfer function of Figure 18, a crossover frequency of fBuck/20 = 5 kHz and a phase margin of 52° have been set, yielding the third-order controller (35) whose coefficients are listed in Table 3: To obtain the digital version of such a controller, the Tustin transform (36) has been adopted: where the sampling frequency fsamp has been set equal to the buck switching frequency fBuck, so as to synchronize the sampling process with respect to the switching of the converter. Substituting (36) into (35) provides the digital controller transfer function Gva(z) given in (37), whose coefficients are listed in Table 4: Referring to the duty-to-output transfer function of Figure 18, a crossover frequency of f Buck /20 = 5 kHz and a phase margin of 52 • have been set, yielding the third-order controller (35) whose coefficients are listed in Table 3: To obtain the digital version of such a controller, the Tustin transform (36) has been adopted: where the sampling frequency f samp has been set equal to the buck switching frequency f Buck , so as to synchronize the sampling process with respect to the switching of the converter.
Substituting (36) into (35) provides the digital controller transfer function G va (z) given in (37), whose coefficients are listed in Table 4: where K p is a scaling factor allowing to adapt the ADC resolution res ADC to the DPWM resolution res DPWM [33]: The ADC resolution is determined by the ADC full-scale value V FS and by the number of bits used for the quantization N bit : The DPWM resolution is determined by the number of discrete DPWM levels N DPWM : where N DPWM is determined by a fixed time resolution t res of the DPWM peripheral and by the desired buck switching frequency f Buck according to (41): where an edge-aligned mode of the DPWM peripheral has been adopted, which allows realizing a desired PWM period by counting from zero up to the N DPWM level and then starting a new period. Applying the inverse Z-transform to (37) yields the digital control law (42): Due to the sampling process, the sampled output voltage shows an additive delay, equal to half the sampling period, as compared to the original signal, which may lead to the phase margin erosion of the compensated loop gain T c (s) that can affect the system stability. Figure 21 shows the impact of the sampling delay on the Bode plots of T c (s), highlighting that the desired phase margin Pm = 52 • of T c (s) (blue curves) is decreased to Pm = 43 • in the delayed version of T c (s) (red curves). Nevertheless, the closed-loop system stability is still ensured with the acceptable values of both gain and phase margins.
Eventually, the absence of the limit cycle phenomenon has been verified for the proposed DPWM scheme. Limit cycles refer to the steady-state oscillations of v o (t) and other system variables at frequencies lower than the converter switching frequency, which may result from the presence of signal amplitude quantizers such as the ADC and DPWM modules in the feedback loop [34]. Referring to Figure 19, for a given duty-to-output DC gain G vd0 , the duty-to-feedback voltage DC gain is G vd0 H V . To prevent limit cycles, the change of the feedback voltage ∆V fb (t) determined by the minimum duty-cycle change ∆D min (corresponding to the DPWM resolution res DPWM ) has to be smaller than ADC resolution res ADC : The static gain G vd0 has been estimated by substituting s = 0 in (34). For the presented controller design, the aforementioned parameter values are listed in Table 5. Substituting such values into (43), the absence of the limit cycle has been ascertained. It is worth mentioning that the presence of the IPTS connected to the buck input has caused the static gain reduction as compared to the stand-alone buck regulator for which G vd0 is equal to the converter input voltage (herein V in = 14 V). This helped prevent the limit cycle onset which otherwise could occur in the digitally controlled buck converter. The static gain Gvd0 has been estimated by substituting s = 0 in (34). For the presented controller design, the aforementioned parameter values are listed in Table 5. Substituting such values into (43), the absence of the limit cycle has been ascertained. It is worth mentioning that the presence of the IPTS connected to the buck input has caused the static gain reduction as compared to the stand-alone buck regulator for which Gvd0 is equal to the converter input voltage (herein Vin = 14 V). This helped prevent the limit cycle onset which otherwise could occur in the digitally controlled buck converter.

IPT Coil Realization
To optimize the overall system performances while maintaining the limited coupling area, custom IPT coils have been herein realized by adopting ferrite pot cores and suitable litz-wires. These latter allow to reduce high-frequency skin and proximity effects in the windings, which could lead to an increase in the resulting AC resistance and power losses [35]. In particular, the Ferroxcube P36/22-3C91 pot cores made of 3C91 ferrite material have been adopted [36] and are depicted in Figure 22a. To realize the windings, litz-wire 170/40 has been used, which is composed of 170 strands of AWG #40 wire, recommended for the operating frequency range [100, 200] kHz. At 200 kHz, the resulting skin depth in the copper wire is higher than the litz-wire diameter dAWG#40, thus allowing to reduce the skin effect:

IPT Coil Realization
To optimize the overall system performances while maintaining the limited coupling area, custom IPT coils have been herein realized by adopting ferrite pot cores and suitable litz-wires. These latter allow to reduce high-frequency skin and proximity effects in the windings, which could lead to an increase in the resulting AC resistance and power losses [35]. In particular, the Ferroxcube P36/22-3C91 pot cores made of 3C91 ferrite material have been adopted [36] and are depicted in Figure 22a. To realize the windings, litz-wire 170/40 has been used, which is composed of 170 strands of AWG #40 wire, recommended for the operating frequency range [100, 200] kHz. At 200 kHz, the resulting skin depth δ skin in the copper wire is higher than the litz-wire diameter d AWG#40 , thus allowing to reduce the skin effect: where ρ Cu = 1.68 × 10 −8 Ω·m and µ Cu = 1.256629 × 10 −6 are the copper resistivity and magnetic permeability, respectively. The number of strands (N str = 170) allows for the rms current handling capability of the litz-wire given by (45): where J rms = 6 A/mm 2 represents the maximum allowable rms current density of the copper wire. Thus, the resulting I rms is sufficiently higher than the expected rms current levels in the coils depicted in Figure 13b (see the feasible frequency range from approximately 100 kHz to approximately 150 kHz). where Jrms = 6 A/mm 2 represents the maximum allowable rms current density of the copper wire. Thus, the resulting Irms is sufficiently higher than the expected rms current levels in the coils depicted in Figure 13b (see the feasible frequency range from approximately 100 kHz to approximately 150 kHz). Fifteen turns of the litz-wire 170/40 have been realized on each pot core, and the resulting self-inductances L1, L2 and the DC winding resistances RL1, RL2 have been measured by means of the Extech Instruments LCR200 Passive Component LCR Meter [37]. Such measurement data are listed in Table 6, together with the coupling coefficient values = √ /( 1 2 ) obtained between the two identical coils for three different air-gap lengths, namely lg = {1.5, 3, 6} mm. The air-gap lg = 3 mm has been herein selected for the final TX and RX coil set depicted in Figure 22c, since such a value yields sufficiently high selfinductances of the coils L1 = L2 = 23 µ H and a coupling coefficient k = 0.53, which is a good trade-off solution for the considered application.

PR-IPTS Boards
An experimental prototype of the proposed PR-IPTS has been assembled using the components listed in Table 7 (refer to Figures 12 and 22 for the IPTS and buck components, respectively). The realized custom Printed Circuit Boards (PCBs) of the IPT TX and RX stages are depicted in Figure 23, with the dimensions of 95 mm × 70 mm × 18 mm and 106 mm × 70 mm × 18 mm, respectively.  Fifteen turns of the litz-wire 170/40 have been realized on each pot core, and the resulting self-inductances L 1 , L 2 and the DC winding resistances R L1 , R L2 have been measured by means of the Extech Instruments LCR200 Passive Component LCR Meter [37]. Such measurement data are listed in Table 6, together with the coupling coefficient values k = M/(L 1 L 2 ) obtained between the two identical coils for three different air-gap lengths, namely l g = {1.5, 3, 6} mm. The air-gap l g = 3 mm has been herein selected for the final TX and RX coil set depicted in Figure 22c, since such a value yields sufficiently high selfinductances of the coils L 1 = L 2 = 23 µH and a coupling coefficient k = 0.53, which is a good trade-off solution for the considered application.

PR-IPTS Boards
An experimental prototype of the proposed PR-IPTS has been assembled using the components listed in Table 7 (refer to Figures 12 and 22 for the IPTS and buck components, respectively). The realized custom Printed Circuit Boards (PCBs) of the IPT TX and RX stages are depicted in Figure 23, with the dimensions of 95 mm × 70 mm × 18 mm and 106 mm × 70 mm × 18 mm, respectively. Table 7. PR-IPTS components.

Circuit Components Values
Inverter On the TX board, the switching frequency and phase-shift modulation of the fullbridge inverter has been digitally implemented through the Infineon 32-bit XMC1302-T038X0064AB microcontroller with ARM ® Cortex ® -M0 [38], which allows to properly configure the peripherals using the proprietary Integrated Development Environment (IDE) Dave Infineon ® [39]. Thus, two PWM signal pairs synchronized at the same switching frequency have been generated from two different DPWM peripherals of the Micro Controller Unit (MCU) and subsequently delivered to the IRS2106SPBF drivers of the two inverter legs [40]. Each PWM signal pair includes two complementary square-wave signals used to drive the high-and low-side MOSFETs of the respective leg, and a 100 ns dead-time has been introduced to prevent a cross-conduction of the switches. To realize a desired phase-shift angle, a delay has been added to the second PWM signal pair with respect to the first one. Both DPWM peripherals have a fixed time resolution tres = 15.625 ns, resulting in a number of discrete digital levels NDPWM which depends on the desired inverter switching frequency fs, according to (46): On the TX board, the switching frequency and phase-shift modulation of the fullbridge inverter has been digitally implemented through the Infineon 32-bit XMC1302-T038X0064AB microcontroller with ARM ® Cortex ® -M0 [38], which allows to properly configure the peripherals using the proprietary Integrated Development Environment (IDE) Dave Infineon ® [39]. Thus, two PWM signal pairs synchronized at the same switching frequency have been generated from two different DPWM peripherals of the Micro Controller Unit (MCU) and subsequently delivered to the IRS2106SPBF drivers of the two inverter legs [40]. Each PWM signal pair includes two complementary square-wave signals used to drive the high-and low-side MOSFETs of the respective leg, and a 100 ns dead-time has been introduced to prevent a cross-conduction of the switches. To realize a desired phase-shift angle, a delay has been added to the second PWM signal pair with respect to the first one. Both DPWM peripherals have a fixed time resolution t res = 15.625 ns, resulting in a number of discrete digital levels N DPWM which depends on the desired inverter switching frequency f s , according to (46): where a center-aligned mode of the DPWM peripherals has been set, which allows to realize a desired PWM period by first counting up from zero to the N DPWM level and then down to zero [38]. On the RX board, the DVMC of the buck converter has been realized through the Infineon 32-bit XMC4200-F64X256 microcontroller with the ARM ® Cortex ® -M4 [41]. Its main peripheral parameters of interest are provided in Table 5, where a high-resolution DPWM peripheral of the XMC4200 MCU has been adopted. The generated complementary DPWM signals are used to drive the buck MOSFETs M HS -M LS through the IRS2011SPBF gate driver [42]. Each of the rectifier MOSFETs M 1 -M 4 is switched by the respective IR1161LPBF controller [29], according to the synchronous rectification scheme previously described in Section 2.1.

Efficiency Assessment with Electronic Load
The developed PR-IPTS prototype has been tested under different load conditions to assess its power and efficiency performances and output voltage regulating capabilities for variable load demands. Figure 24 shows a complete experimental set-up used during the tests, including the TX and RX boards with the coupling coils, a BK Precision 9111 180 W Multi Range 60 V/8 A DC Power Supply connected to the IPTS input, an HP Agilent Keysight 6060B 300 W 60 A/60 V DC Electronic Load connected to the system output, and a Teledyne LeCroy HDO9404 Digital Oscilloscope.
The developed PR-IPTS prototype has been tested under different load conditions to assess its power and efficiency performances and output voltage regulating capabilities for variable load demands. Figure 24 shows a complete experimental set-up used during the tests, including the TX and RX boards with the coupling coils, a BK Precision 9111 180 W Multi Range 60 V/8 A DC Power Supply connected to the IPTS input, an HP Agilent Keysight 6060B 300 W 60 A/60 V DC Electronic Load connected to the system output, and a Teledyne LeCroy HDO9404 Digital Oscilloscope.  Figure 13d) wherein the buck controller may loose the capability of regulating the output voltage because of the non-monotonic control-to-output characteristic (see Figure 14a,b). On the other hand, for frequencies higher than 140 kHz, the overall high-frequency losses increase yielding the lower experimental efficiency. The intermediate bus voltage V 2dc has been varied in the range [14,17] V while ensuring the output voltage regulation at 12 V: the V 2dc values lower than 14 V cannot be realized by the buck converter due to the respective duty-cycle saturation, while the V 2dc values higher than 17 V cannot be achieved over the frequency range of interest f s = [105, 140] kHz due to the phase-shift saturation, as previously highlighted in Figure 13a. Figure 25 depicts the resulting experimental efficiencies obtained over the considered ranges of f s and V 2dc for four analyzed load conditions. It can be noted that for the heavy loads R L = 5 Ω (Figure 25a) and R L = 7 Ω (Figure 25b), η decreases with f s , for the light load R L = 24 Ω (Figure 25d), η increases with f s , while for the intermediate load R L = 14 Ω (Figure 25c), the efficiency decreases with f s at low V 2dc values and increases with f s at high V 2dc levels. Figure 25b-d highlight that the efficiency is maximized at V 2dc = 14 V for loads R L = {7, 14, 24} Ω, while V 2dc = 15 V maximizes η for R L = 5 Ω (Figure 25a). The resulting maximum efficiency points are listed in Table 8 for the analyzed load conditions. Eventually, Figure 26 shows the mean values of the experimental efficiency (red circles, obtained by averaging the measurement data of Figure 25) vs. the output power P o , together with the respective error bars indicating the minimum and the maximum experimental efficiency points. The graph highlights that the average efficiency increases from approximately 71% at P o = 6 W to approximately 91% at P o = 28.8 W.
V2dc = 15 V maximizes η for RL = 5 Ω (Figure 25a). The resulting maximum efficiency points are listed in Table 8 for the analyzed load conditions. Eventually, Figure 26 shows the mean values of the experimental efficiency (red circles, obtained by averaging the measurement data of Figure 25) vs. the output power Po, together with the respective error bars indicating the minimum and the maximum experimental efficiency points. The graph highlights that the average efficiency increases from approximately 71% at Po = 6 W to approximately 91% at Po = 28.8 W.    To assess the output voltage regulation capabilities, the IPTS has been tested under both static and dynamic load conditions. Figure 27

Output Voltage Regulation under Variable Load Conditions
To assess the output voltage regulation capabilities, the IPTS has been tested under both static and dynamic load conditions. Figure 27 shows steady-state experimental waveforms of the output voltage v o (t) and intermediate bus voltage v 2dc (t) measured under static load conditions, obtained for the load values R L = {5, 7, 14, 24} Ω at f s = 120 kHz and V 2dc = 15 V. The plots highlight that for all the analyzed load levels, the output voltage is correctly regulated at the desired nominal value V o,nom = 12 V (with an accuracy lower than 20 mV ≈ 0.17% V o,nom ), while the amplitude of the peak-to-peak voltage ripple is limited to 110 mV ≈ 0.92% V o,nom . Finally, Figure 28 shows experimental waveforms of v o (t) and v 2dc (t) measured under dynamic conditions, where the electronic load has been configured to emulate a square-wave variation of the load resistance between 7 Ω and 14 Ω (Figure 28a) and between 5 Ω and 24 Ω (Figure 28b) at a frequency f LT = 5 Hz. Note that such results have been obtained for the inverter switching frequency f s = 120 kHz, while the phase-shift has been adjusted during each test to achieve the intermediate bus voltage V 2dc = 15 V at the lower load resistance (i.e., d = 0.621 for R L = 7 Ω in Figure 28a and d = 0.717 for R L = 5 Ω in Figure 28b). From Figure 28a, it can be observed that v 2dc (t) presents a step variation between 15 V and 15.7 V as the load resistance changes from 7 Ω to 14 Ω (and vice versa), since the equivalent DC resistance R dc seen at the buck input also changes, and the IPT stage evolves towards a new bias point. As a result, v o (t) presents over-and undershoots with amplitudes of 123 mV (1.03% V o,nom ) and 148 mV (1.23% V o,nom ), respectively. From Figure 28b it can be observed that v 2dc (t) presents a step variation between approximately 14.8 V and 17.6 V as the load resistance changes from 5 Ω to 24 Ω, resulting in the output voltage overshoot and undershoot amplitudes of 240 mV (2% V o,nom ) and 282 mV (2.35% V o,nom ), respectively. It is worth observing that such amplitudes are contained within the typical ranges conventionally adopted for switching regulators (e.g., 5% ∆V o,nom ), while the DVMC controller ensures a correct output voltage regulation under load transient conditions.

Battery Charging Test
Eventually, the developed PR-IPTS prototype has been used to charge the Aftertech EB-162442275573 Lithium battery with a nominal voltage of 12 V, a capacity of 10 Ah and a maximum recharge current of 3 A [43]. The charging process has been performed in a constant voltage mode by imposing the 12 V regulated output voltage of the PR-IPTS to the battery. Since the equivalent static resistance of the battery, defined as the ratio between the slowly varying voltage and the current, increases during the charging, the tests

Battery Charging Test
Eventually, the developed PR-IPTS prototype has been used to charge the Aftertech EB-162442275573 Lithium battery with a nominal voltage of 12 V, a capacity of 10 Ah and a maximum recharge current of 3 A [43]. The charging process has been performed in a constant voltage mode by imposing the 12 V regulated output voltage of the PR-IPTS to the battery. Since the equivalent static resistance of the battery, defined as the ratio between the slowly varying voltage and the current, increases during the charging, the tests

Battery Charging Test
Eventually, the developed PR-IPTS prototype has been used to charge the Aftertech EB-162442275573 Lithium battery with a nominal voltage of 12 V, a capacity of 10 Ah and a maximum recharge current of 3 A [43]. The charging process has been performed in a constant voltage mode by imposing the 12 V regulated output voltage of the PR-IPTS to the battery. Since the equivalent static resistance of the battery, defined as the ratio between the slowly varying voltage and the current, increases during the charging, the tests have been carried out by setting the inverter switching frequency equal to 130 kHz and gradually adjusting the inverter phase-shift to achieve the intermediate bus voltage V 2dc = 15 V. During the test, the battery static resistance R batt increased from approximately 4 Ω to approximately 24 Ω, as shown in Figure 29a, while the battery current decreased from 3 A to 0.5 A, and the average output power delivered to the battery varied from approximately 35 W to approximately 6 W. The resulting PR-IPTS efficiency is depicted in Figure 29b, confirming that the developed IPT system yields experimental efficiencies higher than 85% over a wide output power range [15,35] Figure 29a, while the battery current decreased from 3 A to 0.5 A, and the average output power delivered to the battery varied from approximately 35 W to approximately 6 W. The resulting PR-IPTS efficiency is depicted in Figure  29b, confirming that the developed IPT system yields experimental efficiencies higher than 85% over a wide output power range [15,35] W.

Results Discussion
The experimental tests presented in the previous section have showed that the developed IPTS is able to correctly perform the output voltage regulation at the desired nominal value of 12 V for static resistive loads in the range RL = [5,24] Ω, yielding the output power in the range Po = [6, 28.8] W. The experimental efficiencies have been measured over the operating ranges fs = [105, 140] kHz and V2dc = [14,17] V, highlighting that, for different loads, the efficiency is maximized in different operating points of fs and V2dc as previously reported in Table 8. The achieved maximum efficiencies are of 72.1% for RL = 24 Ω (6 W) and of 91.7% for RL = 5 Ω (28.8 W).
The system performances have also been assessed during a battery charging test, performed on a commercial lithium battery with a 12 V nominal voltage. It has been shown that the PR-IPTS is able to correctly charge the battery with efficiency levels higher than 85% over the output power range Po = [15,35] W, while an experimental efficiency of approximately 70% has been obtained for the battery power level of 6 W toward the end of the charging process. These results, obtained for the slowly varying battery static resistance in the range Rbatt = [4,24] Ω, are consistent with the tests performed for the fixed resistive loads. Thus, the developed system can be effectively adopted to charge both fixed and variable loads.
Eventually, Tables 9-10 provide a comparison between the main IPTS solutions discussed in Section 1.1 and the system developed in this work, highlighting their relevant specifications (Table 9) and functionalities (Table 10).

Results Discussion
The experimental tests presented in the previous section have showed that the developed IPTS is able to correctly perform the output voltage regulation at the desired nominal value of 12 V for static resistive loads in the range R L = [5,24] Ω, yielding the output power in the range P o = [6, 28.8] W. The experimental efficiencies have been measured over the operating ranges f s = [105, 140] kHz and V 2dc = [14,17] V, highlighting that, for different loads, the efficiency is maximized in different operating points of f s and V 2dc as previously reported in Table 8. The achieved maximum efficiencies are of 72.1% for R L = 24 Ω (6 W) and of 91.7% for R L = 5 Ω (28.8 W).
The system performances have also been assessed during a battery charging test, performed on a commercial lithium battery with a 12 V nominal voltage. It has been shown that the PR-IPTS is able to correctly charge the battery with efficiency levels higher than 85% over the output power range P o = [15,35] W, while an experimental efficiency of approximately 70% has been obtained for the battery power level of 6 W toward the end of the charging process. These results, obtained for the slowly varying battery static resistance in the range R batt = [4,24] Ω, are consistent with the tests performed for the fixed resistive loads. Thus, the developed system can be effectively adopted to charge both fixed and variable loads.
Eventually, Tables 9 and 10 provide a comparison between the main IPTS solutions discussed in Section 1.1 and the system developed in this work, highlighting their relevant specifications (Table 9) and functionalities (Table 10).  It can be observed that the system proposed in this work ranks among the best IPTS solutions in terms of efficiency (92%), together with the systems developed in [14,24] having the maximum efficiencies of 90% and 95%, respectively. As regards the IPTS solution presented in [14], it provides a wider output power range (up to 90 W) but a slightly lower maximum efficiency (90%) as compared to our system (92%, 35 W). Both systems are able to guarantee the output voltage regulation, while with respect to the efficiency maximization, the solution of [14] only considers the ZVS achievement yielding a minimization of the inverter switching losses, but does not optimize the overall system efficiency. A complication of the proposed scheme lies in the need for current phase detection circuits on both the TX and RX sides to realize the proposed control strategy.
The solution presented in [24] outperforms our system in terms of efficiency (95%) and is conceived for higher output power levels (3 kW). In comparison, our system presents a limited architectural complexity, since it does not require a pre-regulation and a bidirectional communication link between the TX and RX sides. Even if the latter has a limited implementation cost, the system complexity is significantly increased. Moreover, the solution of [24] does not implement the output voltage regulation which could be a drawback for the loads requiring a stable supply voltage. Such a scheme is mainly focused on the maximum efficiency achievement performed under resonance conditions, but is not valid at different operating frequencies.
Even though our solution does not implement the maximum efficiency tracking scheme, it enables the efficiency mapping with respect to both the inverter switching