Research on an Improved Three-Level SVPWM Modulation Algorithm Based on ID-NPC Topology

: The conventional three-level SVPWM (Space Vector Pulse Width Modulation) algorithm is a basic modulation algorithm, which can be performed easily due to clear modulation ideas. Considering different criteria for sectors, however, the basic vector action time is calculated repeatedly, the selection of vector action sequence is cumbersome, and the algorithm execution time is extended as a result of processing by the digital processing chip. In order to better adapt to the PMSM (Per-manent Magnet Synchronous Motor) control requirements of the ID-NPC (Improved Diodes Neutral Point Clamped) topology for converter control objects, the sector judgment part, time effect part and vector synthesis part are optimized according to the principles of saving hardware resources and shortening the execution cycle. The vector synthesis optimization algorithm of 2 × amplitude substitution and the vector synthesis algorithm of 1/2 × amplitude substitution are both proposed. Finally, the ID-NPC topology is used to verify the proposed modulation algorithm.


Introduction
With the development of high power electronic components, the topology of the PWM (Pulse Width Modulation) converter has changed from two-level, to three-level, to multi-level [1,2]. In the three-level neutral point clamped ID-NPC structure, If the voltage offset is too large, the voltage distribution will be balanced, which will result in increase in the output voltage THD (Total Harmonic Distortion) of the converter and thus damage to switching devices. The voltage fluctuation of the neutral point must not exceed 5% of the DC bus voltage [3]. When the long vector is used, the three-phase connection is connected to the positive bus or negative bus, and there is no connection with the neutral point, no current flows through the neutral point, and the long vector does not affect the neutral point potential [4]. When the medium vector is used, the three phases of the load are connected with the positive and negative buses and the neutral point, and the current flows through the neutral point when the capacitor is charged and discharged, and the influence of the medium vector on the central point potential is uncontrollable under different working conditions of the motor [5]. The influence of small vectors on the neutral point is complex, and the paired redundant small vectors can produce opposite current and opposite influence on the neutral point potential [6,7]. In addition, some non-ideal factors, such as unbalanced capacitance caused by circuit distribution parameters, inconsistent characteristics of switching devices, three-phase asymmetric operation, etc., will also affect the neutral point potential [8]. In order to reduce the NP (Neutral Point) offset, the conventional modulation algorithm must be improved, in accordance with the principles of using long vectors with priority, controlling the applications of short vectors and reducing the applications of medium vectors. The two-level modulation algorithm is simpler than three-level modulation algorithm, and the three-level SVPWM modulation algorithm can be converted into a two-level modulation algorithm [9,10].

Improved D-NPC Topology
The improved diode-clamped multilevel topology (ID-NPC) is shown in Figure 1. Each set of main bridge arm consists of six controllable switching elements and two diode clamping elements. The connection between the DC power supply and converter is the same as that of the D-NPC. Taking the U-phase main bridge arm as an example, six switching elements of the main bridge arm are divided into three groups: T11 and T12, T13 and T14, T15 and T16. The drive ports are G11, G13 and G15, respectively. When the drive port G11 is connected, the phase output is Vdc/2 (positive level state); when the drive port G15 is connected, the phase output is 0 (zero level state); when the drive port G13 is connected, the phase output is −Vdc/2 (negative level state). The six controllable switching elements in three groups are connected in turn for three output levels. That is, the elements are connected separately in the positive, negative, and zero level states, without repeated conduction superimposition. The heat on single elements is distributed evenly. Three drive circuits are required for three switching elements in three groups on the main bridge arm, and nine switching drive circuits for a single converter [11]. The switching state of the ID-NPC topology is shown in Table 1 below, which is simpler and more intuitive. The switching state table and loss a distribution analysis are based on the U-phase as an example.

Three-Level SVPWM Sequential Synthesis Algorithm
After Clark transformation, the three-phase symmetric voltage is substituted into the formula, U is the amplitude of the modulation voltage: The sine and cosine values are found in the lookup table of 16-bit. When the reference voltage vector is V15 (HLL, corresponds to ("+" "−" "−") level state): Similarly, in addition to 3 zero vectors, 12 vectors (short vectors) with an amplitude of Vdc/3, 6 vectors (medium vectors) with an amplitude of √3Vdc/3, and 6 vectors (long vectors) with an amplitude of 2Vdc/3 are obtained, as shown in Figure 2 The degree of modulation is defined as M = π|V |/2V . For SVPWM modulation, the ratio of the synthesized voltage vector amplitude V to maximum basic vector amplitude 2V /3 (V /3 for the 2 × vector modulation algorithm) is √3/2 or less within the linear modulation section and [0, 0.907] within the linear modulation section of M. As shown in Figure 2, when θ is within 0-360° and M ≤ 0.907, the SVPWM linear modulation section within the hexagonal incircle [12][13][14]. As can be seen from the above analysis and Figure 2, the result of SVPWM modulation is a rotating space voltage vector to drive the PMSM to rotate. It is not necessary to determine the specific vector in the sequential synthesis strategy. Instead, only clockwise or counterclockwise modulation at a certain speed is needed. The linear modulation section [0, 0.907] can be divided as follows based on the M: [0, 0.453], (0.453, 0.5], (0.5, 0.907], as detailed below.

Vector Synthesis Algorithm of 2 × Amplitude Substitution
According to the above analysis, when M ∈ [0, 0.453], the reference vector passes through two areas in one sector; and when M ∈ (0.453, 0.907], the sector where the reference vector passes includes more than two areas. Once the vector passes through one area, a series of switching tubes will change accordingly, resulting in switching losses. In order to further reduce switching losses, the synthesis strategy of 2 × amplitude substitution is proposed by using M ∈ [0, 0.453] in the case of M ∈ (0.453, 0.907]. Take the S1 sector as an example. When a ∈ (0.453, 0.907], a/2 ∈ (0.227, 0.453] is converted to the first case discussed in the previous section. According to the volt-second balance rule (reference vector: Vref, when M = a/2, the corresponding reference vector is Vref/2), get the following formula: V is the x-axis projection of Vref/2 and V is the y-axis projection of Vref/2. The action time of the adjacent basic vector is calculated as follows: Sort out the coefficients: The reference vector ( V ) is equivalent to the synthesis of V × T /T and V × T /T . According to the linear invariance, both sides of the Formula (5) are multiplied by 2 at the same time: The two vectors V and V can be doubled within the action time of the corresponding basic vector, as shown in Figure 6. It can be seen from the above figure that the vector Vref/2 is half of Vref, covering 1/4 of the sector. After this vector is doubled, the linear modulation area can be fully covered. The order of the full modulation area is optimized in a counterclockwise order: S11→S12→S21→S22→S31→S32→S41→S42→S51→S52→S61→S62.

Vector Synthesis Algorithm of 1/2 × Amplitude Substitution
Since short vectors have a complicated impact on the NP unbalance, a vector synthesis algorithm of 1/2 × amplitude substitution is proposed, in which medium and long vectors are synthesized instead of short vectors. The vectors in the areas S11 and S12 can be replaced by 1/2 the amplitude in S13, S14, S15 and S16. In conjunction with the Formulas (3) to (6), the vector Vref is used instead of Vref/2 in Figure 6, i.e., Vref/2 = (1/2)Vref. The derivation process is similar to the vector synthesis algorithm of 1/2 × amplitude substitution.

Time Effect Optimization
Adjacent basic vectors are synthesized to the equivalent reference voltage vector. The action time of basic vectors is determined according to the principle of volt-second balance. As shown in Figure 4, the area in sector S1 is marked as S11-S16, parts of S11 and S12 are collectively marked as S112, parts of S21 and S22 are collectively marked as S212, parts of S31 and S32 are collectively marked as S312, parts of S41 and S42 are collectively marked as S412, parts of S51 and S52 are collectively marked as S512, parts of S61 and S62 are collectively marked as S612, and other medium and small areas in large areas are marked similarly [15,16]. Each vector in a small area is the synthetic result of three basic vectors, which correspond to the action time T11, T12 and T13, respectively. That is, the basic vectors in 36 small areas in the conventional modulation algorithm correspond to 108 time values, so the time calculation is cumbersome. Each area in S11-S16 is composed of three adjacent vectors. Taking the first area as an example, the corresponding adjacent vectors and action time are shown in Table 2.  The redundant switching sequence of the converter can be changed based on the minimum switching loss or minimum total harmonic distortion (THD) target. In order to achieve low THD, the vector switching sequence of the area S112: V13→V12→V11→V12→V13→V13→V12→V11→V12→V13.
Among six areas (S11-S16), the areas S12-S16 can be obtained by rotating S11 by nπ/3(n = 1, 2, 3, 4, 5). Taking S11 rotation to obtain S12 as an example, the relationship between the space vector and voltage is shown Table 3 below. The reference vector V of the first area is obtained according to the principle of volt-second balance: Both sides of the formula are multiplied by the factor e / , and the reference vector V of the first area is rotated to obtain the reference vector V of the second area: By comparison, it can be seen that the conduction time is exactly the same for them, and so on. The conduction time is also the same for six areas. Assuming that V is composed of u , u and u , then: The phase voltage relationship of six areas is shown in Table 4.
Through simplification, all six areas can be mapped to the first area, which can simplify the process and save hardware resources.

Simulation and Analysis of Modulation Algorithm Based on ID-NPC
Simulation conditions is shown in Table 5.  PMSM motor parameter setting is shown in Table 6.

Waveform of Vector Synthesis Algorithm of 2 × Amplitude Substitution
When M = 0.8 in the conventional vector modulation algorithm, the waveforms of the parameters are shown in Figure 7, and the stator voltages u , u and u are shown in Figure 8. In Figure 7, the first part is the speed waveform (Unit: rad/s), the second part is the three-phase current ia, ib, ic waveform (Unit: A), the third part is dq current id, iq waveform (Unit: A), the fourth part is torque waveform (Unit: N × m).  When M = 0.4, the vector synthesis strategy of 2 × amplitude substitution is equivalent to M = 0.8, the waveforms of parameter are shown in Figure 9, and the stator phase voltages u , u and u are shown in Figure 10. In Figure 9, the first part is the speed waveform (Unit: rad/s), the second part is the three-phase current ia, ib, ic waveform (Unit: A), the third part is dq current id, iq waveform (Unit: A), the fourth part is torque waveform (Unit: N × m).

Waveform of Vector Synthesis Algorithm of 1/2 × Amplitude Substitution
When M = 0.4, the waveforms of the stator phase currents i , i and i in the conventional vector synthesis strategy are shown in Figure 11, and the stator voltages u , u and u are shown in Figure 12. In Figure 11, the first part is the speed waveform (Unit: rad/s), the second part is the three-phase current ia, ib, ic waveform (Unit: A), the third part is dq current id, iq waveform (Unit: A), the fourth part is torque waveform (Unit: N × m).  When M = 0.8, the vector synthesis strategy of ½ × amplitude substitution is equivalent to M = 0.4, the waveforms of parameter are shown in Figure 13, and the stator phase voltages u , u and u are shown in Figure 14. In Figure 13, the first part is the speed waveform (Unit: rad/s), the second part is the three-phase current ia, ib, ic waveform (Unit: A), the third part is dq current id, iq waveform (Unit: A), the fourth part is torque waveform (Unit: N × m).

Discussion
Compared with the conventional modulation strategy, the vector synthesis strategy of 2 × amplitude substitution features the synthesis of short vectors, fewer passing areas. The modulation vector is composed of two short vectors and one zero vector, since the composite vector contains zero vector, so it is not necessary to add other zero vector to the seven-segment or five-segment modulation. In the linear region of modulation M ∈ [0, 0.907], the synthesizing vectors can cover the whole hexagon area, the area of hexagonal modulation region is 1.103 times, compared with that of circular modulation region. Furthermore, the synthesis strategy increased in the speed waveform amplitude, but poor waveform of currents i , i and i , as well as over-modulation. In addition, the current amplitudes of three phases are difference, and the NP potential is unbalanced.
In the vector synthesis strategy of 1/2 × amplitude substitution, short vectors are modulated with medium and long vectors, and the current waveform of the three-phase stator is better than that of the vector synthesis strategy of 2 × amplitude substitution, but with more passing areas. In order to further reduce over-modulation, the control algorithm should be added for corrections.
The two optimized modulation strategies feature the reduction of hardware resources and higher simulation speed. By comparison, both modulation algorithms affect the NP balance. To balance the passing areas and waveform quality, the medium and long vector synthesis algorithm of 2 × amplitude substitution is used as the converter modulation algorithm.

Conclusions
The principle and four steps of the conventional three-level SVPWM modulation are analyzed. The modulation algorithm of three-level SVPWM sequential synthesis is adopted on this basis. It is not necessary to judge the sector in this algorithm. Instead, only clockwise or counterclockwise rotation based on the angle sequence is required. Adjacent vectors in the area where the reference vector passes need to be synthesized. Then, the vector synthesis algorithm of 2 × amplitude substitution is used. When M ∈ (0.453, 0.907] the resultant reference vector changes to M ∈ [0, 0.453], which reduces the switching loss and optimizes the even distribution of heat. Since short vectors are applied and the NP potential unbalance is affected to some extent, the vector synthesis modulation algorithm of 1/2 × amplitude substitution (half of medium and long vectors) is also put forward. Through comparison and analysis, the vector synthesis modulation algorithm of 1/2 × amplitude substitution features high waveform quality, while that of 2 × amplitude substitution features less switching loss, and the 2 × amplitude substitution modulation can cover all hexagon regions, and in the linear region of modulation, the area of modulation area is 1.103 times of the original. The converter of ID-NPC topology is also subjected to simulation experiments by two modulation algorithms, and the feasibility of the improved modulation algorithm is proved.