A Novel Switched-Capacitor Inverter with Reduced Capacitance and Balanced Neutral-Point Voltage

A novel three-phase switched-capacitor multilevel inverter (SCMLI) with reduced capacitance and balanced neutral-point voltage is proposed in this paper. Applying only one DC source, the three-phase seven-level topology possessing voltage-boosting capability is accomplished without the high-voltage stress of power switches. Owing to the inherent redundant switching states of the proposed topology, two charging approaches that can effectively limit the voltage ripples and path selection for capacitors can be realized. This provides the presented topology with reduced capacitance, balanced neutral-point voltage, good performance in not only the three-phase four-wire system but also the three-phase three-wire system, and low total harmonic distortion (THD) of the output voltage. A comprehensive comparison with previous SCMLIs in various aspects is conducted to validate the merits mentioned above. The simulation results accord with theoretical analyses, confirming the feasibility of the proposed three-phase SCMLI.


Introduction
Multilevel inverters are important circuit configurations in modern electrical power systems because of their many advantages, such as low total harmonic distortion (THD) of the output voltage, low voltage stress on power devices, and low electromagnetic interference (EMI). The main applications of these inverters include static compensators, high-voltage DC transmission systems, active power filters, and renewable energy systems that include variable-frequency motor drives [1][2][3][4][5][6]. Neutral-point-clamped (NPC) [7], flying-capacitor [8], and cascaded H-bridge [9] are three well-researched multilevel inverters. These inverters are widely used in practical and commercial applications. However, these inverters have shortcomings such as neutral-point voltage imbalance and the need for excessive isolated DC sources [10]. Owing to the inability to boost the input voltage, the sum of the DC source voltages cannot be less than the amplitude of the output voltage. To overcome the drawbacks mentioned above, many new topologies have been introduced that offer more optimized component utilization, more voltage levels, higher efficiency, and so on [11,12].
Since the input voltage is relatively low compared with the output voltage, boost circuits [13,14] are required in many applications, such as grid-connected photovoltaic modules, distributed generation (DG) systems, and electric vehicles. Inductors or transformers are used in most boost circuits, making the systems bulky and heavy [15]. Therefore, a charge pump is typically adopted as a boost circuit [16]. In the charge pump, the output voltage is equal to the sum of the capacitor voltages and the input voltage. The capacitors in the charge pump are discharged when connected in series and charged when connected in parallel along with the DC source.
Inverters using the same working principle are called switched-capacitor multilevel inverters (SCMLI), which have become a recent research topic of interest [17,18]. Unlike

Proposed SCMLI and Operating Principle
The proposed three-phase SCMLI topology is shown in Figure 1. Employing one DC source and eight capacitors, it can generate seven voltage levels (0 V, 0.5 Vdc, Vdc, 1.5 Vdc, −0.5 Vdc, −Vdc, −1.5 Vdc) under different kinds of load conditions. The capacitors' rated voltage is UN = 0.5 Vdc. Bidirectional switches are used to block positive and negative voltage stress. The floating capacitors C1,2 are used to generate the top voltage level. They can also balance the voltages of the DC-link capacitors Cdc1,2 when needed. Furthermore, the proposed topology is used in a three-phase four-wire system when O and N are connected and is used in a three-phase three-wire system when O and N are not connected. All switching states of the proposed three-phase SCMLI are listed in Table 1. Main switching states are depicted in Figure 2a-g. Other switching states are fully discussed in Sections 3 and 4. To generate 0 V, S2, S3, S11, and S12 need to be ON, as shown in Figure 2a. In Figure 2b,e, the black and red devices represent two different paths. Both C1 and C2 can be used to generate not only 0.5 Vdc but also −0.5 Vdc. Selecting the right path can make uC1 approach uC2. In Figure 2c,f, the capacitors Cdc1, C2 and Cdc2, C1 are used to generate Vdc and −Vdc, respectively. To generate 1.5 Vdc, S1, S7, S9, and S10 need to be ON, as shown in Figure  2d. Similarly, to generate −1.5 Vdc, S6, S7, S8, and S13 need to be ON, as shown in Figure 2g. For multilevel inverters, there are several modulation strategies. In this paper, the phase opposition disposition PWM is adopted, which is shown in Figure 2h.

STATES
Voltage Figure Position Switches Level S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 1 1.5 Vdc All switching states of the proposed three-phase SCMLI are listed in Table 1. Main switching states are depicted in Figure 2a-g. Other switching states are fully discussed in Sections 3 and 4. To generate 0 V, S 2 , S 3 , S 11 , and S 12 need to be ON, as shown in Figure 2a. In Figure 2b,e, the black and red devices represent two different paths. Both C 1 and C 2 can be used to generate not only 0.5 V dc but also −0.5 V dc . Selecting the right path can make u C1 approach u C2 . In Figure 2c,f, the capacitors C dc1 , C 2 and C dc2 , C 1 are used to generate V dc and −V dc , respectively. To generate 1.5 V dc , S 1 , S 7 , S 9 , and S 10 need to be ON, as shown in Figure 2d. Similarly, to generate −1.5 V dc , S 6 , S 7 , S 8 , and S 13 need to be ON, as shown in Figure 2g. For multilevel inverters, there are several modulation strategies. In this paper, the phase opposition disposition PWM is adopted, which is shown in Figure 2h.   S9 S10 S11 S12

Capacitor Charging Approaches
Two significant approaches are used in this paper to charge capacitors. Approach I that is first proposed in this paper plays an important role in balancing capacitors voltages and makes it possible for the proposed topology to solve the problem of neutral-point voltage imbalance. Approach II is a widely adopted approach that can charge the capacitors together. The equivalent circuits of approach I and approach II are shown in Figure  3a,b, respectively. Rdc1, Rdc2, R1, and R2 are the equivalent resistances of the devices.

Capacitor Charging Approaches
Two significant approaches are used in this paper to charge capacitors. Approach I that is first proposed in this paper plays an important role in balancing capacitors voltages and makes it possible for the proposed topology to solve the problem of neutral-point voltage imbalance. Approach II is a widely adopted approach that can charge the capacitors together. The equivalent circuits of approach I and approach II are shown in Figure 3a,b, respectively. R dc1 , R dc2 , R 1 , and R 2 are the equivalent resistances of the devices. Figure 3. Equivalent circuit of (a) approach I and (b) approach II.

Approach I
All of the DC-link capacitors Cdc1,2 and one of the floating capacitors C1,2 were realize approach I in this paper. The circuit mode with C1, Cdc1 and Cdc2 in Figu taken as an example to illustrate approach I. The approximation that Cdc1 = Cdc2 =

Approach I
All of the DC-link capacitors C dc1,2 and one of the floating capacitors C 1,2 were used to realize approach I in this paper. The circuit mode with C 1 , C dc1 and C dc2 in Figure 3a is taken as an example to illustrate approach I. The approximation that C dc1 = C dc2 = C 1 = C 0 and R dc1 = R dc2 = R 1 = R 0 is introduced to simplify the analysis. The following analysis is based on this approximation. According to the topology, the equivalent capacitance C eq and the equivalent resistance R eq can be expressed as follows: (1) Therefore, the current that flows through the DC source is given by where The voltage of capacitor C dc2 can be expressed as The voltage of capacitor C dc1 satisfies the following differential equation: According to Equation (5), C dc1 initial voltage is u Cdc1 (0) and final voltage is (V dc + u Cdc1 (0) − u Cdc2 (0) + u C1 (0))/3. According to the full response theory of the first order circuit, u Cdc1 can be expressed as Similarly, u C1 can be expressed as When u Cdc1 (0) > 0.5 V dc > u Cdc2 (0) and u C1 (0) < 0.5 V dc , capacitors C 1 and C dc2 will be charged, and capacitor C dc1 will be discharged according to Equations (4), (6) and (7). When u Cdc1 (0) < 0.5 V dc < u Cdc2 (0) and u C1 (0) > 0.5 V dc , capacitors C 1 and C dc2 will be discharged, and capacitor C dc1 will be charged similarly. If approach I is adopted, all relevant capacitor voltages will move toward 0.5 V dc . Furthermore, these voltages will reach 0.5 V dc if u Cdc1 (0) − u Cdc2 (0) + u C1 (0) = 0.5 V dc . As shown in Figure 4a, S 1 , S 8 , S 2 , and S 3 are ON. C 1 and C dc1 are connected in parallel, and approach I is realized. To generate 0 V at the same time, S 11 and S 12 should be ON. Moreover, 0.5 V dc and −0.5 V dc can be generated when S 10 and S 13 are ON, respectively. As shown in Figure 4b, S 2 , S 3 , S 6 , and S 9 are ON. C 2 and C dc2 are connected in parallel, and approach I is realized. Similarly, 0 V, 0.5 V dc , and −0.5 V dc can be generated at the same time.
if uCdc1(0) − uCdc2(0) + uC1(0) = 0.5 Vdc. As shown in Figure 4a, S1, S8, S2, and S3 are ON. C1 and Cdc1 are connected in parallel, and approach I is realized. To generate 0 V at the same time, S11 and S12 should be ON. Moreover, 0.5 Vdc and −0.5 Vdc can be generated when S10 and S13 are ON, respectively. As shown in Figure 4b, S2, S3, S6, and S9 are ON. C2 and Cdc2 are connected in parallel, and approach I is realized. Similarly, 0 V, 0.5 Vdc, and −0.5 Vdc can be generated at the same time. S9 S10 S11 S12 S13 Cdc1 Cdc2 C1 C2 (a) (b) (c) Figure 4. Switching states when (a) approach I is realized and C1 is used, (b) approach I is realized and C2 is used, and (c) approach II is realized.

Approach II
Approach II, which is used to balance the floating capacitor voltages, is shown in Figure 3b. Similarly, it is assumed that C1 = C2 = C0 and R1 = R2 = R0. According to the topology, Req = 2R0 and Ceq = 0.5C0. Therefore, is is given by eq eq dc eq s eq where ueq(0) = uC1(0) + uC2(0). uC1 can be calculated as follows: Similarly, uC2 can be expressed as follows: After applying approach II, the average uC1 and uC2 reach 0.5 Vdc, according to Equations (9) and (10). Moreover, uC1 and uC2 will reach 0.5 Vdc if uC1(0) = uC2(0). Approach II can be realized when S1, S8, S6, and S9 are ON, as shown in Figure 4c. Any one of 0 V, 0.5 Vdc, and −0.5 Vdc can be generated at the same time. These two charging approaches can be realized, which is an important feature of the proposed three-phase SCMLI.

Control Strategies to Limit Voltage Ripples
To limit voltage ripples, the control strategies of the capacitor voltages are listed in Table 2. For capacitors C1 and C2, the control strategies can be divided into two aspects. The first aspect involves using approach II and making the average of uC1 and uC2 return to 0.5 Vdc. Approach II is taken when |0.5(uC1 + uC2) − 0.5 Vdc| > uγ. uγ is an adjustable parameter. The second aspect involves selecting the right path and making uC1 approach uC2. The path selection for C1,2 is used if |0.5(uC1 + uC2) − 0.5 Vdc| < uγ. Switching states when (a) approach I is realized and C 1 is used, (b) approach I is realized and C 2 is used, and (c) approach II is realized.

Approach II
Approach II, which is used to balance the floating capacitor voltages, is shown in Figure 3b. Similarly, it is assumed that C 1 = C 2 = C 0 and R 1 = R 2 = R 0 . According to the topology, R eq = 2R 0 and C eq = 0.5C 0 . Therefore, i s is given by where u eq (0) = u C1 (0) + u C2 (0). u C1 can be calculated as follows: Similarly, u C2 can be expressed as follows: After applying approach II, the average u C1 and u C2 reach 0.5 V dc , according to Equations (9) and (10). Moreover, u C1 and u C2 will reach 0.5 V dc if u C1 (0) = u C2 (0). Approach II can be realized when S 1 , S 8 , S 6 , and S 9 are ON, as shown in Figure 4c. Any one of 0 V, 0.5 V dc , and −0.5 V dc can be generated at the same time. These two charging approaches can be realized, which is an important feature of the proposed three-phase SCMLI.

Control Strategies to Limit Voltage Ripples
To limit voltage ripples, the control strategies of the capacitor voltages are listed in Table 2. For capacitors C 1 and C 2 , the control strategies can be divided into two aspects. The first aspect involves using approach II and making the average of u C1 and u C2 return to 0.5 V dc . Approach II is taken when |0.5(u C1 + u C2 ) − 0.5 V dc | > u γ . u γ is an adjustable parameter. The second aspect involves selecting the right path and making u C1 approach u C2 . The path selection for C 1,2 is used if |0.5(u C1 + u C2 ) − 0.5 V dc | < u γ . Table 2. Control strategies of the capacitor voltages.

Capacitors Control Strategy
C 1 and C 2 Approach II, path selection C dc1 and C dc2 Approach I, path selection Similarly, for capacitors C dc1 and C dc2 , the control strategies can be divided into two aspects. The first aspect involves using approach I and making u Cdc1 and u Cdc2 move toward 0.5 V dc . Approach I is taken when |u Cdc1 − u Cdc2 | > u α . u α is also an adjustable parameter. The second aspect involves selecting the right path and making u Cdc1 approach u Cdc2 . As u Cdc1 + u Cdc2 = V dc , u Cdc1 and u Cdc2 return to 0.5 V dc when u Cdc1 reaches u Cdc2 .
There are more paths for selection in the proposed topology, and the redundant switching states are depicted in Figure 5a-e. With respect to Figure 5a, the black and red devices represent two different paths. S 1 , S 8 , S 11 , and S 12 are ON, and the capacitors C dc1 and C 1 are used to generate 0 V. Similarly, S 6 , S 9 , S 11 , and S 12 are ON, and capacitors C dc2 and C 2 are used to generate 0 V. Moreover, 0.5 V dc is generated when S 1 , S 8 , and S 10 are ON, as shown in Figure 5b, whereas −0.5 V dc is generated when S 6 , S 9 , and S 13 are ON, as shown in Figure 5d. In Figure 5c,e, capacitors C 1 and C 2 can be used to generate not only V dc but also level −V dc . For capacitors in the proposed topology, path selection is an important control strategy. As shown in Figures 2 and 5, there are various paths for selection at several voltage levels, and the capacitors used are different, making it easier to balance the capacitor voltages. This is one of the main advantages of the proposed topology.

C1 and C2
Approach II, path selection Cdc1 and Cdc2 Approach I, path selection Similarly, for capacitors Cdc1 and Cdc2, the control strategies can be divided into two aspects. The first aspect involves using approach I and making uCdc1 and uCdc2 move toward 0.5 Vdc. Approach I is taken when |uCdc1 − uCdc2| > uα. uα is also an adjustable parameter. The second aspect involves selecting the right path and making uCdc1 approach uCdc2. As uCdc1 + uCdc2 = Vdc, uCdc1 and uCdc2 return to 0.5 Vdc when uCdc1 reaches uCdc2. The path selection for Cdc1,2 is used if |uCdc1 − uCdc2| < uα.
There are more paths for selection in the proposed topology, and the redundant switching states are depicted in Figure 5a-e. With respect to Figure 5a, the black and red devices represent two different paths. S1, S8, S11, and S12 are ON, and the capacitors Cdc1 and C1 are used to generate 0 V. Similarly, S6, S9, S11, and S12 are ON, and capacitors Cdc2 and C2 are used to generate 0 V. Moreover, 0.5 Vdc is generated when S1, S8, and S10 are ON, as shown in Figure 5b, whereas −0.5 Vdc is generated when S6, S9, and S13 are ON, as shown in Figure 5d. In Figure 5c,e, capacitors C1 and C2 can be used to generate not only Vdc but also level −Vdc. For capacitors in the proposed topology, path selection is an important control strategy. As shown in Figures 2 and 5, there are various paths for selection at several voltage levels, and the capacitors used are different, making it easier to balance the capacitor voltages. This is one of the main advantages of the proposed topology.

S6
(e) Usually, there is a conflict between the control strategies of uC1,2 and the control strategies of uCdc1,2. It is important to make a comprehensive decision according to the latest status. In this paper, the top priority is to decide whether to take approach II. |0.5(uC1 + uC2) − 0.5 Vdc| > uγ, and this is the criterion that uC1 and uC2 have to meet if approach II is to be taken. After that, approach I is taken when |uCdc1 − uCdc2| > uα. This will make uCdc1 and uCdc2 move toward 0.5 Vdc. Then, the path selection for Cdc1,2 is used if |uCdc1 − uCdc2| > uβ. uα is larger than uβ. Lastly, the path selection for C1,2 is used.
The reasons for there being no problem of neutral-point voltage imbalance for the proposed three-phase SCMLI can be divided into two aspects. On the one hand, approach Usually, there is a conflict between the control strategies of u C1,2 and the control strategies of u Cdc1,2 . It is important to make a comprehensive decision according to the latest status. In this paper, the top priority is to decide whether to take approach II. |0.5(u C1 + u C2 ) − 0.5 V dc | > u γ , and this is the criterion that u C1 and u C2 have to meet if approach II is to be taken. After that, approach I is taken when |u Cdc1 − u Cdc2 | > u α . This will make u Cdc1 and u Cdc2 move toward 0.5 V dc . Then, the path selection for C dc1,2 is used if |u Cdc1 − u Cdc2 | > u β . u α is larger than u β . Lastly, the path selection for C 1,2 is used.
The reasons for there being no problem of neutral-point voltage imbalance for the proposed three-phase SCMLI can be divided into two aspects. On the one hand, approach I is adopted in this paper. This approach is an effective measure to balance the capacitor voltages. On the other hand, there are various paths for selection at several voltage levels. These two aspects complement each other, giving the proposed topology the ability to solve the problem of neutral-point voltage imbalance.

Capacitance Determination
Approach II can be used at 0 V, 0.5 V dc , and −0.5 V dc . Thus, capacitors C 1 and C 2 are discharged when u ref > V dc and i bus > 0 in the positive half cycle. To address this problem, an important change to the original modulation method is made in this paper, and the new modulation wave in the positive half cycle is shown in Figure 6.

Capacitance Determination
Approach II can be used at 0 V, 0.5 Vdc, and −0.5 Vdc. Thus, capacitors C1 discharged when uref > Vdc and ibus > 0 in the positive half cycle. To address th an important change to the original modulation method is made in this pap new modulation wave in the positive half cycle is shown in Figure 6. The longest discharging time of floating capacitors is an important SCMLI because the required capacitance can be calculated according to it. The longes ing time tldt of floating capacitors in the proposed three-phase SCMLI can be ex where Ts is the switching period, and tc is the minimum duration of 0.5 Vdc wh or t3 ≤ t ≤ t4. According to Equation (11), the longest discharging time of floating in the proposed topology is smaller than 2Ts, which is much shorter than th traditional SCMLIs. During the longest discharging time, the current that flow floating capacitors is ibus. The voltage variation of floating capacitors that com can be calculated as follows: where m is the modulation index, and Aboost is the voltage gain. tstart and tend a time and end time of the longest discharging time, respectively. ZMN is the total between point M and point N. Considering that approach I is adopted, Eq needs to satisfy According to Equation (13), the required capacitance of floating capaci calculated as follows: According to the original modulation method, there are two choices in a switching period when u ref > V dc . These choices are u bus = V dc and u bus = 1.5 V dc . In this paper, this condition is expressed as u bus {V dc , 1.5 V dc }. u bus {0.5 V dc , 1.5 V dc } is added when t 1 ≤ t ≤ t 4 because the abovementioned control strategies can be realized at 0.5 V dc . Specifically, u bus {0.5 V dc , 1.5 V dc } is used in half of the switching periods when The longest discharging time of floating capacitors is an important SCMLI parameter because the required capacitance can be calculated according to it. The longest discharging time t ldt of floating capacitors in the proposed three-phase SCMLI can be expressed as where T s is the switching period, and t c is the minimum duration of 0.5 V dc when t 1 ≤ t ≤ t 2 or t 3 ≤ t ≤ t 4 . According to Equation (11), the longest discharging time of floating capacitors in the proposed topology is smaller than 2T s , which is much shorter than that in other traditional SCMLIs. During the longest discharging time, the current that flows through floating capacitors is i bus . The voltage variation of floating capacitors that comes from i bus can be calculated as follows: where m is the modulation index, and A boost is the voltage gain. t start and t end are the start time and end time of the longest discharging time, respectively. Z MN is the total impedance between point M and point N. Considering that approach I is adopted, Equation (12) needs to satisfy 2T s C 1,2 According to Equation (13), the required capacitance of floating capacitors can be calculated as follows: According to Equations (11)- (14), reducing the longest discharging time of the floating capacitors can effectively reduce the capacitance of the floating capacitors.
Approach I, which can make u Cdc1 and u Cdc2 move toward 0.5 V dc , is taken if |u Cdc1 − u Cdc2 | > u α . Thus, u Cdc1 and u Cdc2 can be limited to 0.5 V dc ± 0.5 u α with less DC-link capacitance. Similarly, the voltage variation of the DC-link capacitors between t begin (the end time of the first approach I) and t finish (the start time of the second approach I) can be calculated as follows: where kT s = t finish − t begin . To coincide with approach I, Equation (15) needs to satisfy According to Equation (16), the required capacitance of the DC-link capacitors can be calculated as follows: According to Equations (14) and (17), the required capacitance of the floating capacitors is similar to that of the DC-link capacitors. Therefore, C 1,2 = C dc12 in this paper.

Efficiency Calculation
In this section, the overall efficiency of the proposed three-phase SCMLI is calculated. First, the conduction loss of the power switches P con1 can be expressed as where i si , r si , and V si are the current, internal resistance, and voltage drop of the i-th switch, respectively. N swi is the number of power switches. T o and f o are the period and frequency of the output voltage, respectively. The conduction loss P con2 that comes from the DC-link capacitors and the floating capacitors can be calculated as follows: where i Ci and r Ci are the current and the internal resistance of the i-th capacitor, respectively. N ca is the number of capacitors. The conduction loss of the output filters P con3 can be calculated as follows: where i Lfi and r Lfi are the current and the internal resistance of the i-th filter inductor, respectively. i Cfi and r Cfi are the current and the internal resistance of the i-th filter capacitor, respectively. N fil is the number of filters.
To simplify the analysis, the voltage and the current of the power switches are considered to have a linear relation with time during the switching process. Therefore, the switching loss P off(i,j) that is caused by the j-th turning OFF process of the i-th switch is given by Electronics 2021, 10, 947 10 of 21 where V off(i,j) and I off(i,j) are the voltage after the turning OFF process and the current before the turning OFF process, respectively. Similarly, switching loss P on(i,j) that is caused by the j-th turning ON process of the i-th switch is given by where V on(i,j) and I on(i,j) are the voltage before the turning ON process and the current after the turning ON process, respectively. According to Equations (21) and (22), the total switching loss P sw can be calculated by where N on(i) and N off(i) are the number of i-th switch turning ON processes and turning OFF processes, respectively. According to Equations (18)- (20), and (23), the overall efficiency of the proposed topology is given by

Simulation Results
MATLAB/Simulink was chosen as the simulation software. The parameters of the proposed three-phase SCMLI are listed in Table 3. The input voltage was set as 200 V, which resembles many other SCMLIs. Thus, the rated voltage of the capacitors was 100 V. The modulation ratio was 0.95, and the output voltage was 285 (300 × 0.95) V. The capacitance used was 200 µF, which meets the requirement of Equation (15). The output power was 1884 W, and the resistive-inductive load Z 1 was 40 Ω, 100 mH. u α was 8 V since the maximum allowable voltage ripple of capacitors was 10 V (10% of the rated voltage). The filter capacitor was 80 µF, and the filter inductor was 4 mH. The switching frequency was 20 kHz. This frequency can reduce the requirement of capacitance according to Equation (15). The output frequency was 50 Hz. To assess the performance of the proposed three-phase SCMLI in the three-phase four-wire system, Z o = Z 1 is given. Figure 7a shows the observed A-phase bus voltage. The top voltage level was 300 V, and the proposed three-phase SCMLI could boost the input voltage. Because u α was equal to 8 V, the voltages of the DC-link capacitors in the A-phase were limited to 96-104 V, as shown in Figure 7b. Approach I could move the voltage of DC-link capacitors toward 100 V when they were larger than 104 V or smaller than 96 V. Figure 7c shows the floating capacitor voltages in the A-phase, which were approximately 96-103 V. It can be seen in this figure that the longest discharging time of floating capacitors was shorter than 2T s . These waveforms meet the voltage ripple requirement, which should be less than 10% of the rated voltage. four-wire system, Zo = Z1 is given. Figure 7a shows the observed A-phase b top voltage level was 300 V, and the proposed three-phase SCMLI could b voltage. Because uα was equal to 8 V, the voltages of the DC-link capacitors were limited to 96-104 V, as shown in Figure 7b. Approach I could move DC-link capacitors toward 100 V when they were larger than 104 V or sma Figure 7c shows the floating capacitor voltages in the A-phase, which were 96-103 V. It can be seen in this figure that the longest discharging time of f tors was shorter than 2Ts. These waveforms meet the voltage ripple requ should be less than 10% of the rated voltage. To further test the performance of the proposed three-phase SCMLI, ductive load transient is given. The time when the load changed from Zo was 0.12 s. The bus voltage of the A-phase is shown in Figure 10a. The diffe the waveform before 0.12 s and the waveform after 0.12 s was not nota shows the A-phase DC-link capacitor voltages. The voltage ripple of these 8 V during the entire process (uα = 8 V). Figure 10c shows the A-phase flo voltages. The transient process only lasted for a short period of time (appr s). After that, the floating capacitor voltages quickly returned to the stea waveforms also meet the voltage ripple requirements and are in good agre abovementioned theoretical analysis. To further test the performance of the proposed three-phase SCMLI, a resistiveinductive load transient is given. The time when the load changed from Z o = 2Z 1 to Z o = Z 1 was 0.12 s. The bus voltage of the A-phase is shown in Figure 10a. The difference between the waveform before 0.12 s and the waveform after 0.12 s was not notable. Figure 10b shows the A-phase DC-link capacitor voltages. The voltage ripple of these capacitors was 8 V during the entire process (u α = 8 V). Figure 10c shows the A-phase floating capacitor voltages. The transient process only lasted for a short period of time (approximately 0.01 s). After that, the floating capacitor voltages quickly returned to the steady state. These waveforms also meet the voltage ripple requirements and are in good agreement with the abovementioned theoretical analysis.
The output voltage of each phase during a resistive-inductive load transient is shown in Figure 11a, and the FFT result of the A-phase output voltage is shown in Figure 11b. THD = 1.96%, and the start time was 0.12 s. There was no significant change in the output voltage of each phase after 0.12 s. The output current of each phase under the same resistive-inductive load transient is shown in Figure 12 To test the presented three-phase SCMLI more rigorously, a special load with a temporary three-phase unbalanced disturbance is given. For each phase, Z o = 2Z 1 . A disturbance load R d = 100 Ω was only added to the A-phase when 0.8 s < t < 0.85 s. Under this condition, Figure 13a shows the A-phase bus voltage, and there was no obvious change in the waveform when 0.8 s < t < 0.85 s or t > 0.85 s. Figure 13b shows the A-phase DC-link capacitor voltages. Similarly, the transient process only lasted for a short period of time (approximately 0.01 s). During this transient process, u Cdc2 was momentarily larger than 104 V, and u Cdc1 was momentarily smaller than 96 V. After that, the DC-link capacitor volt-ages were limited to 96-104 V, as before. Figure 13c shows the A-phase floating capacitor voltages. During the same transient process, u C2 was momentarily larger than 105 V. After that, the floating capacitor voltages quickly returned to the steady state.  The output voltage of each phase during a resistive-inductive loa in Figure 11a, and the FFT result of the A-phase output voltage is s THD = 1.96%, and the start time was 0.12 s. There was no significant c voltage of each phase after 0.12 s. The output current of each phase u tive-inductive load transient is shown in Figure 12. Similarly, the tr lasted for a short period of time. The output current of each phase qu the initial steady state to a new steady state. Thus, there is no need overvoltage problem or the overcurrent problem.  To test the presented three-phase SCMLI more rigorously, a spec porary three-phase unbalanced disturbance is given. For each phase, ance load Rd = 100 Ω was only added to the A-phase when 0.8 s < t condition, Figure 13a shows the A-phase bus voltage, and there was in the waveform when 0.8 s < t < 0.85 s or t > 0.85 s. Figure 13b shows th capacitor voltages. Similarly, the transient process only lasted for a s (approximately 0.01 s). During this transient process, uCdc2 was mom 104 V, and uCdc1 was momentarily smaller than 96 V. After that, the voltages were limited to 96-104 V, as before. Figure 13c shows the A pacitor voltages. During the same transient process, uC2 was momenta V. After that, the floating capacitor voltages quickly returned to the st When the disturbance load was added to the A-phase, the outp phase was as shown in Figure 14a, and the FFT result of the A-phase as shown in Figure 14b. THD = 3.28%, and the start time was 0.08 s output voltage of each phase during the transient process was small.
When the disturbance load was added to the A-phase, the outp phase was as shown in Figure 15. The amplitude of the A-phase ou creased because of the disturbance load when 0.8 s < t < 0.85 s. After A-phase output current ioA quickly returned to the steady state. As for turbance load had no effect because it was only added to the A-phase When the disturbance load was added to the A-phase, the output voltage of each phase was as shown in Figure 14a, and the FFT result of the A-phase output voltage was as shown in Figure 14b. THD = 3.28%, and the start time was 0.08 s. The change in the output voltage of each phase during the transient process was small.
When the disturbance load was added to the A-phase, the output current of each phase was as shown in Figure 15. The amplitude of the A-phase output current i oA increased because of the disturbance load when 0.8 s < t < 0.85 s. After that (t > 0.85 s), the A-phase output current i oA quickly returned to the steady state. As for i oB and i oC , the disturbance load had no effect because it was only added to the A-phase.
All these observed waveforms in the three-phase four-wire system are in good agreement with the theoretical analyses, confirming the feasibility of the proposed three-phase SCMLI in the three-phase four-wire system.
The recorded efficiency of different topologies is shown in Figure 16. The efficiency decreased with increasing output power. Compared with [27,30], the proposed topology has greater efficiency. The efficiency of the proposed topology is similar to that of [31]. As shown in Figure 17, the share of total conduction loss was larger than that of switching loss. This is because the switching frequency was at a normal level. Furthermore, the share of switching loss increased with decreasing output power. Therefore, decreasing the switching frequency can be adopted to improve the efficiency of the proposed topology when the output power is lower than 800 W.      Figure 15. The output current of each phase when the disturbance load was a All these observed waveforms in the three-phase four-wire system ment with the theoretical analyses, confirming the feasibility of the pr SCMLI in the three-phase four-wire system. has greater efficiency. The efficiency of the proposed topology is similar to that of [31]. As shown in Figure 17, the share of total conduction loss was larger than that of switching loss. This is because the switching frequency was at a normal level. Furthermore, the share of switching loss increased with decreasing output power. Therefore, decreasing the switching frequency can be adopted to improve the efficiency of the proposed topology when the output power is lower than 800 W.  To test the performance of the proposed three-phase SCMLI in a three-phase threewire system, the same resistive-inductive load transient is given. The A-phase bus voltage is shown in Figure 18a. Because uNO was not always equal to 0, the bus voltage had more voltage levels. The resistive-inductive load transient had no effect on the bus voltage. Figure 18b shows the DC-link capacitor voltages of the A-phase. The voltage ripple of these capacitors was 10 V. Figure 18c shows the floating capacitor voltages of the A-phase. They changed from 98-101 V to 96-104 V. All these waveforms met the voltage ripple requirements during the entire process. decreased with increasing output power. Compared with [27,30], the proposed topology has greater efficiency. The efficiency of the proposed topology is similar to that of [31]. As shown in Figure 17, the share of total conduction loss was larger than that of switching loss. This is because the switching frequency was at a normal level. Furthermore, the share of switching loss increased with decreasing output power. Therefore, decreasing the switching frequency can be adopted to improve the efficiency of the proposed topology when the output power is lower than 800 W.

Efficiency (%)
Output power (W) [Proposed] [31] [27] To test the performance of the proposed three-phase SCMLI in a three-phase threewire system, the same resistive-inductive load transient is given. The A-phase bus voltage is shown in Figure 18a. Because uNO was not always equal to 0, the bus voltage had more voltage levels. The resistive-inductive load transient had no effect on the bus voltage. Figure 18b shows the DC-link capacitor voltages of the A-phase. The voltage ripple of these capacitors was 10 V. Figure 18c shows the floating capacitor voltages of the A-phase. They changed from 98-101 V to 96-104 V. All these waveforms met the voltage ripple requirements during the entire process. To test the performance of the proposed three-phase SCMLI in a three-phase threewire system, the same resistive-inductive load transient is given. The A-phase bus voltage is shown in Figure 18a. Because u NO was not always equal to 0, the bus voltage had more voltage levels. The resistive-inductive load transient had no effect on the bus voltage. Figure 18b shows the DC-link capacitor voltages of the A-phase. The voltage ripple of these capacitors was 10 V. Figure 18c shows the floating capacitor voltages of the A-phase. They changed from 98-101 V to 96-104 V. All these waveforms met the voltage ripple requirements during the entire process.
The output voltage of each phase during a resistive-inductive load transient is shown in Figure 19a, and the FFT result of the A-phase output voltage is shown in Figure 19b. THD = 0.90%, and the start time was 0.12 s. Even in the first period after 0.12 s, the waveform quality of each phase output voltage satisfied the requirement. The output current of each phase under the same resistive-inductive load transient is shown in Figure 20. The transient process only lasted for a short period of time. The output current of each phase quickly changed from the initial steady state to a new steady state.
The problem of neutral-point voltage imbalance became more serious for traditional SCMLIs in the three-phase three-wire system. In contrast, these observed waveforms were in line with expectations, confirming that the proposed three-phase SCMLI achieves good performance in a three-phase three-wire system and there is no problem of neutral-point voltage imbalance.     The problem of neutral-point voltage imbalance became mo SCMLIs in the three-phase three-wire system. In contrast, these ob in line with expectations, confirming that the proposed three-pha

Comparison
To better illustrate the advantages of the proposed topology, a comprehensive comparison with other up-to-date SCMLIs in various aspects is shown in Table 4. The main advantages of the proposed topology are as follows: (1) Less capacitance (200 µF) is used. (3) Good performance is achieved in not only the three-phase four-wire system but also the three-phase three-wire system.
Most traditional three-phase SCMLIs [19,32,33] suffer from the problem of neutralpoint voltage imbalance, which becomes more serious in the three-phase three-wire system. Owing to the advantage above, the proposed topology can be adopted in more applications.
(4) Only one DC source is used as a three-phase topology.
The methods used in [20,26,27,30,31] all represent single-phase topologies. In the threephase applications, three DC sources are required for such topologies. This advantage of the proposed topology reduces the complexity and cost of the system. Not all floating capacitors were used to generate the top voltage level in [26,30]. The voltages of these floating capacitors are underused. This advantage of the proposed topology reduces the demand for capacitors.
Furthermore, the proposed topology is simple. Thirteen power switches are used in each phase, and the sum of their voltage stresses is only 11 V dc , which reaches the average level of other SCMLIs. Two DC-link capacitors and two floating capacitors in each phase are used, and the sum of their rated voltages is 4 V dc , which is not larger than that of the other three-phase SCMLIs. The proposed topology can generate seven voltage levels under different kinds of load conditions.

Conclusions
A novel three-phase SCMLI with reduced capacitance and balanced neutral-point voltage was proposed in this paper. Good performance was achieved in not only the threephase four-wire system but also the three-phase three-wire system. Only one DC source was used in the three-phase topology. A comprehensive comparison with other recently presented SCMLIs in various aspects was made, and simulation results under different kinds of load conditions were given. All observed waveforms were in good agreement with the theoretical analyses, confirming the feasibility of the proposed three-phase SCMLI.   Bus voltage. R dc1 , R dc2 , R 1 and R 2 000000000 Equivalent resistance of the devices. R 0 and C 0 It is assumed that R dc1 = R dc2 = R 1 = R 2 = R 0 and C dc1 = C dc2 = C 1 = C 2 = C 0 . R eq and C eq Equivalent resistance and equivalent capacitance of the charging topology. i s Current that flows through the DC source in the charging topology.
u Cd1 , u Cd2 , u C1 , u C2 Voltage of capacitors. i Cd1 , i Cd2 , i C1 , i C2 Current of capacitors. u Cdc1 (0), u Cdc2 (0), u C1 (0), u C2 (0) Initial voltage of capacitors. u eq (0) Initial voltage of the equivalent capacitor. u α , u β , u γ Adjustable parameters that represent the requirements of selecting the appropriate control strategy. i bus Bus current that flows through the filter inductor. Conduction loss of the output filters. i Lfi and r Lfi Current and internal resistance of the i-th filter inductor. i Cfi and r Cfi Current and internal resistance of the i-th filter capacitor. N fil Number of filters. P off(i,j) Switching loss caused by the j-th turning OFF process of the i-th switch.
V off(i,j) and I off(i,j) Voltage after the j-th turning OFF process of the i-th switch and current before the j-th turning OFF process of the i-th switch P on(i,j) Switching loss caused by the j-th turning ON process of the i-th switch.
V on(i,j) and I on(i,j) Voltage before the j-th turning ON process of the i-th switch and current after the j-th turning ON process of the i-th switch. P sw Total switching loss. N on(i) and N off(i) Number of i-th switch turning ON processes and turning OFF processes. η Overall efficiency of the proposed topology. P o Output power. Z o Load impedance. Z 1 Load condition that is adopted in this paper. R d A disturbance load that is only added to the A-phase temporarily.