K-Band Hetero-Stacked Differential Cascode Power Ampliﬁer with High Psat and Efﬁciency in 65 nm LP CMOS Technology

: A K-band complementary metal-oxide-semiconductor (CMOS) differential cascode power ampliﬁer is designed with the thin-oxide ﬁeld effect transistor (FET) common source (CS) stage and thick-oxide FET common gate (CG) stage. Use of the thick-oxide CG stage affords the high supply voltage to 3.7 V and enables the high output power. Additionally, simple analysis shows that the gain degradation due to the low cut-off frequency of the thick-oxide CG FET can be compensated by the high output resistance of the thick-oxide FET if the inter-stage node is neutralized. The measured results of the proposed power ampliﬁer demonstrate the saturated output power of the 23.3 dBm with the 31.3% peak power added efﬁciency (PAE) at 24 GHz frequency. The chip is fabricated in 65-nm low power (LP) CMOS technology and the chip size including all pads is 700 µ m × 630 µ m. curation, K.-J.C. and B.-S.K.; writing—original draft preparation, K.-J.C.; writing—review and editing, K.-J.C. and B.-S.K.; visualization, B.-S.K.; supervision, B.-S.K.; project administration, B.-S.K.; funding acquisition, B.-S.K. All authors have read and agreed to the published version of the manuscript.


Introduction
Rapid scaling of CMOS technology enables the mm-wave transceiver design including 5G mobile communications and automotive radar applications. Despite many advantages of the CMOS process, such as high-density integration of radio frequency (RF) and digital building blocks and low-cost mass manufacturing capability, the output power degradation due to the low breakdown voltage of highly scaled CMOS devices is a serious weakness for the design of RF power amplifiers. Accordingly, various design approaches for CMOS power amplifiers have been studied to achieve high efficiency and output power. Series voltage or parallel current combining techniques are essential to obtain high output power. Another approach to increase the output power is to stack the FETs for high voltage swing [1]. The larger the number of cascoded transistors increase, the higher the supply voltage can be used. Accordingly, the maximum output power also increases. However, the available number of stacked FETs is not unlimited due to breakdown issues in the common gate (CG) stage [2]. This paper presents a K-band differential power amplifier using the hetero-stacked cascode structure adopting two different gate oxide thicknesses. The common source (CS) stage uses a normal field effect transistor (FET) with the shortest gate length available from the process for high current driving capability, and the CG stage uses the thick-oxide FET for the high voltage swing. Though the hetero-stacked cascode power amplifier (PA) has been used for low GHz applications in a single-ended fashion [3], the PA above the X-band has not adopted this structure because of gain and efficiency degradation due to the low cut-off frequency of the thick-oxide FET. This work shows that the high gain as well as the high output power can be achieved near the cut-off frequencies of the thick CG FET by neutralizing the inter-stage node for the hetero-stacked cascode amplifier.

High Frequency Gain of the Neutralized Hetero-Stacked Cascode Amplifier
The thick-oxide common gate (CG) field effect transistor (FET) used in the cascode amplifier can enhance the output power by allowing a high supply voltage without multistage stacking. However, as the operation frequency increases, the efficiency and gain tend to more rapidly decrease because of the lower inter-stage pole frequency due to the smaller transconductance of the thick-oxide CG FET than the thin-oxide CG FET. But, examining the maximum available gain (MAG) of the cascode amplifier, neutralizing the inter-stage capacitances can surprisingly mitigate the effect of the cut-off frequency of the CG FET on the MAG. Figure 1a shows the hetero-stacked cascode power amplifier with a shunt inductor neutralization. The MAG of the neutralized cascode cell can be derived based on the small signal equivalent half circuit of the cascode cell shown in Figure 1b. The value of L neu for compensating C gs2 is determined by the resonance condition. For the differential amplifier design in mm-wave range, the stability of the common source (CS) FET is enforced by using the cross-coupled capacitor C neu , which achieves infinite isolation between the input and output of the CS FET as in [4]. Assuming the perfect neutralization as explained in [4], we simplified the analysis to calculate the MAG of the cascode cell ignoring C gd1 . At first, the available source power (P avs ) is given by (Equation (1)).
Electronics 2021, 10, x FOR PEER REVIEW 2 of 8 cies of the thick CG FET by neutralizing the inter-stage node for the hetero-stacked cascode amplifier.

High Frequency Gain of the Neutralized Hetero-Stacked Cascode Amplifier
The thick-oxide common gate (CG) field effect transistor (FET) used in the cascode amplifier can enhance the output power by allowing a high supply voltage without multi-stage stacking. However, as the operation frequency increases, the efficiency and gain tend to more rapidly decrease because of the lower inter-stage pole frequency due to the smaller transconductance of the thick-oxide CG FET than the thin-oxide CG FET. But, examining the maximum available gain (MAG) of the cascode amplifier, neutralizing the inter-stage capacitances can surprisingly mitigate the effect of the cut-off frequency of the CG FET on the MAG. Figure 1a shows the hetero-stacked cascode power amplifier with a shunt inductor neutralization. The MAG of the neutralized cascode cell can be derived based on the small signal equivalent half circuit of the cascode cell shown in Figure 1b. The value of Lneu for compensating Cgs2 is determined by the resonance condition. For the differential amplifier design in mm-wave range, the stability of the common source (CS) FET is enforced by using the cross-coupled capacitor Cneu, which achieves infinite isolation between the input and output of the CS FET as in [4]. Assuming the perfect neutralization as explained in [4], we simplified the analysis to calculate the MAG of the cascode cell ignoring Cgd1. At first, the available source power (Pavs) is given by (Equation (1)).
(a) (b) Figure 1. Hetero-stacked cascode power amplifier with a shunt inductor neutralization. The re-Scheme 1. ssuming the shunt neutralization at the input of the CG FET, the output resistance of the cascode cell is given by (Equation (2)) [5]. Under the conjugate matching condition at the output, the input resistance Rin2 of the CG FET is determined by (Equation (3)) as explained in [5].
In (Equations (2) and (3)), the resistance rp is a parallel equivalent resistance combining ro1 and RLP. Then the available output power (Pavo) is given by (Equation (4)). The Assuming the shunt neutralization at the input of the CG FET, the output resistance of the cascode cell is given by (Equation (2)) [5]. Under the conjugate matching condition at the output, the input resistance R in2 of the CG FET is determined by (Equation (3)) as explained in [5].
R out2 = (r o2 + r p (1 + g m2 r o2 )) ≈ g m2 r p r o2 (2) Electronics 2021, 10, 890 3 of 9 In (Equations (2) and (3)), the resistance r p is a parallel equivalent resistance combining r o1 and R LP . Then the available output power (P avo ) is given by (Equation (4)). The input current of the CG FET from the output current of the CS FET can be determined by current division between R in2 and r p . Additionally, the output resistance R out2 and the load resistance R load equally share the output current of the cascode cell under conjugate matching condition, a half of the output current of CG FET is delivered to R load . In (Equation (5)), the P avo is expressed in terms of the input current instead of the voltage V gs1 since the available source power is expressed using the input current I g . The P avo in (Equation (6)) is obtained by using (Equations (2) and (3)) for R out2 and R in2 in (Equation (5)) at the neutralizing frequency f 0 .
Introducing the quality factor Q int (=2πf 0 C gs2 r p ) at the inter-stage node excluding R in2 , the final P avo is obtained as follows.
In (Equation (7)), f t1 and f t2 are cut-off frequencies of CS and CG FET given by g m1 /2πC gs1 and g m2 /2πC gs2 , respectively. The final P avo (Equation (7)) is expressed using the cut-off frequency of FETs and neutralization frequency to evaluate and compare the effect of neutralization in terms of the cut-off frequency of the CG FET.
The resistance R LP is a parallel equivalent resistance of the neutralizing inductor L neu given by where Q L is the quality factor of the neutralizing inductor. As seen in (Equation (8)), R LP decreases as the operation frequency increases, considering that the available maximum Q factor of the inductor in CMOS process is limited. Finally, MAG is obtained as the ratio of P avo and P avs as follows.
When the operation frequency satisfies the following condition, The MAG at the neutralizing frequency can be approximated as (Equation (11)).
The result of (Equation (11)) implies that the MAG of the neutralized cascode cell is linearly proportional to f t2 , unlike the quadratic dependence on f t1 of the CS FET. This behaviour is valid regardless of the gate lengths of CG FETs. It means that the effect of f t2 on the total gain of the cascode cell appears relatively smaller than f t1 . Especially, the Electronics 2021, 10, 890 4 of 9 high output resistance of the thick-oxide CG FET additionally compensates the low cut-off frequency of its own. Since the cut-off frequency and the output resistance of CMOS FET are inversely and proportionally dependent on the gate length, the overall gain of the cascode cell using the thick-oxide CG stage is almost comparable to that using all thin-oxide FETs around the neutralizing frequency while the condition (Equation (10)) holds. In fact, the node Q factor Q int initially increases with neutralizing frequency because the resistance r p is dominated by r o1 at low frequencies. However, as the frequency goes high, the resistance r p gradually decreases with the neutralizing frequency due to the relation (Equation (8)). Therefore, Q int eventually saturates to the constant value and gain compensation by neutralization is relaxed.
The MAGs of two cascode cells based on (Equation (9)) are compared in Figure 2 as a function of the neutralizing frequency using extracted equivalent circuit parameters of two cascode cells using the same widths for CS/CG FETs and bias current conditions. In the relatively low frequency, the hetero-stacked cascode cell shows the higher gain up to 1.7 dB compared to the normal cascode cell because of the sufficient compensation by the Q int and high output resistance of thick-oxide CG FET. As neutralization frequency increases, the MAGs become similar and finally the normal cascode cell shows a higher gain above 90 GHz.
Electronics 2021, 10, x FOR PEER REVIEW gain of the cascode cell using the thick-oxide CG stage is almost compara ing all thin-oxide FETs around the neutralizing frequency while the cond (10)) holds. In fact, the node Q factor Qint initially increases with neutrali because the resistance rp is dominated by ro1 at low frequencies. Howev quency goes high, the resistance rp gradually decreases with the neutraliz due to the relation (Equation (8)). Therefore, Qint eventually saturates t value and gain compensation by neutralization is relaxed.
The MAGs of two cascode cells based on (Equation (9)) are compared a function of the neutralizing frequency using extracted equivalent circuit two cascode cells using the same widths for CS/CG FETs and bias current the relatively low frequency, the hetero-stacked cascode cell shows the hig 1.7 dB compared to the normal cascode cell because of the sufficient com the Qint and high output resistance of thick-oxide CG FET. As neutraliza increases, the MAGs become similar and finally the normal cascode cell s gain above 90 GHz.  Figure 3 shows the schematic of the proposed differential hetero-st power amplifier composed of the thin-oxide common source (CS) field e (FET), thick-oxide common gate (CG) FET, and neutralization inductor L ential architecture is chosen for easy neutralization compared to the singl ture and an additional capacitive neutralization for the CS stage.  Figure 3 shows the schematic of the proposed differential hetero-stacked cascode power amplifier composed of the thin-oxide common source (CS) field effect transistor (FET), thick-oxide common gate (CG) FET, and neutralization inductor L neu . The differential architecture is chosen for easy neutralization compared to the single-ended structure and an additional capacitive neutralization for the CS stage.

MAG Simulation Verification
According to the accurate simulation, the hetero-stacked cascode cell without neutralization shows the higher gain below 19 GHz because of the higher output resistance of the thick-oxide CG FET, and the inter-stage pole is negligible at low frequencies as shown in Figure 4a. However, the maximum available gain (MAG) of the hetero-stacked cascode cell without inductive neutralization is lower than that of the normal cascode cell by 3.5 dB at 24 GHz. Adopting neutralization at 24 GHz for both cascode cells, the hetero-stacked cascode shows the higher MAG up to 34 GHz and 1.5 dB higher MAG than normal cascode cell at 24 GHz as shown in Figure 4b.  Figure 3 shows the schematic of the proposed differential hetero-stacked cascode power amplifier composed of the thin-oxide common source (CS) field effect transistor (FET), thick-oxide common gate (CG) FET, and neutralization inductor Lneu. The differential architecture is chosen for easy neutralization compared to the single-ended structure and an additional capacitive neutralization for the CS stage.  According to the accurate simulation, the hetero-stacked cascode cell without neutralization shows the higher gain below 19 GHz because of the higher output resistance of the thick-oxide CG FET, and the inter-stage pole is negligible at low frequencies as shown in Figure 4a. However, the maximum available gain (MAG) of the hetero-stacked cascode cell without inductive neutralization is lower than that of the normal cascode cell by 3.5 dB at 24 GHz. Adopting neutralization at 24 GHz for both cascode cells, the hetero-stacked cascode shows the higher MAG up to 34 GHz and 1.5 dB higher MAG than normal cascode cell at 24 GHz as shown in Figure 4b.   Figure 5 shows the simulation results of the MAGs when neutralization is performed at every frequency to confirm the previous analysis. Results of Figure 5 consider all parasitics of passive networks using full-wave electromagnetic simulation. Increasing neutralization frequency by reducing the value of Lneu of the same component QL-value, the gain cross-over frequency is found to be approximately 60 GHz, which is slightly lower than the predicted in Figure 2. It is because the simple small signal model presented by Figure  1b ignores additional parasitic capacitances of the real cascode cells. However, surprisingly, the hetero-stacked cascode cell shows the higher gain than the normal cascode cell even beyond the cut-off frequency about 40 GHz of the thick-oxide CG FET. This result shows that the low cut-off frequency of thick-oxide FET is compensated by its high output resistance.   Figure 5 shows the simulation results of the MAGs when neutralization is performed at every frequency to confirm the previous analysis. Results of Figure 5 consider all parasitics of passive networks using full-wave electromagnetic simulation. Increasing neutralization frequency by reducing the value of L neu of the same component Q L -value, the gain cross-over frequency is found to be approximately 60 GHz, which is slightly lower than the predicted in Figure 2. It is because the simple small signal model presented by Figure 1b ignores additional parasitic capacitances of the real cascode cells. However, surprisingly, the hetero-stacked cascode cell shows the higher gain than the normal cascode cell even beyond the cut-off frequency about 40 GHz of the thick-oxide CG FET. This result shows that the low cut-off frequency of thick-oxide FET is compensated by its high output resistance.

Measurement Results
1b ignores additional parasitic capacitances of the real cascode cells. Howev ly, the hetero-stacked cascode cell shows the higher gain than the normal ca beyond the cut-off frequency about 40 GHz of the thick-oxide CG FET. Thi that the low cut-off frequency of thick-oxide FET is compensated by its h sistance.

Measurement Results
The chip microphotograph is shown in Figure 6. The chip size is 0.7 cluding all pads. The proposed PA is fabricated using 65-nm low power (LP

Measurement Results
The chip microphotograph is shown in Figure 6. The chip size is 0.7 × 0.63 mm 2 including all pads. The proposed PA is fabricated using 65-nm low power (LP) CMOS technology with 0.57 mA/um current density and 1-poly 8-metal layers. The supply voltage is 3.7 V and DC power dissipation is 466 mW under quiescent condition.  Measured and simulated S-parameters are plotted in Figure 7a. The measured small signal gain is 14.6 dB and the input return loss is -9.4 dB for 24 GHz. Figure 7b shows the measured power gain, output power, and power added efficiency (PAE) of the proposed PA with a 24 GHz 1-tone continuous wave (CW) signal. The large signal measurement results demonstrate 15.4 dB gain, saturated output power of 23.3 dBm, output 1-dB compression point of 20.8 dBm, and peak PAE of 31.3% at 24 GHz. The large signal performance versus different frequencies is shown in Figure 7c from 22 GHz to 28 GHz. Performance comparison with recent state-of-art K-band CMOS PAs is shown in Table 1. Though the higher output powers were reported in [6,9,10], they were obtained utilizing the parallel power combining techniques for unit amplifiers. Since the proposed hetero-stacked cascode power amplifier only used a unit amplifier and N-way combining can be used for more output power.

Conclusions
In this paper, a K-band hetero-stacked cascode CMOS PA with high saturated output power and efficiency is presented. The PA is fabricated in 65-nm low power (LP) CMOS process stacking the thin-oxide field effect transistor (FET) and thick-oxide FET for cascode configuration with neutralization. The hetero-stacked cascode structure can enhance the output power by using a high supply voltage compared to the normal cascode structure. But using a hetero-stacked cascode in the mm-wave range, the high frequency gain degradation occurs due to low cut-off frequency of the thick-oxide common gate (CG) FET. If the inductive neutralization is applied to the inter-stage of the hetero-stacked cascode cell as used in this work, the high frequency gain degradation can be compensated by high output resistance of the thick-oxide CG FET. Additionally, this work analyses the effect of inter-stage neutralization on the gain improvement of the cascode cell. The analysis shows that the proposed cascode amplifier provides a comparable gain to the normal cascode amplifier near the cut-off frequency of the thick-oxide CG FET. The proposed cascode structure is advantageous to easily enhance the output power without gain degradation and complicated power combining techniques in the mm-wave range.