Ten-Bit 0.909-MHz 8-Channel Dual-Mode Successive Approximation ADC for a BLDC Motor Drive

This paper presents a 10-bit 0.909-MHz 8-channel dual-mode successive approximation (SAR) analogue-to-digital converter (ADC) for brushless direct current (BLDC) motor drive, using a Taiwan Semiconductor Manufacturing (TSMC) 0.25 μm 1P3M Complementary Metal Oxide Semiconductor (CMOS) process. The sample-and-hold (S/H) circuit operates with two sampling modes. One is individually sampling eight channels in sequence with an S/H circuit and the other is sampling four channels simultaneously with four S/H circuits. All sampled data will be digitized with high-speed SAR ADC in time division multiplexing (TDM). A dynamic latch-type comparator is utilized to latch the output at an upper or lower level. The advantage of the designed comparator is that it performs with positive feedback to quickly complete the latch function. The double-tail latch-type architecture is utilized to mitigate the significant kickback effect by separating the pre-amplifier stage from the latch. By integrating an input NMOSFET with an input PMOSFET, the designed latch-type comparator can perform with full-swing input voltage. Measurements show that the signal-to-noise ratio (SNR), signal-to-noise-and-distortion ratio (SNDR), effective number of bits (ENOB), power consumption, and chip area are 50.56 dB, 57.03 dB, 8.11 bits, 833 μW, and 1.35 × 0.98 mm2, respectively. The main advantages of the proposed multichannel dual-mode SAR ADC are its low power consumption of 833 μW and high measured resolution of 8.11 bits.


Introduction
This paper proposed a 10-bit 2.27 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with two sampling modes and an eight-channel switch, which is usually used in the brushless direct current (BLDC) motor. BLDC motor is generally characterized by higher efficiency, lower maintenance, higher cost, and small volume [1]. A new digital control concept for BLDC machine has been introduced, experimentally verified, and implemented in a low-cost application-specific integrated circuit (ASIC). The field programmable gate array (FPGA)-based new digital pulse-width modulation (PWM) controller results in a considerable reduction of size and the cost of the system for BLDC motor drive [1]. Besides, the optical sensor can be used to measure the rotation speed of BLDC motor using the pulse width modulation (PWM) and the serial interface can be implemented using an energy-effective eight-bit SAR ADC [2]. To improve the performance of BLDC motor, integrating the ADC with control circuits is a good idea for electric vehicle, especially for high-voltage process. This idea had been published in [3] by integrating the permanent-magnet synchronous motor (PMSM) with a 10-bit SAR ADC.
To have low power consumption motor drive, the SAR ADC is popular for integration with electric vehicle control circuits because it performs with a continuous progressive tion with electric vehicle control circuits because it performs with a continuous pr sive characteristic and does not need a high-performance operational amplifier. A speed low-power SAR ADC circuit with 8-bit accuracy and 1.25 GSPS sampling ra been published based on TSMC 28 nm CMOS technology [4]. Low power consum and high accuracy are main advantages of SAR ADC [5]. Neither a micro-contro (MCU), nor analog-to-digital converters (ADCs) are required with the proposed sen architecture to achieve low-cost but high-performance sensorless control IC for BLD tor, with wide speed ranges [6]. However, the whole architecture is evaluated w FPGA-based system, which occupies great volume and operates with high powe sumption. Figure 1 shows the proposed control circuits of electric vehicle for BLDC m which is composed of digital controller, gate driver, detectors, SAR ADC, channel re DC-DC buck converter, and BLDC Motor. The multi-channel detectors are used to and monitor those useful parameters, including average current, peak current, ove rent, temperature, speed, and so on. After those sensing data have been digitalized SAR ADC, the digital control code can be fed into the controller and generates an a priate pulse-width modulation (PWM) signal to control the gate driver and to dri BLDC motor smoothly. In brief, the designed SAR ADC is a key component in BLD tor drive. The rest of this paper is organized as follows. Section II elucidates the design of the proposed SAR ADC and its relational circuits. Section III presents the layout simulation and measurement results, and the conclusion is drawn in Section  Figure 2 shows the schematic of the proposed 10-bit SAR ADC with multiple for BLDC motor drive. The proposed SAR ADC can be divided into five subcircu cluding the 8-way switch control system, sample and hold (S/H) circuit, digital-to-a converter (DAC), comparator, and successive approximation register (SAR). The o tional principle of the proposed SAR ADC is a binary search algorithm. It operates in modes, including the sampling mode, hold mode, and charge redistribution mode.  Figure 2 shows the schematic of the proposed 10-bit SAR ADC with multiple inputs for BLDC motor drive. The proposed SAR ADC can be divided into five subcircuits, including the 8-way switch control system, sample and hold (S/H) circuit, digital-toanalog converter (DAC), comparator, and successive approximation register (SAR). The operational principle of the proposed SAR ADC is a binary search algorithm. It operates in three modes, including the sampling mode, hold mode, and charge redistribution mode.   Figure 3 shows the designed 8-way switch control system, which is composed of three selection signals, se2-se0, to control 8 witches, t7-t0, and two mode signals, ma and mb. In the first sampling mode (M = 0), a set of S/H circuit (SH0) is assigned to sample 8 input signals (V7-V0) in sequence. The second sampling mode (M = 1) means that 4 sets of S/H circuits (SH3-SH0) are used to sample 4 input signals simultaneously. For an 8way input signals, we need two steps to complete the second sampling mode. The first step (ma = 1) samples the most significant bit (MSB) group with 4 input signals, V7-V4 Next, the least significant bit (LSB) group (V3-V0) would be sampled in the second step (Mb = 1). Table 1 shows the control signals of the 8-way switch control system. In the firs sampling mode (M = 0) (blue color), the input signal is determined with three selection signals, se2-se0 (yellow color), and is stored in the first S/H circuit (SH0) in sequence (red color)). In the second sampling mode (M = 1) (purple color), 4 input signals are sampled simultaneously. If the third selection signal se2 is set to 1, the MSB group, V7-V4, are sampled and stored in 4 S/H circuits, SH0-SH3, respectively (green color). On the contrary the LSB group, V3-V0, are sampled and stored in 4 S/H circuits, SH0-SH3, respectively when the third selection signal se2 is equal to 0 (pink color). The significant problem presented in the development of time-multiplexed channels is the inter-channel cross talk Such cross talk may occur accidentally because of the long inductive leads, insufficient decoupling of circuits containing inductances, and other causes [7]. It is advisable to determine the effect on the phase response of slight variations in component tolerances Phase-lock loop (PLL) is a good choice, not only to eliminate the phase variation, but also to mitigate the cross talk.  Figure 3 shows the designed 8-way switch control system, which is composed of three selection signals, se2-se0, to control 8 witches, t7-t0, and two mode signals, ma and mb. In the first sampling mode (M = 0), a set of S/H circuit (SH0) is assigned to sample 8 input signals (V7-V0) in sequence. The second sampling mode (M = 1) means that 4 sets of S/H circuits (SH3-SH0) are used to sample 4 input signals simultaneously. For an 8-way input signals, we need two steps to complete the second sampling mode. The first step (ma = 1) samples the most significant bit (MSB) group with 4 input signals, V7-V4. Next, the least significant bit (LSB) group (V3-V0) would be sampled in the second step (Mb = 1). Table 1 shows the control signals of the 8-way switch control system. In the first sampling mode (M = 0) (blue color), the input signal is determined with three selection signals, se2-se0 (yellow color), and is stored in the first S/H circuit (SH0) in sequence (red color)). In the second sampling mode (M = 1) (purple color), 4 input signals are sampled simultaneously. If the third selection signal se2 is set to 1, the MSB group, V7-V4, are sampled and stored in 4 S/H circuits, SH0-SH3, respectively (green color). On the contrary, the LSB group, V3-V0, are sampled and stored in 4 S/H circuits, SH0-SH3, respectively, when the third selection signal se2 is equal to 0 (pink color). The significant problem presented in the development of time-multiplexed channels is the inter-channel cross talk. Such cross talk may occur accidentally because of the long inductive leads, insufficient decoupling of circuits containing inductances, and other causes [7]. It is advisable to determine the effect on the phase response of slight variations in component tolerances. Phase-lock loop (PLL) is a good choice, not only to eliminate the phase variation, but also to mitigate the cross talk.     Figure 4 depicts the proposed sample and hold circuit, which is a switch with a constant gate to source voltage Vgs [8]. It is made of a sampling capacitor CS and a simple NMOSFET MA9 driven by the boosted driver to achieve both low power and wide bandwidth. The boosted driver produces a periodical output switching between VDD + Vin and the input voltage Vin. Two PMOSFETs, MA3 and MA5, are utilized to alleviate the errors induced by charge injection and clock feed-through because they conduct interactively. If clk = 0, then MA4 and MA8 turn on simultaneously. Next, the MA3 turns on because MA7 and MA8 are connected to ground. The sampling capacitor CS is charged to VDD rapidly. Besides, MA5 turns off by connecting to VDD through MA1 and two NMOSFETs, MA6 and  Figure 4 depicts the proposed sample and hold circuit, which is a switch with a constant gate to source voltage V gs [8]. It is made of a sampling capacitor C S and a simple NMOSFET MA 9 driven by the boosted driver to achieve both low power and wide bandwidth. The boosted driver produces a periodical output switching between V DD + V in and the input voltage V in . Two PMOSFETs, MA3 and MA5, are utilized to alleviate the errors induced by charge injection and clock feed-through because they conduct interactively. If clk = 0, then MA4 and MA8 turn on simultaneously. Next, the MA3 turns on because MA7 and MA8 are connected to ground. The sampling capacitor C S is charged to V DD rapidly. Besides, MA5 turns off by connecting to V DD through MA1 and two NMOSFETs, MA6 and MA9, are off by setting to ground through MA7 and MA8. Contrarily, if clk = 1, the MA5 turns on by setting the gate of MA5 to ground through MA2 and the source of MA5 to V DD , simultaneously. Note, both supply voltages, V DD and ground, are stored in the sampling capacitor C S in previous clock (clk = 0). After the MA5 turns on, the MA6 will be turned on. Therefore, the lower plate of Cs is connected to the input voltage V in through MA6, and the upper plate of C S will be lifted up to V DD + V in . Passing through MA5, the gate-source voltage V gs of MA9 is fixed to V DD , regardless of the variation of input voltage V in . That is, the output voltage V out would not be adversely affected by the errors of MA6 and MA9, which are induced by charge injection and clock feed-through [2]. Note that all transistors, including NMOSFETS and PMOSFETs, are operating in saturation mode. Table 2 shows the simulated results of the proposed S/H circuit with five design corners. The power supply, sampling frequency, input swing, and input frequency are 3.3 V, 5 MHz, 0-VDD, and 100 kHz, respectively. The effective number of bits (ENOB) and power consumption perform uniformly. The simulated differential nonlinearity (DNL) locates between −1 and +1 LSB. The performance of the proposed S/H circuit satisfies the required specification even though the simulated INL is larger than 1.0 LSB.

Capacitive Digital-to-Analog Converter
In this study, a binary-weighted capacitive digital-to-analog converter (DAC) is considered to complete the required DAC circuit. The capacitive DAC performs with high density and high accuracy by combining the properties of the binary-weighted and the serial charge-redistribution DACs. This architecture operates with low integral nonlinearity (INL), good matching, and high tolerance to parasitic capacitance [9]. The designed DAC allows an efficient optimization based on the specifications of chip area, conversion speed, and linearity. Figure 5 shows the adopted 10-bit binary-weighted capacitive DAC with 11 capacitors denoted by C = {C0, C1, …, C10} with a ratio of C0: C1: C2: …: C10 be 1: 2 0 : 2 1 : 2 2 : …: 2 9 , respectively [10]. Then the total number of capacitors Ctotal are equal to 2 10 unit capacitors (C0).  Table 2 shows the simulated results of the proposed S/H circuit with five design corners. The power supply, sampling frequency, input swing, and input frequency are 3.3 V, 5 MHz, 0-V DD , and 100 kHz, respectively. The effective number of bits (ENOB) and power consumption perform uniformly. The simulated differential nonlinearity (DNL) locates between −1 and +1 LSB. The performance of the proposed S/H circuit satisfies the required specification even though the simulated INL is larger than 1.0 LSB.

Capacitive Digital-to-Analog Converter
In this study, a binary-weighted capacitive digital-to-analog converter (DAC) is considered to complete the required DAC circuit. The capacitive DAC performs with high density and high accuracy by combining the properties of the binary-weighted and the serial charge-redistribution DACs. This architecture operates with low integral nonlinearity (INL), good matching, and high tolerance to parasitic capacitance [9]. The designed DAC allows an efficient optimization based on the specifications of chip area, conversion speed, and linearity. Figure 5 shows the adopted 10-bit binary-weighted capacitive DAC with 11 capacitors denoted by C = {C 0 , C 1 , . . . , C 10 } with a ratio of C 0 : C 1 : C 2 : . . . : C 10 be 1: 2 0 : 2 1 : 2 2 : . . . : 2 9 , respectively [10]. Then the total number of capacitors C total are equal to 2 10 unit capacitors (C 0 ).  For a 10-bit SAR ADC, we need 11 switches, S0−S10, and 11 conversion steps, Q0-Q10, to complete the conversion process. The first step (cycle) Q0 is a reset state, which is completed in the previous conversion process. In the reset state, the DAC voltage VDAC is connected to ground by setting S0 to 1 and the remainder switches, S1−S10, to 0. In the second step (Q10), the switch S10 is set to 1 and the MSB capacitor is connected to the reference voltage VREF and the VDAC is charged into the half a reference voltage (= 0.5 × VREF). If the input voltage VS/H, which is fed from the S/H circuit, is larger than VDAC, the output digital code is set to 1 (D10 = 1). Otherwise, the output code is 0. A register is used to store the output digital code and keep it until the end of the conversion process. Next, the switch S9 is set to 1 and the S10 is set to D10, a new VDAC is generated and compared to next input voltage VS/H. A new output digital code D9 is obtained and stored into the register. The following steps (Q8-Q1) will be completed in a similar fashion. Note that the last step is a reset state (Q0) (blue color in bold), which is prepared for the next conversion process. Table 3 presents the state table of the DAC switches and the output digital codes. Table 3. State table of DAC switches (S0 − S10) and output digital codes (D).

Dynamic Comparator with Complementary Inputs
A comparator is an important circuit for designing SAR ADC. Both offset and complexities of the comparison process will seriously affect the accuracy and conversion rate of the designed SAR ADC. A dynamic latch-type comparator is utilized to latch the output at upper or lower level based on the voltage difference between two input nodes. The advantage of the designed comparator is that it performs with positive feedback to quickly complete the latch function. A voltage-type comparator has become especially popular because of their high input impedance, full-swing output, and absence of static power consumption [11].
The double-tail latch-type architecture, which was published in [11], is utilized to mitigate the significant kickback effect by separating the pre-amplifier stage from the latch For a 10-bit SAR ADC, we need 11 switches, S 0 -S 10 , and 11 conversion steps, Q 0 -Q 10 , to complete the conversion process. The first step (cycle) Q 0 is a reset state, which is completed in the previous conversion process. In the reset state, the DAC voltage V DAC is connected to ground by setting S 0 to 1 and the remainder switches, S 1 − S 10 , to 0. In the second step (Q 10 ), the switch S 10 is set to 1 and the MSB capacitor is connected to the reference voltage V REF and the V DAC is charged into the half a reference voltage (=0.5 × V REF ). If the input voltage V S/H , which is fed from the S/H circuit, is larger than V DAC , the output digital code is set to 1 (D 10 = 1). Otherwise, the output code is 0. A register is used to store the output digital code and keep it until the end of the conversion process. Next, the switch S 9 is set to 1 and the S 10 is set to D 10 , a new V DAC is generated and compared to next input voltage V S/H . A new output digital code D 9 is obtained and stored into the register. The following steps (Q 8 -Q 1 ) will be completed in a similar fashion. Note that the last step is a reset state (Q 0 ) (blue color in bold), which is prepared for the next conversion process. Table 3 presents the state table of the DAC switches and the output digital codes.

Dynamic Comparator with Complementary Inputs
A comparator is an important circuit for designing SAR ADC. Both offset and complexities of the comparison process will seriously affect the accuracy and conversion rate of the designed SAR ADC. A dynamic latch-type comparator is utilized to latch the output at upper or lower level based on the voltage difference between two input nodes. The advantage of the designed comparator is that it performs with positive feedback to quickly complete the latch function. A voltage-type comparator has become especially popular because of their high input impedance, full-swing output, and absence of static power consumption [11].
The double-tail latch-type architecture, which was published in [11], is utilized to mitigate the significant kickback effect by separating the pre-amplifier stage from the latch [12]. To have a full-swing input, the designed comparator must limit the threshold voltage of PMOSFET and NMOSFET. For an input NMOS transistor, the latch-type comparator is limited to a lower limited voltage, which is equal to the threshold voltage of NMOS transistor (V thN ). If an input PMOS transistor is only considered, an upper limited voltage, which is equal to V DD -V thP , is achieved with a threshold voltage of PMOSFET V thP . By integrating an input NMOSFET with an input PMOSFET, the designed latch-type comparator can compensate this shortcoming and perform with full-swing input voltage. Furthermore, the authors want to state clearly that the common-mode voltage V cm of the comparator must be well controlled if the input is single-ended. As shown in Figure 6, if the inputs with large and small Vcm need to be processed by NMOSFET, and PMOSFET input transistors, respectively, the authors can expect they have differential offset and noise performances.  Figure 7 shows a logic circuit diagram of the conversion step, which is used to generate 11 step signals, Q0−Q10. Combining the step signals (Q0-Q10) with the output digital codes (D1-D10), the proposed DAC operates correctly by controlling those 11 DAC switches, S0-S10. Figure 8 presents the signal generation circuit of DAC switch Sn with integer n from 1 to 10. As shown in Figure 8, the Q0 and Qn are generated from Figure 7. The input signal of comp_end is an exclusive OR (XOR) function of VOUTP and VOUTN, which are shown in Figure 6. The reset signal RST is generated with clock signal (clk), logic circuit, and nonoverlap circuit. Figure 9 shows the simulated waveforms of DAC switches. The proposed circuit works correctly.  Figure 6 presents the proposed complementary-input double-tail latch-type voltage comparator. If the clock signal CLK is set to 0, both NMOSFETs, ML5 and ML6, turn on simultaneously and the differential outputs, V OUTN and V OUTP , are connected to ground. The reset function is completed. In the meantime, MN10, MN13, and MN14 turn off, on, and on, respectively. Both outputs, N N and N P , are pulled up to V DD . Similarly, MP10, MP13, and MP14 turn off, on, and on, respectively, and both P N and P P are connected to ground. Next, MP15 and MP16 turn on and P N is connected to V DD , so does P P . Then four PMOSFETs, ML7-ML10, turn off. Both outputs, V OUTN and V OUTP , are connected to ground stably and save the static power consumption. In the comparing mode, the clock  (1). Both MP10 and MN10 turn on and those outputs, P N , P P , N N , and N P , can be determined with two inputs, V INN and V INP . If V INP > V INN , then the voltage of N P is low (0) and ML10 conducts. Therefore, the positive output V OUTP is high (1) and ML1 conducts. The negative output V OUTN is low (0). Note that the discharge speeds of outputs, N N , N P , P N and P P , are different due to the voltage difference between two inputs, V INN and V INP . Besides, if the input V INP is high (1) and the V INN is low (0), then the output V OUTP is high (1) and the V OUTN is low (0). This result verifies that the proposed comparator performs with positive feedback to achieve the latch function quickly. Two inverters are added between the P-type pre-amplifier and the latch stage to reverse the control signal and to guarantee that the output is high (1) through PMOS transistor and the output is low (0) via NMOS transistor. Figure 7 shows a logic circuit diagram of the conversion step, which is used to generate 11 step signals, Q 0 -Q 10 . Combining the step signals (Q 0 -Q 10 ) with the output digital codes (D 1 -D 10 ), the proposed DAC operates correctly by controlling those 11 DAC switches, S 0 -S 10 . Figure 8 presents the signal generation circuit of DAC switch S n with integer n from 1 to 10. As shown in Figure 8, the Q 0 and Q n are generated from Figure 7. The input signal of comp_end is an exclusive OR (XOR) function of V OUTP and V OUTN , which are shown in Figure 6. The reset signal RST is generated with clock signal (clk), logic circuit, and nonoverlap circuit. Figure 9 shows the simulated waveforms of DAC switches. The proposed circuit works correctly.  Figure 7 shows a logic circuit diagram of the conversion step, which is used to generate 11 step signals, Q0−Q10. Combining the step signals (Q0-Q10) with the output digital codes (D1-D10), the proposed DAC operates correctly by controlling those 11 DAC switches, S0-S10. Figure 8 presents the signal generation circuit of DAC switch Sn with integer n from 1 to 10. As shown in Figure 8, the Q0 and Qn are generated from Figure 7. The input signal of comp_end is an exclusive OR (XOR) function of VOUTP and VOUTN, which are shown in Figure 6. The reset signal RST is generated with clock signal (clk), logic circuit, and nonoverlap circuit. Figure 9 shows the simulated waveforms of DAC switches. The proposed circuit works correctly.       Figure 10 shows the simulated power spectrum density (PSD) of the proposed sample and hold circuit. The 8192-point fast Fourier transform (FFT) simulation presents that the simulated SFDR is 71.51 dB, which is equal to 11.59 bits, at the input frequency of 100 kHz, sampling frequency of 5 MS/s, power supply of 3.3 V, and power consumption of 10.89 µW. As shown in Table 2, the simulated resolution of 11.59 bits at TT mode satisfies the design requirement of the sample and hold circuit in a 10-bit SAR ADC.  Figure 10 shows the simulated power spectrum density (PSD) of the proposed sample and hold circuit. The 8192-point fast Fourier transform (FFT) simulation presents that the simulated SFDR is 71.51 dB, which is equal to 11.59 bits, at the input frequency of 100 kHz, sampling frequency of 5 MS/s, power supply of 3.3 V, and power consumption of 10.89 µW. As shown in Table 2, the simulated resolution of 11.59 bits at TT mode satisfies the design requirement of the sample and hold circuit in a 10-bit SAR ADC. As shown in Figure 6, if the common-mode voltage VCM is set to 0.1 V, two NMOSs, MN11 and MN12, turn off and two PMOSs, MP11 and MP12, turn on, simultaneously. Then four node voltages, NN, NP, PN, and PP, were pulled up to VDD and two node voltages, PN' and PP', were pushed down to ground by passing through inverters. As the differential input voltage ∆Vin of 1.0 mV, the discharge rate are different at node voltages, NN, NP, PN', and PP'. Then the differential output voltages, VOUTP and VOUTN, will be latched to VDD (3.3 As shown in Figure 6, if the common-mode voltage V CM is set to 0.1 V, two NMOSs, MN11 and MN12, turn off and two PMOSs, MP11 and MP12, turn on, simultaneously.

Simulated and Measurement Results
Then four node voltages, N N , N P , P N , and P P , were pulled up to V DD and two node voltages, P N' and P P' , were pushed down to ground by passing through inverters. As the differential input voltage ∆V in of 1.0 mV, the discharge rate are different at node voltages, N N , N P , P N' , and P P' . Then the differential output voltages, V OUTP and V OUTN , will be latched to V DD (3.3 V), and ground (0 V), respectively, by passing through the latch stage with cross-connected inverters and positive feedback. Figure 11 shows the simulation waveforms of the proposed comparator with V CM = 0.1 V and ∆V in = 1.0 mV. Figure 10. Simulated power spectrum density (PSD) of the proposed sample and hold circuit.
As shown in Figure 6, if the common-mode voltage VCM is set to 0.1 V, two NMOSs, MN11 and MN12, turn off and two PMOSs, MP11 and MP12, turn on, simultaneously. Then four node voltages, NN, NP, PN, and PP, were pulled up to VDD and two node voltages, PN' and PP', were pushed down to ground by passing through inverters. As the differential input voltage ∆Vin of 1.0 mV, the discharge rate are different at node voltages, NN, NP, PN', and PP'. Then the differential output voltages, VOUTP and VOUTN, will be latched to VDD (3.3 V), and ground (0 V), respectively, by passing through the latch stage with cross-connected inverters and positive feedback. Figure 11 shows the simulation waveforms of the proposed comparator with VCM = 0.1 V and ∆Vin = 1.0 mV.  If the common-mode voltage V CM is set to 3.3 V, two NMOSs, MN11 and MN12, turn on and two PMOSs, MP11, and MP12, turn off, simultaneously. Then four node voltages, N P , N N , P P , and P N , were pushed down to ground and two node voltages, P N' and P P' , were pulled up to V DD by passing through inverters. As the differential input voltage ∆V in of 1.0 mV, the discharge rate are different at nodes, N N , N P , P N' , and P P' . Thus the differential output voltages, V OUTP and V OUTN , were connected to V DD (3.3 V) and ground (0 V), respectively, by passing through the latch stage with cross-connected inverter and positive feedback. Figure 12 shows the simulation waveforms of the proposed comparator with V CM = 3.3 V and ∆V in = 1.0 mV. Note that the delay time is appropriately 1.86 ns at V CM = 0.1 V, whereas it is 1.24 ns at V CM = 3.3 V. Figure 13 shows the post-layout-simulated PSD of the proposed SAR ADC. The simulated SNDR is about 65.88 dB and the ENOB is roughly 10.65 bits at input frequency of 110 kHz. The simulated resolution satisfies the specification of SAR ADC for use in BLDC motor drive. The simulation also presents that the DNL is +0.062/−0.501 dB, INL is +0.936/−0.081 dB, power consumption is 833 µW, and chip area is roughly 1.35 × 0.98 mm 2 at TT corner. The proposed SAR ADC operates without missing code because the maximum DNL is less than 1 LSB. Table 4 summarizes the post-layout-simulated results of the proposed SAR ADC with three design corners. The SNDR and ENOB perform uniformly. The simulated performance of the proposed SAR ADC satisfies the required specification without missing code. Figure 14 shows the chip microphotograph of the proposed SAR ADC. A separation technique is considered to divide the large capacitor into two small capacitors and put them in common centroid. The small capacitor is put in the center of a circle, while the large capacitor is aligned outside the circle. Those parasitic impedance and capacitance can be reduced with symmetric layout. Furthermore, the temperature variation does not affect the resolution of the proposed SAR ADC from −40 • C to 100 • C. The simulated results satisfy the required specification of the proposed SAR ADC. pulled up to VDD by passing through inverters. As the differential input voltage ∆Vin of 1.0 mV, the discharge rate are different at nodes, NN, NP, PN', and PP'. Thus the differential output voltages, VOUTP and VOUTN, were connected to VDD (3.3 V) and ground (0 V), respectively, by passing through the latch stage with cross-connected inverter and positive feedback. Figure 12 shows the simulation waveforms of the proposed comparator with VCM = 3.3 V and ∆Vin = 1.0 mV. Note that the delay time is appropriately 1.86 ns at VCM = 0.1 V, whereas it is 1.24 ns at VCM = 3.3 V.  Figure 13 shows the post-layout-simulated PSD of the proposed SAR ADC. The simulated SNDR is about 65.88 dB and the ENOB is roughly 10.65 bits at input frequency of 110 kHz. The simulated resolution satisfies the specification of SAR ADC for use in BLDC motor drive. The simulation also presents that the DNL is +0.062/−0.501 dB, INL is +0.936/−0.081 dB, power consumption is 833 µW, and chip area is roughly 1.35 × 0.98 mm 2 at TT corner. The proposed SAR ADC operates without missing code because the maximum DNL is less than 1 LSB. Table 4 summarizes the post-layout-simulated results of the proposed SAR ADC with three design corners. The SNDR and ENOB perform uniformly. The simulated performance of the proposed SAR ADC satisfies the required specification without missing code. Figure 14 shows the chip microphotograph of the proposed SAR ADC. A separation technique is considered to divide the large capacitor into two small capacitors and put them in common centroid. The small capacitor is put in the center of a circle, while the large capacitor is aligned outside the circle. Those parasitic impedance and capacitance can be reduced with symmetric layout. Furthermore, the temperature variation does not affect the resolution of the proposed SAR ADC from −40 °C to 100 °C. The simulated results satisfy the required specification of the proposed SAR ADC. . Figure 13. Post-layout-simulated PSD of the proposed SAR ADC.          Figure 16 presents the measured 32,768-point PSD of the proposed SAR ADC with two sampling modes and an 8-channel switch at an input frequency of 110 kHz, a sampling frequency of 0.909 MS/s, and a power supply of 3.3 V. When a full-scale input sine wave was considered at the frequency of 110 kHz, the proposed SAR ADC yielded an SNDR of 50.56 dB, which was approximately 8.11 bits; this was achieved by setting two bias voltages, V bias_N and V bias_P , to 0.8 V, and 2.5 V, respectively. The measured resolution of 8.11 bits satisfies the specification of SAR ADC in BLDC motor drive because the PWM register contains an 8-bit channel. The DNL and INL are demonstrated in Figures 17 and 18, respectively. The measured DNL varies from +0.99 LSB to −0.625 LSB and the measured INL changes from +1.28 LSB to −0.173 LSB. The proposed SAR ADC operates without missing code even though the measured INL is larger than 1.0 LSB. Note that the DNL/INL spurs are enlarged around code 50 and code 400 in Figures 17 and 18, those negative impacts affect the measured results significantly.         Figure 19 shows the measured ENOBs with respect to input frequency at the sampling frequency of 0.909 MS/s. The measured ENOBs perform uniformly from 10 kHz to 110 kHz and the maximum SNDR occurs at 110 kHz. Note that the post-layout-simulated SNDR of 65.88 dB can be compared with the measured SNDR of 50.56 dB; the main difference was generated from the complementary-input double-tail latch-type voltage comparator. The sampled-and-held voltage V S/H was seriously affected by clock feedthrough phenomenon from N-type and P-type input stages. This impact caused the discrepancy between the measured and simulated SNDRs. Figure 20 shows the clock feed-through paths from N-type and P-type input stages at reset mode (CLK = 1 at N-type input stage). Besides, the second-order effects such as channel-length modulation and mismatch effects inside the S/H circuit need to be addressed in the future study [2].
Electronics 2021, 10, x FOR PEER REVIEW 15 of 19 Figure 19 shows the measured ENOBs with respect to input frequency at the sampling frequency of 0.909 MS/s. The measured ENOBs perform uniformly from 10 kHz to 110 kHz and the maximum SNDR occurs at 110 kHz. Note that the post-layout-simulated SNDR of 65.88 dB can be compared with the measured SNDR of 50.56 dB; the main difference was generated from the complementary-input double-tail latch-type voltage comparator. The sampled-and-held voltage VS/H was seriously affected by clock feedthrough phenomenon from N-type and P-type input stages. This impact caused the discrepancy between the measured and simulated SNDRs. Figure 20 shows the clock feed-through paths from N-type and P-type input stages at reset mode (CLK = 1 at N-type input stage). Besides, the second-order effects such as channel-length modulation and mismatch effects inside the S/H circuit need to be addressed in the future study [2].  thermal noise. Therefore, the post-layout simulation performs with a high post-layout ENOB of 10.65 bits, whereas a low ENOB of 8.11 bits was measured in our implemented chip. The FoM is defined as follows [17 Figure 20. Clock feedthrough paths from N-type and P-type input stages at reset mode (CLK = 1 at N-type input stage).

Conclusions
In this paper, we proposed a 10-bit 0.909-MHz 8-channel dual-mode SAR ADC for BLDC motor drive. The proposed sample and hold circuit is made of a sampling capacitor and a simple NMOSFET driven by the boosted driver to achieve both low power and wide bandwidth. A dynamic latch-type comparator is utilized to latch the output at upper or lower level. The advantage of the designed comparator is that it performs with positive feedback to quickly complete the latch function. The double-tail latch-type architecture is utilized to mitigate the significant kickback effect by separating the pre-amplifier stage All the characteristics of the proposed 10-bit 0.909-MHz 8-channel dual-mode SAR ADC for BLDC motor drive are successfully verified. Table 5 summarizes the simulated and measured properties of the proposed SAR ADC developed herein and compares it with other SAR ADCs. The performance comparison proved that the measured ENOB of this study is superior to those of References [12,16,17,23], and the power consumption of this chip is lower than those of SAR ADCs [13][14][15]17,19,22]. Furthermore, the simulated FoM of 0.57 pJ/conv.-step of this study is superior to those of 1.26 pJ/conv.-step in [15] and 175.5 pJ/conv.-step in [19], and the measured FoM of 3.316 pJ/conv.-step of this study is superior to those of 17.3 pJ/conv.-step in [18] and 30.9 pJ/conv.-step in [23]. Unfortunately, the measured FoM of this study is inferior to those of SAR ADCs [12][13][14][15][16][17][20][21][22]. The fabricated chip of this study suffers from clock feedthrough error, process variation, and thermal noise. Therefore, the post-layout simulation performs with a high post-layout ENOB of 10.65 bits, whereas a low ENOB of 8.11 bits was measured in our implemented chip. The FoM is defined as follows [17],

Conclusions
In this paper, we proposed a 10-bit 0.909-MHz 8-channel dual-mode SAR ADC for BLDC motor drive. The proposed sample and hold circuit is made of a sampling capacitor and a simple NMOSFET driven by the boosted driver to achieve both low power and wide bandwidth. A dynamic latch-type comparator is utilized to latch the output at upper or lower level. The advantage of the designed comparator is that it performs with positive feedback to quickly complete the latch function. The double-tail latch-type architecture is utilized to mitigate the significant kickback effect by separating the pre-amplifier stage from the latch. By integrating an input NMOSFET with an input PMOSFET, the designed latch-type comparator can perform with full-swing input voltage. By integrating the eightway switch control system, sample and hold circuit, digital-to-analog converter, latch-type voltage comparator, and successive approximation register (SAR) into a whole chip of SAR ADC, the post-layout simulation proved that the SNR was 65.88 dB and the ENOB was 10.65 bits at an input frequency of 110 kHz and a sampling rate of 0.909 MHz. The main advantages of the proposed multichannel dual-mode SAR ADC are its low power consumption of 833 µW and high measured resolution of 8.11 bits. Unfortunately, the measured FoM of the proposed SAR ADC is inferior to those of other SAR ADCs, which are mostly fabricated in advanced process. Due to industrial requirements, this study was limited to design in TSMC 0.25 µm 1P3M CMOS process. Integrating SAR ADC with those control circuits, as shown in Figure 1, is a novelty and a contribution to the future projects, especially for the speed controller with microcontroller unit (MCU) [24,25].