Nonvolatile Analog Switch for Low-Voltage Applications

: In this paper, a nonvolatile switch based on n-type ﬂoating-gate transistors is described. The switch states are programmed through the memory cell ﬂoating-gate voltage, allowing higher levels than the application supply. Furthermore, due to its nonvolatile nature, the power consumption is reduced. The on-state resistance, which does not depend on the supply voltage, is one of the greatest advantages of this type of switch in comparison to conventional switches. This beneﬁt can be successfully exploited in low-voltage applications. The switch on-resistance can be increased without the need for increasing the switch area. The characteristics of the proposed switch were conﬁrmed by the experimental results obtained on a test chip fabricated in a 0.18 µ m EEPROM process. Measured on-resistance values between 45 and 70 Ω were obtained for a ﬂoating-gate voltage of 6.2 V and input source levels below 2 V. The required programming voltage was 18 V. The maximum off-state leakage current was measured at 5 nA.


Introduction
Designing circuits that operate at low voltages is becoming a stringent requirement, as the number of portable electronic devices is continuously growing. This demand is also encouraged by process down scaling [1,2].
An analog switch can be implemented as an nMOS transistor, a pMOS transistor, or as a parallel combination of these two (CMOS switch or transfer gate). However, the most frequently used is the nMOS switch. A very important parameter of this switch is the on-resistance. Its value depends on technology, transistor aspect ratio, and overdrive voltage [14].
The nMOS switch gate voltage is limited to the supply voltage, and this causes strong degradation of its performances when used in low-voltage applications. The low-voltage handling solution is to increase the transistor gate voltage. Actual methods of this employ the boosting and bootstrapping techniques [9][10][11][12]15]. The boosting method involves the use of a charge pump to raise the gate voltage to a value proportional to the supply [9,15]. In the bootstrapping method, the voltage at the switch transistor gate is capacitively enhanced above the supply voltage so that it equals the sum of the input voltage and the supply voltage [10][11][12]. In both cases, the value of the gate voltage is dependent on the supply voltage.
In this paper, a method to increase the switching device gate voltage to a value independent of the system supply is developed. A floating-gate transistor (FGMOS) [16][17][18] is proposed as the switch. The on-resistance of the switch can be controlled through the floating-gate voltage, programmed using a memory cell. Thus, a nonvolatile switch is obtained, which implicitly has isolated terminals when programming. Furthermore, its floating gate does not draw current after it is programmed, reducing the switch's overall power consumption.
These nonvolatile switches are suitable for digital potentiometers supplied at voltages less than 2 V. In this situation, it is difficult to ensure both small on-resistance and a reasonable area with conventional switches. In addition, common requirements of digitally programmable potentiometers are the memorizing of the last wiper position and being able to restore it when powered up. Under these conditions, a conventional switch-based potentiometer would demand a dedicated memory block, while the proposed solution would not need it anymore. This configuration was implemented in a 0.18 µm EEPROM process using n-type floating-gate transistors. Its functionality was experimentally proven in this paper. The measurements confirm the nonvolatile switch simulations previously presented in [19].

Proposed Nonvolatile Switch Description
The proposed nonvolatile switch has the schematic presented in Figure 1. The switching device (NSW) is built in a deep n-well connected to terminal D_SW. The memory cell is formed by NL and NR transistors, both placed in a separate deep n-well. Thus, the isolation of the transistors from the p-substrate of the wafer is achieved. Furthermore, the bulks can be connected to the sources and biased with different voltages. Since the bulk-to-source voltage of the switching transistor (NSW) is zero, its on-state resistance is not affected by the body effect.
floating-gate voltage, programmed using a memory cell. Thus, a nonvolatile switch is obtained, which implicitly has isolated terminals when programming. Furthermore, its floating gate does not draw current after it is programmed, reducing the switch's overall power consumption.
These nonvolatile switches are suitable for digital potentiometers supplied at voltages less than 2 V. In this situation, it is difficult to ensure both small on-resistance and a reasonable area with conventional switches. In addition, common requirements of digitally programmable potentiometers are the memorizing of the last wiper position and being able to restore it when powered up. Under these conditions, a conventional switchbased potentiometer would demand a dedicated memory block, while the proposed solution would not need it anymore. This configuration was implemented in a 0.18 µm EEPROM process using n-type floating-gate transistors. Its functionality was experimentally proven in this paper. The measurements confirm the nonvolatile switch simulations previously presented in [19].

Proposed Nonvolatile Switch Description
The proposed nonvolatile switch has the schematic presented in Figure 1. The switching device (NSW) is built in a deep n-well connected to terminal D_SW. The memory cell is formed by NL and NR transistors, both placed in a separate deep n-well. Thus, the isolation of the transistors from the p-substrate of the wafer is achieved. Furthermore, the bulks can be connected to the sources and biased with different voltages. Since the bulkto-source voltage of the switching transistor (NSW) is zero, its on-state resistance is not affected by the body effect.
All devices in the proposed schematic ( Figure 1) are high-voltage n-type FGMOS transistors.
Floating-gate transistors are MOS transistors that have two polysilicon gates (a control and a floating gate). Because the floating gate is surrounded by dielectric oxides, it is completely isolated from the rest of the device and can store charges [16][17][18].
NR and NSW transistors share a common floating gate (FGR), which enables the switch transistor programming to be performed by the NR transistor. The purpose of the NL transistor is to provide a means for differentially reading the memory cell [20,21].
NSW transistor channel conductivity is controlled only by the floating gate potential, as the control gate is grounded ( Figure 1).  [19]. NL and NR are the memory cell transistors with SL, DL, SR and DR their corresponding source and drain terminals. NSW is the switch transistor and S_SW its source and D_SW its drain terminals, sharing its floating gate FGR with NR.
In order to remove the electrons from the FGR (Figure 2a), a positive high-voltage programming pulse (+VPP) is applied to the NR transistor source (SR), while its control gate (SL) is kept to ground. In this way, the FGR potential becomes positive, causing the  [19]. NL and NR are the memory cell transistors with SL, DL, SR and DR their corresponding source and drain terminals. NSW is the switch transistor and S_SW its source and D_SW its drain terminals, sharing its floating gate FGR with NR.
All devices in the proposed schematic ( Figure 1) are high-voltage n-type FGMOS transistors.
Floating-gate transistors are MOS transistors that have two polysilicon gates (a control and a floating gate). Because the floating gate is surrounded by dielectric oxides, it is completely isolated from the rest of the device and can store charges [16][17][18].
NR and NSW transistors share a common floating gate (FGR), which enables the switch transistor programming to be performed by the NR transistor. The purpose of the NL transistor is to provide a means for differentially reading the memory cell [20,21].
NSW transistor channel conductivity is controlled only by the floating gate potential, as the control gate is grounded (Figure 1).
In order to remove the electrons from the FGR (Figure 2a), a positive high-voltage programming pulse (+VPP) is applied to the NR transistor source (SR), while its control gate (SL) is kept to ground. In this way, the FGR potential becomes positive, causing the Electronics 2021, 10, 736 3 of 10 switch transistor to turn on and allow the current to flow between its drain and source. This is called the on-programming procedure. This is called the on-programming procedure.
To charge the floating gate with electrons (Figure 2b), the positive high-programming voltage is now applied on the NR transistor control gate (SL), while its source (SR) is kept to ground (0V, GND). By negatively charging the FGR, NSW becomes nonconductive (turned off). This is called the off-programming procedure.
Both on-and off-programming are ensured through Fowler-Nordheim tunneling, a mechanism that involves the tunneling of electrons through a surface barrier due to the application of an intense external electric field across a thin oxide [17].
In both cases, the NL and NR drains are left floating, and their deep n-well (DNW) is biased with +VPP in order to ensure that parasitic diodes are kept reverse biased [19].  Table 1 summarizes both the on-and off-programming conditions. The value of the FGR voltage depends on the value of the voltage programming pulse (VPP) and not on the system supply voltage, as is the case for conventional switches or switches where boosting [9,15] and bootstrapping [10,11,12] methods are used.
In order to activate the tunneling of the electrons and to control the floating gate of the switch, a minimum value for VPP is required, usually greater than 10 V [22]. Thus, when the switch is embedded within a low-voltage system a charge pump is needed for VPP generation [23]. Ultimately, the charge pump is the one that establishes the minimum supply voltage requirements. It is also responsible for the power consumption of the switch, but this happens only during the programming procedure. Once programmed in a particular state, the nonvolatile switch does not consume power (zero quiescent current).

Experimental Results and Discussion
The described switch configuration ( Figure 1) was included in a test chip produced in a 0.18 µm EEPROM process. Figure 3 presents a small portion of the test chip layout. Within this test chip, the switch occupied a total area of about 2400 µm 2 . To charge the floating gate with electrons (Figure 2b), the positive high-programming voltage is now applied on the NR transistor control gate (SL), while its source (SR) is kept to ground (0V, GND). By negatively charging the FGR, NSW becomes nonconductive (turned off). This is called the off-programming procedure.
Both on-and off-programming are ensured through Fowler-Nordheim tunneling, a mechanism that involves the tunneling of electrons through a surface barrier due to the application of an intense external electric field across a thin oxide [17].
In both cases, the NL and NR drains are left floating, and their deep n-well (DNW) is biased with +VPP in order to ensure that parasitic diodes are kept reverse biased [19]. Table 1 summarizes both the on-and off-programming conditions. The value of the FGR voltage depends on the value of the voltage programming pulse (VPP) and not on the system supply voltage, as is the case for conventional switches or switches where boosting [9,15] and bootstrapping [10][11][12] methods are used.
In order to activate the tunneling of the electrons and to control the floating gate of the switch, a minimum value for VPP is required, usually greater than 10 V [22]. Thus, when the switch is embedded within a low-voltage system a charge pump is needed for VPP generation [23]. Ultimately, the charge pump is the one that establishes the minimum supply voltage requirements. It is also responsible for the power consumption of the switch, but this happens only during the programming procedure. Once programmed in a particular state, the nonvolatile switch does not consume power (zero quiescent current).

Experimental Results and Discussion
The described switch configuration (Figure 1) was included in a test chip produced in a 0.18 µm EEPROM process. Figure 3 presents a small portion of the test chip layout. Within this test chip, the switch occupied a total area of about 2400 µm 2 . ics 2021, 10, x FOR PEER REVIEW 4 of 11 Figure 3. Test chip layout with included nonvolatile switch structure and associated pads. Figure 4 illustrates the measurement setup used for testing the functionality of the nonvolatile switch on the wafer. It included a micromanipulator for placing the four available needle probes onto the desired pads, a semiconductor parameter analyzer (HP4145B) responsible for biasing and measurements, and a PC for data processing. Two configurations ( Figure 4A,B) were employed during the measurements. In configuration A, the four needle probes were connected on the SL, SR, DNW, and GND pads to enable the programming procedure. In configuration B, three needle probes were connected on the S_SW, D_SW, and GND pads in order to determine the effects of programming on the switch state. The measurement method followed the steps indicated in the diagram shown in Figure 5.  Figure 4 illustrates the measurement setup used for testing the functionality of the nonvolatile switch on the wafer. It included a micromanipulator for placing the four available needle probes onto the desired pads, a semiconductor parameter analyzer (HP4145B) responsible for biasing and measurements, and a PC for data processing.   Figure 4 illustrates the measurement setup used for testing the functionality of the nonvolatile switch on the wafer. It included a micromanipulator for placing the four available needle probes onto the desired pads, a semiconductor parameter analyzer (HP4145B) responsible for biasing and measurements, and a PC for data processing. Two configurations ( Figure 4A,B) were employed during the measurements. In configuration A, the four needle probes were connected on the SL, SR, DNW, and GND pads to enable the programming procedure. In configuration B, three needle probes were connected on the S_SW, D_SW, and GND pads in order to determine the effects of programming on the switch state. The measurement method followed the steps indicated in the diagram shown in Figure 5. Two configurations ( Figure 4A,B) were employed during the measurements. In configuration A, the four needle probes were connected on the SL, SR, DNW, and GND pads to enable the programming procedure. In configuration B, three needle probes were connected on the S_SW, D_SW, and GND pads in order to determine the effects of programming on the switch state. The measurement method followed the steps indicated in the diagram shown in Figure 5. First, the inherent state of the nonvolatile switch was determined to be off by measuring a current in the order of nA through the NSW transistor.
Then, in order to program the nonvolatile switch in the on state, a step voltage varying from 0 V to a variable high voltage level (VPP between 16 and 20 V) was set for the SL pad. The same VPP was applied to the DNW pad, while SR was grounded. For each case, the responsiveness of the FGR potential was assessed using the setup in Figure 6. The VS_SW source was varied between 0 and 7 V, while VD_SW was kept constant at 7 V.  First, the inherent state of the nonvolatile switch was determined to be off by measuring a current in the order of nA through the NSW transistor.
Then, in order to program the nonvolatile switch in the on state, a step voltage varying from 0 V to a variable high voltage level (VPP between 16 and 20 V) was set for the SL pad. The same VPP was applied to the DNW pad, while SR was grounded. For each case, the responsiveness of the FGR potential was assessed using the setup in Figure 6. The V S_SW source was varied between 0 and 7 V, while V D_SW was kept constant at 7 V. First, the inherent state of the nonvolatile switch was determined to be off by measuring a current in the order of nA through the NSW transistor.
Then, in order to program the nonvolatile switch in the on state, a step voltage varying from 0 V to a variable high voltage level (VPP between 16 and 20 V) was set for the SL pad. The same VPP was applied to the DNW pad, while SR was grounded. For each case, the responsiveness of the FGR potential was assessed using the setup in Figure 6. The VS_SW source was varied between 0 and 7 V, while VD_SW was kept constant at 7 V.    Figure 7 depicts the NSW drain current variation with the voltage applied on its source (S_SW) for different VPPs. Note that the maximum switch current value was limited to 10 µA, since the aim of this measurement was only to identify how the programming voltage influences the floating-gate potential. NSW behaves like a standard nMOS transistor, having its gate biased with the floating-gate potential. As VS_SW rises the overdrive voltage of NSW decreases until its channel is cut off (and the drain current sharply decreases to zero).
The increase in VPP causes the floating-gate potential to increase, so the cut off occurs at a higher VS_SW. Even though there is the same 1 V difference between the VPP values corresponding to each two consecutive curves, we can observe from Figure 7 that the tunneling effect starts to saturate with the VPP increase. Thus, there is a limit value for the VPP voltage from which the transistor channel conductivity cannot be further increased.
In order to measure the on-state resistance of the nonvolatile switch, a constant current (I) was sourced into the drain of the NSW transistor, while its source was connected to a variable voltage source from 0 to 7 V. Figure 8 illustrates the switch on-resistance test setup. The on-state resistance measurement was made after the switch was programmed using VPP = 18 V. NSW behaves like a standard nMOS transistor, having its gate biased with the floatinggate potential. As V S_SW rises the overdrive voltage of NSW decreases until its channel is cut off (and the drain current sharply decreases to zero).
The increase in VPP causes the floating-gate potential to increase, so the cut off occurs at a higher V S_SW . Even though there is the same 1 V difference between the VPP values corresponding to each two consecutive curves, we can observe from Figure 7 that the tunneling effect starts to saturate with the VPP increase. Thus, there is a limit value for the VPP voltage from which the transistor channel conductivity cannot be further increased.
In order to measure the on-state resistance of the nonvolatile switch, a constant current (I) was sourced into the drain of the NSW transistor, while its source was connected to a variable voltage source from 0 to 7 V. Figure 8 illustrates the switch on-resistance test setup. The on-state resistance measurement was made after the switch was programmed using VPP = 18 V. In this configuration, the drain voltage was measured, and the on-resistance was determined using the following equation: Different values were used for the current I, but for small currents, we observed that In this configuration, the drain voltage was measured, and the on-resistance was determined using the following equation: Different values were used for the current I, but for small currents, we observed that measurements were strongly affected by the precision of the HP4145B semiconductor parameter analyzer. Thus, in order to minimize the errors introduced by this instrument, a value of 1 mA was chosen for the current sourced to the drain, also taking into consideration a safe power dissipation.
Unfortunately, because of the small-sized pads in the test chip, the four-point resistance measurement method could not be employed, so the measured resistance value was subject to both contact and wire resistance influence.
The on-resistance of the switch varies with the overdrive voltage variation. Because the sourced current through the drain is constant, the R ON variation also causes the drain voltage to change. For V DS_SW values below 0.1 V, the R ON is situated between 45 and 100 Ω, as shown in Figure 9. As expected, the relationship between the on-resistance and the switch drain-to-source voltage is linear. In this configuration, the drain voltage was measured, and the on-resistance was determined using the following equation: Different values were used for the current I, but for small currents, we observed that measurements were strongly affected by the precision of the HP4145B semiconductor parameter analyzer. Thus, in order to minimize the errors introduced by this instrument, a value of 1 mA was chosen for the current sourced to the drain, also taking into consideration a safe power dissipation.
Unfortunately, because of the small-sized pads in the test chip, the four-point resistance measurement method could not be employed, so the measured resistance value was subject to both contact and wire resistance influence.
The on-resistance of the switch varies with the overdrive voltage variation. Because the sourced current through the drain is constant, the RON variation also causes the drain voltage to change. For VDS_SW values below 0.1 V, the RON is situated between 45 and 100 Ω, as shown in Figure 9. As expected, the relationship between the on-resistance and the switch drain-to-source voltage is linear. Figure 9. On-resistance measured variation for drain-to-source voltages smaller than 0.1 V. Figure 9. On-resistance measured variation for drain-to-source voltages smaller than 0.1 V. Figure 10 shows NSW on-resistance variation with V S_SW . At high overdrive voltages, the on-resistance has low values, varying from 45 to 70 Ω for V S_SW under 2 V (see inset of Figure 10). This small variation makes this switch ideal for low-voltage applications. A "knee" shape can be observed in Figure 10 when V S_SW is around 3 V. This effect was observed on all measured structures. After the source voltage reaches 5 V, the onresistance abruptly increases in response to the fact that the transistor starts to turn off (V FGR − V S_SW ≤ V T ). Figure 10). This small variation makes this switch ideal for low-voltage applications. A "knee" shape can be observed in Figure 10 when VS_SW is around 3 V. This effect was observed on all measured structures. After the source voltage reaches 5 V, the on-resistance abruptly increases in response to the fact that the transistor starts to turn off (VFGR − VS_SW ≤ VT). Simulations were also performed on the nonvolatile switch considering multiple values for the floating-gate voltage in order to estimate the real FGR value at VPP = 18 V. The simulated results are plotted in Figure 11, together with the measured characteristics presented in Figure 10. Matching was sought in the portion of the curves where RON exhibited an abrupt increase, corresponding to the transition between on and off states. Thus, the real value for the FGR potential was estimated at around 6.2 V. The measured on-resistance variation is larger than its simulated counterpart for a VS_SW lower than 5 V. Simulations were also performed on the nonvolatile switch considering multiple values for the floating-gate voltage in order to estimate the real FGR value at VPP = 18 V. The simulated results are plotted in Figure 11, together with the measured characteristics presented in Figure 10. Matching was sought in the portion of the curves where R ON exhibited an abrupt increase, corresponding to the transition between on and off states. Thus, the real value for the FGR potential was estimated at around 6.2 V. The measured on-resistance variation is larger than its simulated counterpart for a V S_SW lower than 5 V. served on all measured structures. After the source voltage reaches 5 V, the on-resistance abruptly increases in response to the fact that the transistor starts to turn off (VFGR − VS_SW ≤ VT). Simulations were also performed on the nonvolatile switch considering multiple values for the floating-gate voltage in order to estimate the real FGR value at VPP = 18 V. The simulated results are plotted in Figure 11, together with the measured characteristics presented in Figure 10. Matching was sought in the portion of the curves where RON exhibited an abrupt increase, corresponding to the transition between on and off states. Thus, the real value for the FGR potential was estimated at around 6.2 V. The measured on-resistance variation is larger than its simulated counterpart for a VS_SW lower than 5 V. For instance, in a 4 V application, the proposed nonvolatile switch has a maximum on-resistance of 300 Ω regardless of input voltage (Figures 10 and 11). An identically sized conventional nMOS, however, has an R ON in excess of 1 kΩ once the input voltage exceeds 2.7 V. Therefore, for the same on-resistance performances, the area consumed by the nonvolatile switches is lower if the floating-gate voltage is larger than the gate command of the conventional switches. Moreover, the proposed switch performances may be improved through the programming tunneling voltage without increasing the required area, unless the programming limit mentioned before is reached.
However, the EEPROM technology required by the nonvolatile switch needs additional process steps compared to CMOS processes, where conventional switches are usually built in. Therefore, a final estimation about the cost depends on both the switch area and the technology expenses.
NSW was switched off by programming. Thus, a voltage step of 0 to 18 V was applied to the SL pad. SR was grounded while the DNW pad was connected to 18 V. The current measured through NSW after applying this programming sequence on NR was of max. 5 nA, confirming the switch's off state.
The functionality for the nonvolatile switch was also proven by simulations for both on and off states [19].
Additionally, simulations were also carried out in order to determine the bandwidth of the NSW transistor. A 10 mV AC generator was applied to the source, while its drain was connected to a load impedance consisting of a 50 Ω resistor in parallel with a 5 pF capacitor. The cut-off frequency was determined to be around 4 GHz.

Conclusions
In this paper, a nonvolatile switch for low-voltage applications was proposed, comprising common FGMOS transistors, used as the effective switch and a memory cell, respectively. The switch states are programmed through the memory cell floating-gate voltage. Thus, the FGR level can be higher than the application supply in order to optimize the on-resistance of the switch. Furthermore, due to its nonvolatile nature, the power consumption is reduced.
The switch performance was proven by experimental measurements made on a test chip fabricated in a 0.18 µm EEPROM process.
The measured on-state resistance had a small variation (from 45 to 70 Ω) for a floatinggate voltage of 6.2 V and input source levels below 2 V. It remained reasonably small (<300 Ω) until input voltages of 4.3 V. Moreover, there was no need for increasing the switch area in order to obtain smaller on-resistances. The FGR value was obtained using a programming of 18 V, representing a significant amount in low-voltage systems, where the conventional nMOS transistor gate potential is limited by the power supply.
In the off state, the maximum leakage current was measured at 5 nA. The small on-resistance variation, reduced power consumption, and nonvolatility indicate the potential of the proposed switch for low-voltage potentiometer applications such as hearing aids.