Floating Body DRAM with Body Raised and Source/Drain Separation

: One-Transistor (1T) DRAMs are one of the potential replacements for conventional 1T-1C dynamic memory cells for future scaling of embedded and stand-alone memory architectures. In this work, a scaled (channel length 10nm) ﬂoating body 1T memory device architecture with ultra-thin body is studied, which uses a combined approach of a body raised storage region and separated source/drain regions having the role to reduce thermal and ﬁeld enhanced band-to-band recombination. The physical mechanisms along the geometry and bias scaling are discussed in order to address the requirements of embedded or stand-alone applications. Two-dimensional device simulations show that, with proper optimization of the geometry and bias, the combined approach allows the increase of the retention time and of the programming window by more than one order of magnitude.


Introduction
From the early demonstration in 2001 [1], one-Transistor DRAMs (1T-DRAMs) have been largely investigated as a candidate to replace the conventional one transistor-one capacitor (1T-1C) cell. Differently from the 1T-1C architecture, a 1T-DRAM cell is composed of a single device, a Silicon On Insulator MOSFET, which acts with both the roles of access and memory device, leading to superior scaling perspectives with respect to the 1T-1C cell. A different number of 1T-DRAM approaches have been recently reported in the literature [2][3][4][5][6][7]. In Floating Body 1T-DRAMs (FB-DRAMs) [8][9][10][11][12][13][14][15], the information is encoded as non-equilibrium excess charge (typically holes) stored in the bulk of a Silicon On Insulator MOSFET. The advantage of FB-DRAMs with respect to other 1T-DRAM architectures is the higher compatibility with the standard Silicon technology, especially in the cases of embedded systems or systems on chip. In FB-DRAMs, the excess charge is generated by non-equilibrium phenomena like Impaction Ionization (II) and/or Band to Band tunneling (BBT) during the WRITE operation. Due to the body effect, the excess holes stored in the body reduces the threshold voltage, so that a higher channel current is measured during the READ operation. However, the excess charge degrades with time. The retention time of the excess charge is limited by the SRH recombination, during the HOLD operation, in the region where the excess charge is stored. In particular the SRH recombination rate increases with the product of the electron-hole concentrations (np) and reduces with the increase of the recombination lifetime τ. Several new devices, with different materials and/or different architectures, have been proposed to increase the retention time [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. In this work we focus on the architectural approach, maintaining the Silicon as the active material. The product np has been reduced by separating the regions where electrons and holes are stored during HOLD operation [12][13][14]. For example, in [13] a body raised region is used to accommodate the excess holes, separating them from the channel electrons. From the other side the lifetime τ has been increased with a low doping in the region where excess charge is stored. In fact, a lower doping increases τ due to a lower band-to-band defect-assisted thermal and field enhanced recombination. A lower doping can be obtained also by separating the high-doped source and drain regions from a low doped channel [15] or using a dopingless channel with Schottky contacts [13]. Another advantage of low doping is a strongly reduced variability induced by random dopant fluctuations. In this work it is proposed a FB-DRAM architecture which uses both concepts of a body raised region and source/drain separation, with particular emphasis on the former, as source/drain separation has been previously discussed by the same author in [15]. It is shown that the combined approach of body raised and source/drain separation can lead to an increase of more than one order of magnitude of the retention time and of the programming window.
The rest of the paper is organized as stated in the following. In Section 2 the proposed device structure is presented, and the details of the simulation model are given. In Section 3 the operation mode during WRITE, ERASE, HOLD and READ operation is discussed with reference to a scaled device geometry with L = 10 nm. In particular, it is discussed how the presence of the body raised region improve the charge holding capability of the memory cell. In Section 4, it is discussed the scaling of the proposed architecture, starting from the scaled geometry discussed in Section 2 (except for the body raised region scaling, which is discussed in Section 3). As geometry scaling has an impact on the necessary bias levels required to obtain given values of retention time and programming window, the optimization of the geometry/bias trade-off is discussed in Section 5. This can serve as a guideline in order to address the requirements of embedded or stand-alone applications. Finally, in Section 6, the summary and conclusions are drawn. Figure 1 shows a simplified structure of the 1T memory cell under investigation. Source and Drain heavy doped regions (10 20 cm −3 ) are separated from the low doped (10 15 cm −3 ) channel (L = 10 nm) by a spacer region (length L SP ) necessary to relax the field in the channel in order to reduce BBT and Trap-Assisted-Tunneling (TAT) to improve the retention time [15]. A raised body region (height WR) is used to accommodate the excess charge during HOLD operation and to relax the field, allowing larger retention time as discussed in the next sections. Technological details about the body raised region can be found in [13]. The equivalent oxide thickness (EOT) is 1 nm, and the Gate workfunction is 4.5 eV (a different workfunction can be immediately considered if the gate voltage is correspondently shifted). Two-dimensional (2D) Atlas device simulation [16] (T = 300 K) are used to investigate the behavior of the proposed architecture. The simulation model includes the drift-diffusion transport model with Fermi-Dirac statistics, concentration-dependent mobility, concentration-dependent lifetime (Scharfetter), SRH generation/recombination and impact ionization (II) (Selberherr). The Hurkx TAT [17] and the non-local BBT models are included in the simulation model with default parameters to reproduce the charge degradation mechanisms in 1T-DRAMs, the first acting for both generation and recombination, the second for generation. However, as will be clear in the next sections, due to large source/drain separation and body raised region height, BBT and TAT are completely turned off in the proposed architecture allowing a larger retention time.

Device Structure and Simulation Model
No quantization models are included along the transversal direction due to the large W. In fact, as showed in [18], no significant bandgap widening is present with W = 10 nm and, as discussed in [8], no significant effects on the programming window of FB-DRAMs are observed at this large W.

Device Operation
In this section WRITE, ERASE, READ and HOLD operations are discussed with reference to a scaled device geometry with L = L SP = 10 nm and WR = 20 nm. Moreover, the scaling and influence of the body raised region height (WR) are discussed. In Section 4, the scaling of other geometrical/technological parameters are discussed.

WRITE and ERASE Operations
The excess charge is created, during the WRITE operation, via Impact Ionization (II) induced by a sufficient high V D and stored, at the Gate interface, by a sufficient negative V G as discussed in the following. Figure 2 shows a cutline, along the x channel direction (y = 0), of (Top) II and electron/hole BBT generation rates (GR) and (Bottom) conduction and valence bands, at the end of a WRITE operation (pulse width = 5 ns) at the bias V D = −V G = 2 V (the dependence on the pulse strength and width is discussed later). As evident from Figure 2 Top, the overall GR is dominated by II rather than BBT, which is not effective due to the insufficient band-bending at the drain side of the channel and relatively large tunneling distance (Figure 2 Bottom). The low band bending is a consequence of the low doping in the channel region, due to the presence of the spacers, and of the low Gate coupling, due to the presence of the raised region. Impact ionization is mostly localized in the source and drain regions due to the large electric field. The generated excess holes are mainly accumulated at the Gate interface, in the raised region, due to the negative V G during WRITE operation as shown in Figure 3, where a hole concentration cutline along the transversal direction y (x = 0) is shown. Figure 3 shows that the geometry of the raised region (hence its presence) does not affect the charge accumulated during WRITE operation.   Figure 4 shows the transient behavior of the current (left axis) and of the hole concentration (right axis) during WRITE operation. The hole concentration is integrated in the channel and in the body raised regions (−L/2 ≤ x ≤ L/2). Thanks to the very high II-GR (see Figure 2 Top), WRITE operation is very fast so that both the WRITE current and the hole concentration saturate into 1ns (the rise time of the WRITE pulse). Figure 4 shows also the (displacement) current and hole concentration during ERASE operation with V G = V D = 0. As evident, the value of V G = 0 V is sufficiently high in order to quickly increase electron concentration with consequent reduction of excess hole concentration stored in the raised region by SRH recombination [11].  The READ operation immediately follows the WRITE operation (no HOLD operation between) in order to investigate the dependence of the READ after WRITE (RAW) current on the WRITE voltage without the effect of the charge degradation during HOLD operation. The READ current is measured at the end of a pulse width of 5 ns at the bias V G = −2 V, V D = 0.1 V. The hole concentration (red symbols) increases as the WRITE voltage V D = −V G is increased due to the enhanced II-GR (higher V D ) and to the higher storage capability at the Gate interface (more negative V G ). As consequence, the RAW current increases monotonically with the WRITE bias due to the increasing amount of excess charge. In the same figure, the hole concentration after ERASE and the READ after ERASE (RAE) current, which do not depend on the WRITE bias, are reported to show the memory window. As evident, a large memory window can be obtained also at sub 1V WRITE operation.

READ Operation
Because READ operations are invasive, the Gate is biased during READ with a sufficient negative voltage, with the aim of retain part of the residual excess charge generated during WRITE operation. Figure 6 shows the electron/hole concentrations (Top) and the energy bands (Bottom) along a cutline in the transversal direction (y), in the middle of the channel (x = 0), at the end of RAW and RAE operations for a READ pulse width t READ = 5 ns and for a HOLD time t HOLD = 0 (no HOLD operation). Due to the negative Gate bias, the holes generated during WRITE operation (open red symbols in Figure 6 Top) are retained, during RAW operation, in the channel producing an increase, with respect to the case of RAE operation (blue open symbols), of the hole concentration from the Gate interface (maximum increase) to the semiconductor channel region (minimum increase). This increase reflects in energy band lowering (see Figure 6 Bottom) and consequent increase of electron concentration (filled symbols in Figure 6) from the Gate interface (minimum increase) to the channel region (maximum increase). The electron concentration increase reflects in a much higher RAW current with respect to the RAE current (body effect).

HOLD Operation
Between WRITE (ERASE) and READ operation, the device is in HOLD mode with vs. = V D = 0 while the gate voltage is sufficient negative in order to maintain as long as possible the charge generated during WRITE operation. Figure 7 shows cutlines, in the y transversal direction (x = 0), of electron and hole concentrations at the end of HOLD after WRITE (HAW) and HOLD after ERASE (HAE) operations at the bias V G = −2 V and with a HOLD time (t HOLD ) of 100 ms (>64 ms of the ITRS spec.), for different values of the raised region height WR (WR = 20 nm in Figure 7 Top). Figure 7 shows that, during HOLD, holes are mainly accumulated at the Gate interface, due to the negative Gate voltage (−2 V), while electrons are accumulated mainly at the bottom surface (y = W). This physical separation prevents electron-hole recombination and allows excess charge retention during HAW operation. A higher WR allows a larger volume for excess charge storage and increases the separation of the excess holes from electrons, reducing recombination during HAW. On the other hand, the higher WR produces a lower electrostatic integrity. In fact, the higher WR increases the distance between the Gate and the channel resulting in a reduced capacitive coupling and lower source to channel energy barrier (threshold voltage roll-off). In consequence, in the channel (−L/2 ≤ x ≤ L/2, y ≥ 0), the electron concentration increases, and the hole concentration decreases during HAW/HAE operations (Figure 7 Bottom and Figure 8 Top-right axis). The higher electron concentration increases the RAW/RAE currents, as evident from Figure 8 Top-left axis. The higher HAW hole concentration in the channel with respect to HAE case makes the RAW current (I RAW ) higher with respect to the RAE current (I RAE ). The increase of the RAW current with WR produces a larger a programming window PW = I RAW − I RAE . However, the reduced hole concentration during HOLD led to a reduced body effect and lower current ratio CR = I RAW /I RAE. The bottom side of Figure 8 shows the RAW and RAE current with BBT and TAT models turned on (filled symbols) and off (empty symbols) in a geometry with L SP = 2 nm. A smaller spacer is chosen in order to make in evidence the effect of BBT/TAT during HOLD operation. For WR = 5 nm, the charge degradation during HOLD due to BBT/TAT makes the programming window close to zero. However, as WR is increased, the effect of BBT/TAT becomes negligible, and the charge degradation is limited by pure thermal SRH recombination. When the spacer is larger, as for example in Figure 8 Top where L SP = 10 nm, BBT/TAT is already minimized by Source/Drain separation from the channel, and the increase of WR is helpful in increasing the currents, as discussed above. The TAT model used in this work is the well-known Hurkx model (reference [17]), which has only a parameter, the tunneling mass, with a default value of m t = 0.25 × m 0 . In order to investigate the relevance of this parameter, device simulations by varying m t from 0.1 × m 0 to 0.5 × m 0 have been done with reference to the geometry WR = 20 nm. The result is that the RAW current varies between 52.2 µA/µm and 58.1 µA/µm while the RAE current varies between 295 nA/µm and 142 nA/µm. As discussed above, this modest variation is due to the fact the TAT model is turned off by the source/drain separation and by the presence of the body raised region. Similar considerations can be derived for the BBT model. Finally, Figure 9 shows the RAW and RAE currents (filled symbols, left axis) and the integrated hole concentration (empty symbols, right axis) in the channel during HAW and HAE operations as function of the HOLD time. Hole concentration degrades, due to SRH recombination (during HAW) and generation (during HAE), driving the degradation of the RAW and RAE currents. As can be observed, a large memory window (>>6 µA/µm of the ITRS spec.) is obtained at a HOLD time in the order of 10 s.

Geometrical and Technological Scaling
Starting from the basic geometry discussed in the previous section (L = L SP = 10 nm, WR = 20 nm, doping 10 15 cm −3 ), in this Section, the geometrical and technological scaling of the proposed device architecture is studied. In particular, data with the BBT and TAT models turned on and off are shown in order to demonstrate the effectiveness of the proposed architecture along the geometrical and technological scaling. Figure 10a shows the RAW and RAE currents as function of the gate length for two different Gate HOLD biases (V G,HOLD ). As L is increased from L = 10 nm, the currents decrease due to the lower channel field and due to the electrostatic improvement. No significant effects of BBT/TAT must be considered due to the large L SP (=10 nm) and WR (=20 nm) as discussed in the previous sections. When V G,HOLD = −2 V (results reported in the previous section), the RAW current drops strongly with L, and the programming window of the case L = 100 nm is much lower with respect to the case L = 10 nm. However, a more negative V G,HOLD (−2.4 V in Figure 10a) can be used to restore the HOLD capability in the longer channels. In this situation, the RAW current reduction is moderate, and it is only due to the lower field in the longer channels, while the RAE current strongly reduces with L due to electrostatic improvement. The result is that the longer channels have a slightly lower programming window with respect to L = 10 nm but a much higher current ratio. Figure 10a shows that the proposed architecture can be scaled towards 10 nm in the Gate length. This is possible only due to the presence of the raised region as shown in Figure 8.  Figure 10b shows the RAW and RAE currents as function of the spacer length (L SP ) with BBT/TAT models turned on (filled symbols) and off (empty symbols). As L SP increases, the currents reduce due to the higher series resistance. Source/Drain would relax the field with consequent lower BBT/TAT degradation [15]. However, in Figure 10b WR = 20 nm so that even for small spacer lengths, no significant effect of BBT/TAT degradation is observed. Figure 10c shows the RAW and RAE currents as function of the semiconductor doping (the doping of the channel, spacers and body raised regions) with BBT/TAT models turned on (filled symbols) and off (empty symbols). In the previous section, the semiconductor doping is set to 10 15 cm −3 . This corresponds in practice to a low doped or undoped substrate. Figure 10c shows that in a large interval around this value, there is no significant variation of the currents. In fact, at such a low doping level, the low field lifetime is relatively high and the electric field relatively low so that BBT/TAT are irrelevant, and the retention is limited by thermal SRH generation/recombination. As the semiconductor doping is increased above 10 16 cm −3 , the electrostatic degradation produces a rapidly decrease of the currents and, in any case, a negligible impact of BBT/TAT is observed.
Finally, Figure 10d shows the RAW and RAE currents as function of the EOT. As the EOT is increased, the electrostatic degradation makes the current higher. However, during HAW, the applied bias is able to retain the large excess charge generated during WRITE operation so that the RAW current is less sensitive to the EOT increase.

Performance of the Geometry/Bias Trade-Off
Performances of a 1T-DRAM cell depend on both the geometry and bias. In Figure 11, the PW is studied as function of V G , L SP , WR and of the HOLD time t HOLD . In order to simplify the analysis, we set the same V G during READ and HOLD operations (V G = V G,READ = V G,HOLD ) although better performances can be in general obtained with V G,READ = V G,HOLD [11]. As discussed in [11], the more negative is V G , the higher is the HOLD capability and the current ratio, but the lower is the current and the programming window PW. The increase of the spacer length L SP relax the junction field allowing a larger retention time due to the lower TAT recombination. However, the larger series resistance reduces the current and the programming window [15]. Moreover, a larger spacer increases device area. Performances are also a function of the raised region height WR as discussed in the previous section, but differently from the spacer geometry, the raised region height does not affect device area. In particular, the PW increases with WR ( Figure 8-left axis) while the current ratio CR reduces. It appears evident that WR cannot be increased as desired, due to the reduction of the CR. In this discussion (and in Figure 11), we limit the minimum current ratio to a value of CR ≥ 2. Figure 10 Top shows, for a given t HOLD and V G , the minimum spacer length necessary to meet ITRS requirements (PW > 6 µA/µm at t HOLD = 64 ms [13]). For each point in Figure 11 Top, the PW and CR are a function of WR. Figure 10 Bottom shows the maximum of the function PW(WR) and the corresponding value of WR close to each symbol. As the required t HOLD is increased, the minimum spacer (hence the device area) needs to be increased to reduce the junction field and TAT recombination (Figure 11 Top). As can be observed, the PW can be maintained relatively large at large t HOLD by using a sufficient height raised region (Figure 11 Bottom). Stated in other words, the reduction of the PW due to the larger L SP can be compensated with a higher raised region. This approach allows maintaining a relatively high PW also at higher t HOLD . The value of the gate voltage V G is important as well as the geometry. In fact, in embedded or system on chip applications, the bias is often limited by the logic circuitry, while in stand-alone memory chips applications, it can be relaxed in the limits of the maximum allowed power consumption. As can be observed in Figure 11 Top, the minimum L SP , hence the device area, can be reduced if a more negative V G is allowed. In fact, the higher HOLD capability due to the more negative V G compensates the higher TAT degradation due to the lower L SP . Moreover, the more negative can be V G , the higher can be WR, due to the reduced gate coupling, allowing a larger programming window (Figure 11 Bottom). The performance of a DRAM cell can be discussed in terms of the programming window, guaranteeing a retention time of at least 64 ms from the ITRS specification, or in terms of retention time, guaranteeing a programming window of at least 6 µA/µm of the ITRS specification [13]. Following the first point of view, it is evident from Figure 11 that with t HOLD = 100 ms (>64 ms of the ITRS spec.), the PW can reach 100 µA/µm (>>6 µA/µm of the ITRS spec.) with |V G | limited to 1V and L SP = 5 nm, while it can be large up to 1 mA/µm if |V G | can be pushed down to 2 V maintaining a short spacer (2 nm). However, from the other point of view, 10 s of retention time can be obtained with L SP = 10 nm with |V G | limited to 1 V while device area can be reduced with L SP = 4 nm if |V G | can be pushed down to 2 V. Figure 11. (Top) Minimum spacer length in order to meet ITRS requirements as function of t HOLD and V G,READ = V G,HOLD ; (Bottom) the corresponding programming window (close to each symbol the corresponding value of the optimum WR). The observation spaces for L SP and WR are limited to 10 nm and 50 nm, respectively, with 1 nm resolution.

Conclusions
In this work, the physics and geometry/bias trade-off of a scaled (L = 10 nm) device memory cell architecture with a body raised region and source/drain separation spacers is studied, concepts already proposed independently of each other. Source and drain separation spacers reduce the electric field in the active region of the device with consequent reduction of BBT/TAT degradation, but with a reduction of the channel current and of the programming window due to the higher series resistance. On the other hand, the body raised region stores the excess charge during device operation separating it from the conduction charge flow with consequent reduction of the field and thermal SRH recombination, inducing higher retention time and programming window. The raised body is therefore used to balance the current reduction due to the spacers, without affecting device area. Moreover, the body raised region switches off BBT and TAT as source/drain separation. The geometrical and technological scaling is influenced only by electrostatic degradation as BBT/TAT are switched off by the spacers and by the body raised region. The performances of the memory cell depend on a trade-off between geometry and bias. In particular, the trade-off between the body raised region height (WR), the spacers length (L SP ) and the gate bias (V G ) is studied, as reported in Figure 11. While WR can be increased without affecting device area, L SP and |V G | require to be minimized for future scaled technologies. It is evident that the combined approach of body raised and source/drain separation regions is able to increase the retention time or the programming window by more than one order of magnitude in order to address the requirements of embedded or stand-alone applications.