3.3-kV 4H-SiC Split-Gate DMOSFET with Floating p+ Polysilicon for High-Frequency Applications

: A split-gate metal–oxide–semiconductor ﬁeld-effect transistor (SG-DMOSFET) is a well-known structure used for reducing the gate–drain capacitance (C GD ) to improve switching characteristics. However, SG-DMOSFETs have problems such as the degradation of static characteristics and a high gate-oxide electric ﬁeld. To solve these problems, we developed a SG-DMOSFET with ﬂoating p+ polysilicon (FPS-DMOSFET) and compared it with a conventional planar DMOSFET (C-DMOSFET) and a SG-DMOSFET through Technology Computer-Aided Design (TCAD) simulations. In the FPS-DMOSFET, ﬂoating p+ polysilicon (FPS) is inserted between the active gates to disperse the high drain voltage in the off state and form an accumulation layer over the entire junction ﬁeld effect transistor (JFET) region, similar to a C-DMOSFET, in the on state. Therefore, the FPS-DMOSFET can minimize the degradation of static characteristics such as the breakdown voltage (BV) and speciﬁc on resistance (R ON,SP ) in the split-gate structure. Consequently, the FPS-DMOSFET can shorten the active gate length and achieve a gate-to-drain capacitance (C GD ) that is less than those of the C-DMOSFET and SG-DMOSFET by 48% and 41%, respectively. Moreover, the high-frequency ﬁgure of merit (HF-FOM = R ON,SP × C GD ) of the FPS-DMOSFET is lower than those of the C-DMOSFET and SG-DMOSFET by 61% and 49%, respectively. In addition, the FPS-DMOSFET shows an E MOX of 2.1 MV/cm, which guarantees a gate oxide reliability limit of 3 MV/cm. Therefore, the proposed FPS-DMOSFET is the most appropriate device to be used in high-voltage and high-frequency electronic applications.


Introduction
4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are considered promising candidates for high-temperature and high-voltage applications [1,2]. Recently, several studies have been conducted on trench MOSFETs (UMOSFESTs) owing to their high channel mobility and small cell pitch [3][4][5]. However, a high gate-oxide electric field occurs at the trench gate corner, leading to reliability issues in the gate oxide. To achieve stable operation, the maximum electric field in the gate oxide (E MOX ) must be lower than 3 MV/cm [6]. In addition, the gate-drain capacitance (C GD ) and gate-drain charge (Q GD ) of trench MOSFETs are higher than those of planar MOSFETs (DMOSFESTs) due to the large cell density. Furthermore, in high-voltage applications (>3.3 kV), the channel resistance of trench MOSFETs does not have a significant effect on the overall resistance owing to the thick drift region [7]. Therefore, planar MOSFETs are more suitable for high-voltage and high-frequency applications.
The high-frequency performance of SiC MOSFETs is generally evaluated using the highfrequency figure of merit (HF-FOM), which is calculated as R ON,SP × Q GD or R ON,SP × C GD , where R ON,SP is the specific on resistance. A well-known method for reducing C GD is the use of the split-gate MOSFET (SG-MOSFET) structure [8,9], which is shown in Figure 1b. This structure improves HF-FOM through reduction of C GD by decreasing the active gate length protruding into the n-drift region (L SG ). However, this structure substantially decreases Baliga's figure of merit (BFOM), which is calculated as BV 2 /R ON,SP [10]. In particular, SG-DMOSFETs have a serious problem of a high E MOX at the gate-oxide corner, which leads to issues with the reliability of the gate oxide. Previously, we showed that, for high-voltage (>3.3 kV) SG-DMOSFETs, the BFOM reduction is intensified as the L SG decreases compared to the HF-FOM improvement [11]. The decrease in BFOM and gate-oxide reliability issues limits the ability of SG-DMOSFETs to improve HF-FOM at high voltages. The present study proposes and analyzes a new SG-DMOSFET with floating p+ polysilicon (FPS-DMOSFET) in comparison with a conventional planar MOSFET (C-DMOSFET) and conventional SG-DMOSFET through technology computer-aided design Technology Computer-Aided Design (TCAD) simulations. The floating p+ polysilicon (FPS) of the FPS-DMOSFET forms an accumulation layer in the on state and disperses the high drain voltage due to the relatively low potential in the off state. Consequently, the FPS-DMOSFET can have a shorter L SG with significantly less BFOM degradation than the SG-DMOSFET. In addition, it can overcome the problem of electric-field crowding at the active gate oxide, enabling stable operation. The simulation results show that the FPS-DMOSFET achieves not only the best HF-FOM among the studied structures but also an E MOX lower than 3 MV/cm.

Device Structures and Fabrication Process
The simulations in this study were conducted using Sentaurus TCAD simulation from Synopsys, Inc. [12]. The models used in the simulation include the doping-dependent carrier mobility model; Shockley-Read-Hall (SRH) recombination, Auger recombination, and inversion and accumulation layer mobility models, and de Man models for impact ionization. Incomplete ionization, high-field velocity saturation, and band-narrowing models are also used [13][14][15]. Figure 1 shows schematic cross-sectional views of (a) a C-DMOSFET, (b) a SG-DMOSFET, and (c) the proposed FPS-DMOSFET. The doping concentration and device dimensions of the C-DMOSFET and SG-DMOSFET are described in our previous work [10]. All structures had a drift-layer thickness of 30 µm and an n-drift doping concentration of 1.5 × 10 15 cm −3 . The channel length was 0.5 µm, the doping concentration of the channel region was 1 × 10 17 cm −3 , and a fixed charge concentration of 3 × 10 12 cm −2 was included at the interface between 4H-SiC and SiO2 to set an adequate threshold voltage. In addition, the L SG of the SG-DMOSFET was 0.7 µm. The detailed device parameters are listed in Table 1. In the FPS-DMOSFET, FPS is inserted between the active gates. It plays a role in preventing the deterioration of the static characteristics because FPS disperses the high drain voltage in the off state and forms an accumulation layer in the on state, resulting in superior BFOM compared to the SG-DMOSFET.  Figure 2 shows the proposed fabrication procedure of the FPS-DMOSFET. First, the p+ base and n+ source regions are formed by ion implantation. Next, thermal oxidation and n+ polysilicon deposition are performed, as shown in Figure 2b. Then, n+ polysilicon is etched using reactive-ion etching (RIE) to form a split active gate. Subsequently, an interlayer dielectric oxide (ILD) is deposited through low-pressure chemical vapor deposition (LPCVD), which forms a relatively low defect density [16,17]. Next, the ILD is etched to form space for FPS. The thickness of the side oxide between the active gate and FPS (T S,OX ) is one of the most important parameters in FPS-DMOSFETs, which affects both static and dynamic characteristics. Therefore, in this ILD etching process, T S,OX is determined by the alignment of the ILD etching process. Accordingly, the oxide between the FPS and n-drift is formed with a thickness of 50 nm through thermal oxidation. Next, p+ polysilicon is deposited by LPCVD and etch-back [18,19]. ILD is deposited through LPCVD again. Finally, the source and drain electrodes are formed.

FPS-DMOSFET Optimization
In the FPS-DMOSFET optimization process, L SG is one of the most important parameters that determine the performance. A decrease in L SG leads to a decrease in C GD , which improves the HF-FOM; however, it causes deterioration of static characteristics such as BV and R ON,SP . Therefore, L SG should be optimized to enhance the performance of the proposed FPS-DMOSFET, considering both BFOM and HF-FOM. Figure 3 shows the change rate of R ON,SP , BV, and C GD according to L SG . To simultaneously analyze the effect of L SG on device characteristics, the R ON,SP , BV, and C GD of the FPS-DMOSFET were compared by dividing them by the corresponding values for the C-DMOSFET. First, as shown in Figure 3, the FPS-DMOSFET does not increase R ON,SP even if L SG decreases, unlike the SG-DMOSFET, because the FPS forms an accumulation layer in the on state. This allows the FPS-MOSFET to significantly improve the trade-off relationship between BFOM and HF-FOM. On the other hand, a decrease in L SG affects BV and C GD . Figure 3 shows that a reduction of L SG slightly decreases BV while causing a significant improvement in C GD . Therefore, considering both BFOM and HF-FOM, the best performance of the FPS-DMOSFET can be obtained when L SG is set to 0 µm. Although it is difficult to achieve precise alignment in the fabrication process, we assumed it to be the ideal case in the simulation. In addition, as the FPS-DMOSFET is proposed for high-frequency applications, optimization has been performed with a focus on reducing C GD . However, the FPS-DMOSFET has a higher C GD than the SG-DMOSFET when they have the same L SG . Figure 4 shows the C GD change of the SG-DMOSFET and FPS-DMOSFET according to the change in L SG . In Figure 4, the C GD of the FPS-DMOSFET is larger than that of the SG-DMOSFET when both have the same L SG because of the FPS between the active gates in the FPS-DMOSFET. Figure 5 shows the capacitance analysis of the two structures and a capacitance model that schematically shows these capacitances. The C GD of the SG-DMOSFET consists of a series connection of (1) Cox, the capacitance formed by the overlapping region between the active gate and n-drift and (2) C DEP , the capacitance formed by the depletion region in the junction field effect transistor (JFET) region [9]. Therefore, the C GD of the SG-DMOSFET can be expressed as follows: In contrast, the C GD of the FPS-DMOSFET has additional capacitance factors originating from the FPS, active gate, and n-drift, as shown in Figure 5b [20]. Therefore, the total C GD of the FPS-DMOSFET can be expressed as follows: where C F is the total capacitance of the additional factors due to the FPS of the FPS-DMOSFET. In Equation (3), C F1 is the capacitance formed by the overlapping region between the active gate and FPS, and C F2 is the capacitance formed by the overlapping region between the n-drift and FPS. In other words, C F1 is determined by the side-oxide thickness between the active gate and FPS (T S,OX ), and C F2 is determined by the gate-oxide thickness (T OX ). Based on Equation (2), C F must be minimized to reduce the C GD of the FPS-DMOSFET. However, there is a limit to the increase in T OX because it has a significant influence on the static characteristics. Therefore, the FPS-DMOSFET was optimized by increasing T S,OX to reduce C F .    Figure 5. Therefore, T S,OX must be increased to minimize C F . However, increasing T S,OX decreases BV because the drainvoltage dispersion effect of the FPS is reduced in the off state. Therefore, T S,OX should be optimized to enhance the performance of the FPS-DMOSFET. In Figure 6, C GD begins to gradually saturate to a level similar to that of SG-DMOSFET for all L SG values from the point where T S,OX is 250 nm. Therefore, the optimized T S,OX of the FPS-DMOSFET is set to 250 nm.  Figure 7 shows the static characteristics, such as BV, R ON,SP of the three structures. These results are summarized in Table 2. The on-state characteristics were obtained with V GS and V DS set to 20 V. The C-DMOSFET and FPS-DMOSFET have the same R ON,SP of 15.66 mΩ·cm 2 , but the SG-DMOSFET has a higher R ON,SP of 17.88 mΩ·cm 2 . All three structures have the same structure, except for the gate structure. This implies that only the gate structure affects R ON,SP . This can be explained through the following equations representing the accumulation-layer resistance (R A,SP ) and JFET resistance (R JFET,SP ), respectively [21]:

Static Characterisitics
where K A is a coefficient accounting for the current spreading from the accumulation layer to the JFET region, W CELL is the cell pitch, µ nA is the electron mobility of the accumulation layer, V GS is the biased gate voltage, and V TH is the threshold voltage. In Equation (5), ρ JFET is the conductivity of the JFET region, and W 0 is the zero-bias depletion width formed by the junction between the p-base and n-drift under the gate. According to the above equations, a shorter L SG results in a shorter accumulation-layer length, implying a decrease in R A,SP . However, this causes a larger increase in R JFET,SP and a resultant increase in R ON,SP . In addition, in the off state (Figure 7b), the leakage current of the FPS-DMOSFET is the largest and the C-DMOSFET is the smallest. This is because the voltage applied to the body diode composed of p+ base and n−drift increases as the active gate length decreases. However, since the leakage currents of the three structures are almost the same, the overall characteristics are not significantly affected.   Figure 8 shows the electron current densities of the three structures with V GS and V DS set to 20 V. In Figure 8a, the accumulation layer is formed on the entire JFET region owing to the active gate of the C-DMOSFET. On the other hand, in Figure 8b, the accumulation layer breaks in the middle of the JFET because no active gate exists in the middle of the JFET region. As previously mentioned, it leads to an increase in R ON,SP due to the increase in R JFET,SP . Therefore, the SG-DMOSFET, which has a shorter L SG , has a 14% larger R ON,SP compared with the C-DMOSFET. However, as shown in Figure 8c, the FPS-DMOSFET shows the same transformation of the accumulation layer as the C-DMOSFET, despite having a smaller L SG than those of the C-DMOSFET and SG-DMOSFET. This is because FPS, which has a high electrostatic potential, forms an accumulation layer over the entire JFET region. In addition, Figure 9 shows the electrostatic potential of the three structures with V GS and V DS set to 20 V. Figure 9b shows that the SG-DMOSFET has a remarkably low electrostatic potential in the region where the active gate does not exist. However, as shown in Figure 9c, the electrostatic potential of the FPS is very close to that of the active gate; therefore, the FPS-DMOSFET shows a similar performance as the C-DMOSFET in the on state. In the off state, the p+ base junction is the main region that sustains the high drain voltage before avalanche breakdown. Furthermore, this cause of breakdown is strengthened as L SG decreases, leading to premature p+ base junction breakdown [22]. This is the main cause of the BFOM deterioration in the SG-DMOSFET. Figure 10 shows the electrostatic potential in the off state (V DS = 3000 V, V GS = 0 V). Unlike the SG-DMOSFET (Figure 10b), the FPS-DMOSFET in Figure 10c maintains a relatively low electrostatic potential at the center of the gate structure owing to the FPS. In other words, in the FPS-DMOSFET, the FPS mitigates this effect. Consequently, the concentrated drain voltage across the p + base junction is distributed. Therefore, the optimized FPS-DMOSFET has a BV very close to that of the SG-DMOSFET, although the L SG (=0 µm) is significantly lower than that of the SG-DMOSFET (0.7 µm).   Moreover, owing to the relatively low electrostatic potential of the FPS, the FPS-DMOSFET has a smaller E MOX than the SG-DMOSFET. Figure 11 shows the electric-field distribution of the three structures with V DS and V GS set to 3000 V and 0 V, respectively. The SG-DMOSFET shows an E MOX of 3.4 MV/cm owing to the electric-field crowding effect at the active gate corner. Consequently, the SG-DMOSFET does not guarantee the reliability of the gate oxide. On the other hand, the E MOX of C-DMOSFET and FPS-DMOSFET is equal to 2.1 MV/cm. Therefore, the FPS-DMOSFET can guarantee gate-oxide reliability with the split-gate structure applied through FPS.

Dynamic Characteristics
In the simulation of dynamic characteristics, the active area of the device under test (DUT) was set to 1 cm 2 . Figure 12a,b show the capacitance graphs of the three structures. The capacitance simulation conditions were as follows: the AC small signal was set to 1 MHz, V GS was fixed at 0 V, and V DS was swept from 0 V to 1500 V. Figure 12a indicates that the FPS-DMOSFET exhibits the smallest C GD . As mentioned earlier for the capacitance modeling, the FPS-DMOSFET has additional C GD factors due to the FPS. However, the optimized FPS-DMOSFET has a smaller L SG than the SG-DMOSFET, resulting in a smaller C GD . In addition, because T S,OX is sufficiently thick (=250 nm), additional C GD factors due to the FPS are significantly eliminated. Similar to C GD , the input capacitance (C ISS ) is a very important parameter because it affects the delay time in the switching cycle [23]. As shown in Figure 12b, the C ISS values of the FPS-DMOSFET, SG-DMOSFET, and C-DMOSFET are 10.13, 11.82, and 12.37 nF/cm 2 , respectively. This is because the gate-source capacitance (C GS ) decreases as L SG decreases. Moreover, in Figure 12b, all three structures have almost the same output capacitance (C OSS ).  Figure 13a shows the gate charges of the three structures. The test circuit is shown in Figure 13b, and a constant current of 100 mA was used to charge the gate. In addition, a supply voltage of 1700 V and a load current of 100 A were used to charge the gate of the test circuit. The total gate charge (Q G ) affects the delay time, and it is dependent on C ISS . Moreover, Q GD determines the switching power loss and it is dependent on C GD .  Finally, switching parameters such as the turn-on time (T ON ), turn-off time (T OFF ), turnon energy loss (E ON ), and turn-off energy loss (E OFF ) are extracted through a double-pulse test simulation, and the results are summarized in Table 3. Figure 14a,b show the turn-off and turn-on transients of the double-pulse test simulation. In addition, the test circuit for the double-pulse test simulation is shown in Figure 14c. In this circuit, the external gate resistance and stray inductance were set to 10 Ω and 10 nH, respectively. The gate voltage was swept from −5 V to 20 V to switch between the off and on states. The supply voltage and load inductance were set to 1700 V and 170 µH, respectively, and the first gate pulse was biased for 10 µs; therefore, the load current was set to 100 A/cm 2 . The body diode of the DUT was used as a freewheeling diode. In this paper, T ON and T OFF are defined as follows [24]: T OFF = T D,OFF + T F where T D,ON is the turn-on delay (from 10% of V GS to 90% of V DS at the rising edge of the second pulse), T R is the rise time in the turn-on transient (from 90% to 10% of V DS at the rising edge of the second pulse), T D,OFF is the turn-off delay (from 90% of V GS to 10% of V DS at the falling edge of the first pulse), and T F is the fall time in the turn-off transient (from 10% to 90% of V DS ). As a result, FPS-DMOSFET with C ISS has the fastest T ON and T OFF as 71.1 ns and 310.9 ns, respectively.
In addition, Figure 15 shows the extracted total switching energy loss (E TOTAL = E ON + E OFF ) of the three structures. Due to the smallest C GD , FPS-DMOSFET has the E ON of 3.31 mJ/cm 2 and E OFF of 5.20 mJ/cm 2 , so that E TOTAL is 8.51 mJ/cm 2 , which decrease by 43% and 21%, respectively, compared to C-DMOSFET and SG-DMOSFET.

Conclusions
In this paper, an SG-DMOSFET with floating p+ polysilicon (FPS-DMOSFET) was proposed and analyzed in comparison with a C-DMOSFET and a SG-DMOSFET through TCAD simulations. The FPS-DMOSFET shows a shorter L SG with significantly less BFOM degradation than the SG-DMOSFET because the proposed structure has FPS between the active gates, forming an accumulation layer in the on state and dispersing the high drain voltage due to the relatively low potential in the off state. As a result, the HF-FOM of the FPS-DMOSFET is improved by 61% and 49%, respectively, compared to the C-DMOSFET and SG-DMOSFET. Therefore, the FPS-DMOSFET not only has the fastest T ON and T OFF , but also the smallest E ON and E OFF during the switching operation. Moreover, the FPS-DMOSFET has an E MOX of 2.1 MV/cm, which is lower than that of the SG-DMOSFET (3.4 MV/cm) and the same as that of C-DMOSFET. This implies that the FPS-DMOSFET can guarantee reliable operation. Therefore, FPS-DMOSFETs can significantly improve HF-FOM while solving serious problems in SG-DMOSFETs, such as BFOM degradation and a high E MOX at high voltages.