A 40-nm CMOS Piezoelectric Energy Harvesting IC for Wearable Biomedical Applications

Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). 1 Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan; leankarlo.tolentino.ph@ieee.org (L.K.S.T.); billy0327@vlsi.ee.nsysu.edu.tw (P.-C.C.) 2 Institute of Undersea Technology, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan 3 Electrical and Electronics Engineering Institute, University of the Philippines Diliman, Quezon City 1101, Philippines; richard.hizon@eee.upd.edu.ph 4 Department of Mechanical and Electro-Mechanical Engineering, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan; alden0113@gmail.com (C.-K.Y.); pan@mem.nsysu.edu.tw (C.-T.P.) 5 Department of Electronic Engineering, National Yunlin University of Science and Technology, Yunlin 64002, Taiwan; hsuehyh@yuntech.edu.tw * Correspondence: ccwang@ee.nsysu.edu.tw


Introduction
There is a huge demand for wearable sensors which are mainly used in monitoring health status of patients. Conventional batteries which are utilized as power supplies of these wearable sensors are being replaced. They may leak when they are not properly handled or packaged causing danger to the person. In addition, they cannot supply these wearables consistently due to limited battery capacity and the recharging requirement [1]. Moreover, they occupy too much space and add weight to the wearable sensor platforms [2,3]. Hence, they make the person wearing them feel uncomfortable. As a substitute for batteries in wearable sensor platforms, energy harvesting is being sought as a possible solution in providing power to these wearable sensors.
Meanwhile, human movements like feet and leg motion (walking and running), finger motion (writing and typewriting), and muscle contractions (heart, lung, and muscles) can bring an ample amount of wasted energy which can be harvested and converted to electricity. These biomechanical motions are commonly harvested by piezoelectric, electromagnetic, and triboelectric technologies [4,5]. Among the three energy harvesting technologies, piezoelectric is the most widely used and researched. Through the mechanical deformation of a piezoelectric material, an electricity is generated [4,6,7]. Some of the advantages of piezoelectric energy harvesting over the two technologies are higher energy density and output voltage [4,8]. The most widely known applications which utilized piezoelectrics are implemented in shoes [5,9]. More energy is generated by the piezoelectric when this is placed in shoes due to the weight exerted by the user standing on it and the continuous activities made by the user by walking and running. However, the generated output voltage from the vibration of piezoelectric material is not enough to supply or drive an electronic system [10]. One advantage of piezoelectric is that they can be easily integrated and interfaced with electronic systems implemented in a chip for more enhanced energy harvesting; thus, output voltage is now boosted [4,8,11,12].
Many related works have been reported regarding piezoelectric energy harvesting ICs for typical and wearable biomedical applications. A 0.5-µm piezoelectric energy harvester was developed for wireless temperature monitoring which is capable of interfacing with wearables or implants where their data can be transmitted through the Internet (Internet of Things or IoT) [13]. It operates at a minimum input voltage of 0.51 V but generates voltage of only 3 V. In [8], they used a 130-nm CMOS full-bridge rectifier as energy harvester since the the voltage drop across the full-bridge rectifier is lower than the traditional off-chip diode. The voltage conversion ratio or pump gain is 0.987 while the output power is 10.7 µW. Meanwhile, a piezoelectric energy harvesting circuit was developed that serves as supply to the wearable cannula for infant respiratory monitoring [14]. It has a pump gain of 0.987 but a higher output power of 11.1 µW. A buck-boost converter was used for an input voltage of 0.54 V amplitude [15]. Its generated output voltage and power are 3.3 V and 57 mW, respectively. A 0.18-µm piezoelectric energy harvester for wireless sensor nodes was proposed [16], where its possible generated output power and voltage are 94 µW and 1.8 V for an input voltage of 1 V. Lastly, a study in [17] presented a 0.5-µm CMOS vibrational energy harvester that has a pump gain of 3 but only operates at a minimum input voltage of 1 V.
In this study, a piezoelectric made from polyvinylidene fluoride (PVDF) was used because it is flexible which makes it to be wearable, comfortable, and non-intrusive or unobtrusive [14] to the users than the brittle piezoelectric made from lead zirconate titanate (PZT) [18]. The said PVDF as shown in Figure 1 has a wire diameter of 10 µm and wire length of 1 mm. It has a vibration frequency of 6.67 Hz and maximum output voltage of 45 mV. Its output voltage was increased to 120 mV through series connection of the fibers. It was placed on the insole of the shoe.
Based from the previous works presented, none of them have developed an energy harvesting circuit that can accommodate an input voltage below 0.5 V. Previously, we proposed a PVDF film-based energy harvesting circuit [3] for the detection of missing children and elderly using a Bluetooth low energy (BLE) transceiver which requires at least 1 V power supply. Post-layout simulations were made for the evaluation of the said energy harvesting circuit with no chip implementation, measurements, and theoretical analysis conducted. In this paper, an energy harvesting circuit for low voltage PVDF piezoelectric which accommodates at least 120 mV-amplitude input voltage was realized that can be utilized for wearable biomedical applications. TSMC 40-nm CMOS process was used for implementation and fabrication of the energy harvesting IC. The fabricated chip was embedded inside the heel of the shoe for testing. It generates a maximum voltage of 1 V which is enough to drive and supply low-power and low-voltage wearable sensor platforms and systems.

System Architecture of Energy Harvester
The piezoelectric energy harvesting circuit architecture for wearable biomedical applications is shown in Figure 2. It is composed of AC/DC Converter, Voltage Monitor, and DC/DC Converter, which will be presented in the following subsections.

AC/DC Converter
In piezoelectric material energy harvesting circuits, AC/DC converters are needed. There are many different implementations for AC/DC converter circuits, e.g., [19]. However, due to efficiency and simplicity in practical applications of PVDF energy harvesting circuit for wearable biomedical devices, Voltage Multiplier or Charge Pump as shown in Figure 3 was selected in this study as AC/DC Converter in Figure 2. This 5-stage Voltage Multiplier is widely used in energy harvesting to convert AC to DC signals. It is a switched capacitor which elevates the lower voltage to a higher voltage value. Moreover, it can provide a preliminary boost to facilitate the design of the DC/DC Converter, thereby alleviating the problem of too small input voltage in the subsequent DC/DC Converter design. Because the PVDF film's output voltages at PZ1 and PZ2 are very low, a low V th transistor is utilized reducing the voltage drop and boosting the voltage efficiently.

Voltage Monitor
Since a very low output voltage is generated by the PVDF film, energy must be stored at C st first. Then, the next stage will be driven by the large stored energy in C st . As shown in Figure 4, V st is monitored by a CMOS-based Schmitt trigger [20]. When V st > high switching voltage V SPH , the power MOS switch M sw in Figure 2 is switched on. At this moment, the DC/DC converter is started by an enable signal (V sw_n = 1). When V st < low switching voltage V SPL , a disable signal is sent by the Schmitt trigger (V sw_n = 0) to turn off the DC/DC converter and restore energy in C st .

DC/DC Converter
The Boost DC/DC Converter is displayed in Figure 5 [21]. It is composed of Digital Logic, On-time Mode Generator (T on Generator), Off-time Mode Generator (T off Generator). The PMOS switch P sw is used to replace the diode which has lower voltage drop and better efficiency; hence, the said converter is a synchronous type instead of a diode architecture. Because of very low output voltage of PVDF, the bucket fountain method [22] is used in which the energy is kept in C st until it is fully charged to the preset voltage value, and then the second stage boost is used to drive the wearable biomedical device. The Voltage Monitor is used to determine whether the stored voltage is sufficient. If the stored voltage is large enough, the power transistor (M sw ) in Figure 2 is turned on, and a large enough voltage is generated through the DC/DC converter to drive the wearable biomedical device. The system is in standby state waiting for the next startup. When the Voltage Monitor sends an enable signal (V sw_n = 1), the DC/DC converter will now start to operate. S 1 , S 2 , and S 3 are generated by the Digital Logic. S 2 and S 3 are denoted by S 2_b and S 3_b , respectively. A comparator is interfaced to the Digital Logic for output adjustment.

T on Generator
The T on Generator in Figure 5 is shown in Figure 6. It directs the V n signal in Figure 5 to maintain the high pulse width (V n = 1) which governs the ON time of the POWER NMOS N sw . During T on mode, S 1 is high, S 2 and S 3 are low, MN3 is turned on while MP4 is at cutoff. A fixed current (I on ) discharges C on when V con < V in is achieved. During T off mode, S 1 and S 3 are low, S 2 is high, and MN3 and MP4 are at cutoff prior to becoming equal values of V con and V in . Figure 7 shows the timing diagram at T on mode.

T off Generator
The Toff generator in Figure 5 is shown in Figure 8. It directs the V p signal to maintain the low pulse width (V p = 1) for the ON time of power PMOS transistor P sw , and generates charging and discharging currents through the current mirror. During T on mode where S 1 is high, S 2 and S 3 are low, transistors MN7, MP10, and MN11 are at cutoff. On the contrary, during T off mode, where S 1 and S 3 are low, S 2 is high, MN11 is at cutoff while MN7 and MP10 are on. Therefore, this charges C off with a fixed current until V coff > V in is expected. Figure 9 shows the timing diagram at T off mode.

Digital Logic
Digital Logic in Figure 5 controls the signals' timing sequence in the DC/DC converter, so that the DC/DC converter follows a predefined function for it to be operated correctly. Figures 10 and 11 show the flowchart and the timing diagram, respectively, of the timing control of Digital Logic in steady state. There are 3 modes: idle, on-time (T on ), and off-time (T off ). Looking at Figures 5 and 10, the DC/DC converter starts at idle mode, and Digital Logic is at initial state when V sw_n is low and S 3 and V con are high.  The power MOS transistor (M sw ) in Figure 2 will be on when a sufficiently high voltage is across C st ; thus, making V sw_n high. When S 1 which is connected to the Gate Buffer of N sw and V sw_n are high, and S 2 which is connected to the Gate Buffer of P sw is low, the system enters T on mode. At this time, the inductor L stores energy when I L flows through N sw . The T on generator controls the duration of the T on mode. It will enable S 1 to low after a predefined time when V con drops below V in changing the system from T on to T off mode.
When S 2 is high and S 1 is low, the system enters T on mode. C load charges when (I L ) flows through P sw . The T off generator controls the duration of the T off mode. It will enable S 2 to low and S 3 to high after a predefined time when V in drops below V coff returning the system back from T off to idle mode. Figure 12 shows the Reference Current Generator which provides a stable reference current (I bias ) needed in Figures 6 and 8. The duty cycle contributed by the power switches (N sw and P sw ) depend on the Reference Current Generator. Since I bias can be affected by power supply's voltage and temperature variations, proportional (PTAT) and complementary to absolute temperature (CTAT) circuits are implemented to suppress the influence of temperature on accuracy and stability. In PTAT, both MN1 and MN2 are driven to subthreshold operation while both MP3 and MP4 are biased into strong inversion operation. PTAT current generator consists of transistors MN1, MN2, MP3, and MP4. Its generated I pt0 is mirrored by MP3 and MP9 to the resulting (I pt ). Moreover, CTAT current generator is composed of MP5, MN6, MN7, and MP8. Its I nt0 is mirrored by MP8 and MP9 to the output (I nt ). Then, the output current I bias is the sum of I nt and I pt , which will be insensitive to temperature variations. The two comparators in the T on and T off Generators are used to regulate the on-time and off-time modes' maintenance duration, respectively. For these two comparators, their propagation delay and noise have less effect to the their function and performance than the output-regulated Comparator in Figure 5. Therefore, the two comparators' quiescent current can be fixed to a smaller value to consume less power. However, the trade-off is that the propagation delay will be larger. In this design, a two-stage open-loop comparator is used for the AC/DC converter's output adjustment. It is shown in Figure 13.

Measurement Results and Discussion
TSMC 40-nm CMOS process was used to implement and fabricate the PVDF piezoelectric energy harvesting IC. All of the transistor lengths are at minimum size. The aspect ratio of the width of the NMOS and PMOS transistors used in this chip is 2:1. The layout view of the core which has an area of 0.1223 × 0.1065 mm 2 is shown in Figures 14 and 15 and shows the die photo of the chip which has an area of 0.7097 × 0.7097 mm 2 . The core was covered by a dummy layer, as seen in the die photo, because there is a minimum metal density required by the foundry; hence, only the pads and the wire-bonds can be seen in the photo.  The fabricated chip was connected to PCB board and SMA connectors to reduce the loading effect. A power supply (ABM PRT3230 (ABM, Hsinchu City, Taiwan)) was used to provide VDD (0.9 V) and GND. A signal generator (Tektronix AFG3252 (Tektronix, Johnston, OH, USA))provides input signals for testing. It generates a 120 mV-amplitude sinusoid which mimics the excitation and the output voltage of the PVDF film for easy testing and validation of the proposed energy harvesting circuit. An oscilloscope (Teledyne Lecroy Waverunner 610Zi (Teledyne Lecroy, Thousand Oaks, CA, USA))observed the input and output waveforms. It was also used for the measurement and characterization of the PVDF film's output voltage.
The output signal generated by the PVDF film, V st , and V sw_n signals are shown in Figure 16. A maximum of 100 kHz was used as PVDF's vibration frequency for this testing. From Figure 17, it is noted that at the beginning the capacitor (C st ) was charged at 260 mV. When V st reaches at least 260 mV, the Voltage Monitor sends an enable signal (V sw_n = 1 V) to the DC/DC Converter to start the second mode of boosting which is the T on mode.    Figure 18 summarizes the output specifications. The output voltage, current, and power are 1 V, 4.2 mA, and 4.2 mW, respectively. When the on-voltage value (V on ) is lower than V st (237 mV), V sw_n is 0 then wait for the next enable signal. The resulting waveforms of the digital logic timing control in steady state is shown in Figure 18. It is consistent with the designed Digital Logic's timing control waveforms in Figure 19.   Figure 20 shows the waveform of the output voltage V out generated by the piezoelectric energy harvesting IC which is 1 V. For the PVDF generated voltage of 120 mV to 1 V, a regulated output voltage of 1 V is expected. The developed piezoelectric energy harvesting IC can be operated with a PVDF's vibration frequency of 6.67 Hz to 100 kHz. The measurement results correspond with the post-layout simulation results made in the prior work [3]. With this, it can provide a stable power supply to the low-power and low-voltage wearable biomedical devices. The proposed piezoelectric energy harvesting IC is compared with the prior studies as shown in Table 1. In Table 1, it should be noted that the pump gain is represented as the ratio of V out and the PVDF generated voltage. As shown in Table 1, the largest pump gain was generated by the proposed piezoelectric energy harvester IC over all the prior energy harvesting circuits cited in the literature.

Conclusions
A 40-nm CMOS piezoelectric energy harvesting IC has been presented. A Voltage Multiplier was constructed alleviating the problem of very low input voltage from the PVDF piezoelectric by boosting this low voltage. DC/DC converter improves the boosted voltage by following the Digital Logic's predefined timing of three operating modes, namely, idle, T on , and T off . With this, the low-power, low-voltage wearable biomedical devices, which normally require 1 V as their supply, can be operated at stable condition by the developed piezoelectric energy harvesting IC. Among the prior studies, the proposed energy harvesting IC exhibited the highest pump gain and accommodated the lowest piezoelectric generated voltage.