Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior

An analytical criterion for the optimization of the small-signal settling time in three-stage amplifiers is carried out. The criterion is based on making equal the two exponential decays of the step response. Including slew-rate effects, a useful design strategy for the design of three-stage operational transconductance amplifier is provided. Extensive time-domain simulations on a transistor-level design in a 65-nm CMOS process confirm the validity of the proposed approach.


Introduction
Among the various analog and mixed-signal integrated circuits, the operational transconductance amplifier (OTA) is certainly one of the most fundamental building blocks. Over the past few decades, the approach to their design has changed according to the technological scaling that, in turn, has been driven by the manufacturing processes of integrated circuits (ICs). The lowering of the intrinsic gain in MOS transistors (g m r d ∼ 10), the scaling down of the power supply voltage (V DD < 1 V) and the consequent preclusion to the adoption of cascade configurations, moved the interest of the research towards multistage amplifier topologies [1][2][3][4][5][6][7][8]. In this background, the 'speed' of OTAs has been evaluated and compared using the gain-bandwidth product (GBW) as the main performance metric.
In the last 15 years, the extending demand for circuits with fast response to step inputs (i.e., discrete-time or switched-capacitor circuits, data converters, voltage regulators, etc.) has pushed the scientific community towards the design and the optimization of the settling time in low-voltage and multistage CMOS OTAs [9][10][11][12][13][14][15][16][17][18][19]. A significant number of design procedures have been proposed. However, many of them use complex relationships to forecast the settling time from the amplifier parameters, thus becoming unpractical in a real design. Moreover, most of them do not include the slew-rate (SR) limitations that occur under large-signal condition and that, as known, can have a serious impact on the time response.
Since the 1970s, the SR in OTAs has been analyzed in detail [20][21][22][23][24][25][26][27]. However, this specific literature has either produced complex results that did not lead to manageable design equations or provided accurate SR models that were limited to specific topologies.
Recently, in [28], the authors developed an interesting and general approach for the design of three-stage OTAs from settling-time requirements including also SR effects.
Although the technique provides accurate results, it relies on the graphical analysis of the contour plots of the so-called Normalized Settling Time (NST) that change with different settling errors. Consequently, no analytical design criterion exists and, if the amplifier is required to settle within a given settling error, a new contour plot must be produced.
In this paper, we provide an analytical design criterion for optimizing the small-signal settling time of a three-stage amplifier, based on making equal the two exponential decays of the step response. This allows the designer to deal with a well-defined strategy avoiding the generation of contour plots and the design through graphical methods. Moreover, the approach considers large-signal effects since it also includes the slew-rate modeling exploiting the results in [28]. The proposed strategy is used to design a three-stage OTA from settling-time specifications. Extensive time-domain simulations confirm the validity of the proposed design strategy.

Settling-Time Modeling in Three-Stage Amplifiers
In this section, we develop a model for the settling time in three-pole amplifiers. First, we model the small-signal settling time in an all-pole amplifier (i.e., the loop gain of the amplifier has no zeros). Then, we propose a new and analytical design criterion to optimize the settling time that is based on making equal the two exponential decays of the step response. Next, we extend this design criterion to practical cases of generic amplifiers with one or more zeros in the transfer function of the open-loop gain. Finally, we extend the settling-time model by including the effects of slew-rate limitations so that we take into account the large-signal behavior, also.

Modeling of a Pure Three-Pole Amplifier
Pure three-pole amplifiers have no zeros in the transfer function of the open-loop gain. They belong to the class of the all-pole amplifiers and are modeled by where a(s) is the direct gain of the OTA, β is the feedback factor, a 0 = a(0) is the dc gain, ω d is the frequency of the dominant pole and where coefficients a 1 and a 2 represent the non-dominant poles, in general, complex-conjugate. As long as βa 0 1, the significant range of frequencies lies for ω ω d and the dc gain with the dominant pole simplify into where GBW = βa 0 ω d stands for the gain-bandwidth product of the amplifier. Hence the open-loop gain is As explained in [29], the non-dominant poles in (3) arise because of an internal feedback loop nested in the main (external) loop. This situation is represented in Figure 1a where the stage of the internal loop is made up of an inner amplifier characterized by an internal gain-bandwidth product, GBW i , and by an internal non-dominant pole, ω s .
Manipulating the internal feedback loop in Figure 1a we obtain the equivalent block schematic in Figure 1b, where the inner stage is expressed in terms of the internal gainbandwidth product and of the internal separation factor, K i = ω s /GBW i . This latter parameter is accountable for the stability of the internal loop (i.e., in a two-pole amplifier, the separation factor impacts on the phase margin as K ≈ tan(PM) and, in this specific case, the internal separation factor affects the internal phase margin, only). As a rule of thumb, we can assume that the minimum separation factor required for stabilizing the inner stage is K i = 1 [30].
For K i > 1 the inner stage is stable and, at a coarse but functional approximation, we can disregard the term s 2 /(ω 2 s K i ) in the 'non-dominant poles' block in Figure 1b. Consequently, the whole amplifier stability depends on the ratio between the overall second pole, GBW i , and the gain-bandwidth product, GBW, i.e., on the external separation factor, defined as K e = GBW i /GBW.
and, if T(s) has the form expressed in (3), we can evaluate Normalizing the complex frequency with respect to the GBW we obtain a dimensionless version of the transfer function that allows analysis of the time response of the amplifier in a very convenient manner. To do so, we define the dimensionless frequency asŝ = s/GBW and the corresponding dimensionless time ast = GBW · t so that the open-loop transfer function turns into When the system (6) is closed in a feedback loop, its response to a unity step input is a function of the dimensionless time,t, and of the separation factor vector, K = (K e , K i ), i.e., y = y(t, K). From the output response, y(t, K) we can evaluate the dynamic settling error (DSE) and the dimensionless settling time aŝ t s ( , K) = min t : DSE(t, K) ≤ ∀t ≥t (8) being , the accuracy level. Therefore, the final settling-time results From (9) it is apparent that minimizing the small-signal settling time means both maximizing the GBW and minimizing the quantityt s ( , K) by a proper optimization of the separation factor vector, K. Since the maximization of the GBW is a straightforward task, we must find a criterion for the optimization of the dimensionless settling time,t s ( , K).
In the following, to compare different settling-times at different accuracy levels, , it is convenient to use the Normalized Settling Time (NST). This is defined as the settling time of the amplifier under test normalized with respect to the settling time of a single-pole amplifier with the same GBW. In a single-pole amplifier, the settling time is t s(sp) = | ln |/GBW, therefore the normalized settling-time results in where the latter equivalence was derived from (9).

Optimization of the Dimensionless Settling Time
In a third-order system, the response to a unity step input in the time-domain takes the form whose corresponding Laplace transform is If the residues A 1 and A 2 are in the same order of magnitude, we may assume that the behavior of the amplifier's time response is mainly ruled by the two exponential decays, α 1 and α 2 . Therefore, a design criterion for optimizing the amplifier speed is to set equal the two exponential decays so that α = α 1 = α 2 . In this way none of the exponential terms will be responsible for slowing down the time response. As known, the two exponential decays depend on the poles of the closed-loop transfer function, G(s) = sY(s), whose denominator is Using (4), the closed-loop gain is and, equating the coefficients of the denominator of (14) to the coefficients of (13), we obtain the system of equations Manipulating (15) we obtain the constraint that set equal the two exponential decays in terms of K e and K i or, relating K e in terms of K i , whose plot is reported in Figure 2. Observe that since the condition in (16) is independent of the GBW, it represents a design criterion for the optimization of the dimensionless settling time,t s . Among the possible constraints set by (16), the most convenient is represented by the point K in Figure 2, placed at the minimum value of K e . Using (17) to find this minimum yields The plot of the phase margin, PM, versus K i for an ideal three-pole system designed with the constraint in (16) is shown in Figure 3. The point PM = 68.4 deg identifies the phase margin observed at the optimum bias point set by (K e , K i ) = (8/3, 9/4).
To further demonstrate the goodness of our design criterion, in Figure 4 we plot the normalized settling time, NST, versus the internal separation factor, K i , for a three-pole system designed with the constraint in (16) and for different accuracy levels, . The colored spots, all at the point of abscissa K i = 9/4, identify the normalized settling-times observed at the optimum bias point. Even if the proposed criterion does not identify the absolute minimum settling time, a satisfactorily settling time is established in a very simple manner. This is more evident considering that as reported in [29], a circuit designed for obtaining the minimum possible settling time always deviates from its target when unavoidable statistical variations of process or design parameters are taken into account.

Extension to Generic Three-Pole Amplifiers
A generic three-pole amplifier has one or two zeros in the loop gain, i.e., As demonstrated in [28] and briefly reported in Appendix A, if the frequency of the GBW lies below the zeros of T(s), two global separation factors can be introduced The global separation factors can be used to make the condition of a time response with two equal exponential decays. More specifically, the dimensionless settling time of the generic three-pole amplifier is optimized by settingK e andK i to the same values that we would choose for the pure three-pole amplifier, i.e., settingK e = K e = 8/3 and To verify the correctness of our approach, we designed the ideal amplifier in Figure 5 makingK e = 8/3 andK i = 9/4 and compared its time response to that of an ideal pure three-pole amplifier with the same GBW and designed with K e = 8/3 and K i = 9/4. We expect similar behaviors, i.e., very small NSTs, in the interval 0.4-0.6, for both circuits. The amplifier in Figure 5 exploits the well-known Reversed Nested-Miller Compensation (RNMC) for which the coefficients of the transfer function in (19) are In our design, we assumed that the amplifier required a GBW of 100 Mrad/s (about 15.5 MHz) for driving a load capacitor C L = 2 pF. Supposing that G m1 = 100 µA/V was set by noise specifications, from (21a) we obtained C C1 = 1 pF. Then we substituted (21) into (20) and finalized our design by solving for K e ,K i = (8/3, 9/4). The procedure led to C C2 = 1.1 pF and G m2 = G m3 = 752 µA/V. The time response of this 'generic amplifier' is depicted in Figure 6. For an effective comparison, the time response of a 'pure three-pole amplifier' with the same GBW is depicted also. It is observed a good matching between the two curves.  The details, in terms of settling time and NST, are reported in Table 1 for the two amplifiers. As expected, the approach for the optimization of the 'generic amplifier' produces a time response nearly as fast as the time response of the pure three-pole one. Table 1. Evaluation of the settling time, t s , for the generic amplifier and for the pure three-pole amplifier, at different accuracy levels. The amplifiers are designed settingK e = 8/3 andK i = 9/4. The NST is also reported for an effective comparison.

Extension to Slew-Rate Modeling
Slew-rate effects in operational amplifiers can be included using the simple model introduced in [31] and analyzed in detail in [28].
The model assumes that the slew-rate limitation is in the first stage of the amplifier and, in particular, that it depends on the capacitor that determines the dominant pole. If this assumption is not satisfied, the amplifier can experience a positive feedback connection during its slewing period that degrades its speed performance and results in an inefficient design. In a good design, this inefficiency must be avoided either using slew-rate enhancers or class-ab topologies [30,32,33] in the stages placed after the first one.
As a second constraint, the model assumes that the amplifier is designed so to exhibit NST ≤ 1 in small-signal condition. In our case, this simply means that the amplifier can be designed in the optimum bias point set by (K e ,K i ) = (8/3, 9/4). If the two assumptions described above are satisfied, the dimensionless settling time of the amplifier is bounded bŷ where ∆Y is the output step voltage of the amplifier and defines the equivalent saturation limit of the first stage, expressed in terms of its maximum short-circuit output current, I o1 , of its small-signal transconductance, G m1 , and of the overall feedback factor, β. Also, in this case, to compare different settling-times at different accuracy levels, , we can define the NST by normalizing the settling time of the amplifier under test with respect to the small-signal settling time of a single-pole amplifier with the same GBW. From this definition and considering (10), the NST comes from dividing (22)

The Design Strategy with Settling-Time Constraints
In this section, we propose a design strategy based on settling-time constraints. It relies on two design equations. The first design equation is represented by the system in (20) and refers to the small-signal behavior. Using this system of equations, we guarantee that the small-signal settling time of the amplifier is less than (or comparable to) the settling time of a single-pole amplifier with the same GBW.
The second design equation stems from the dimensionless settling time in (22) and accounts for the large-signal effects in terms of slew-rate. Considering thatt s = GBW · t s , the settling-time constraint allows us to dimension the GBW from where the maximum possible value for ∆Y/ν must be considered. Considering (23) we obtain that The feedback factor, β, is a parameter that is specified by the application and cannot be freely chosen by the designer. In some particular cases the feedback factor can be programmed in a range of values (i.e., in switched-capacitor circuits, β can be selected by changing the connections of a proper array of capacitors) so that β = β max must be considered in the design equation.
Concerning the ratio G m1 /I o1 , it depends on the quiescent point of the first stage and, in the common case of a CMOS source coupled differential pair, it is where Γ is the g m -over-I D ratio of the input transistors [34]. The plot of the g m -over-I D versus the gate-source overdrive is reported in Figure 7 for two complementary devices of a 65-nm CMOS process. Other nanometer CMOS processes have similar plots with no practical differences compared to the curves in Figure 7 [35]. Since, in the analog design context, transistors are biased so that V GS ∼ V TH , the choice of the g m -over-I D ratio has a limited range (typically, 8 V −1 ≤ Γ ≤ 16 V −1 ). Finally, for the maximum output step, ∆Y, we can consider the highest possible value set by the power supply, V DD .
From all these considerations, based on the required settling time, the GBW is dimensioned according to The draft of the proposed design strategy is reported in the flow-chart in Figure 8. More specifically, once that the GBW is determined based on the settling time specification, the designer has two design equations that allows him to set two suitable parameters of the OTA. The remaining parameters can be chosen freely or based on other constraints set by noise, power dissipation or other critical figures of merit that, in general, depend on the application or on the amplifier topology.
Known parameters are V DD , C L , β, t s , ε Choose the g m /I D (Γ) of the first stage Evaluate the required GBW from (28) With T(s) as in (19), determine a i and b j in terms of the OTA parameters (i.e., Gm i , C j , etc.) Use (20) with K e =8/3 and K i =9/4 for dimensioning two proper unknown parameters of the OTA

Design Example and Validation
To demonstrate and confirm the proposed design strategy, we apply it to the design of an appropriate three-stage OTA for the switched-capacitor (SC) application depicted in Figure 9. Figure 9. Forward-Euler SC integrator.
Here the circuit acts as a forward-Euler SC integrator and, assuming T s is the sampling period, it works as follows. During the sampling phase, φ 1 at time t = (n − 1/2)T s , switches S 1 and S 2 close, the sampling capacitor, C s , charges at the input voltage, v IN , while the feedback capacitor, C f , maintains the charge processed at the previous time, t = (n − 1)T s . During the evaluation phase, φ 2 at time t = nT s , the sampling capacitor, C s , discharges through the virtual ground node and transfers its charge to capacitor C f , thus updating the output. The charge balance is represented by ∆Q C s = ∆Q C f and leads to where we omitted the obvious dependance on the sampling period, T s , and used the equivalence v OUT (n − 1/2) = v OUT (n − 1). During the sampling phase, φ 1 , the OTA does not change its output and remains in the 'hold' condition. During the evaluation phase, φ 2 , the output is fed back to the inverting terminal by the voltage divider composed by C f and C s so that the OTA experiences a feedback factor β = C f /(C s + C f ). At the same time, the OTA is loaded by an equivalent capacitor given by C L = C out + C s C f /(C s + C f ). These two parameters shall be considered during the design of the OTA.
In our design example, we assume that the capacitors of the integrator in the figure are C s = C f = C out = 0.4 pF. Therefore, the OTA has to be designed considering C L = 0.6 pF and β = 0.5. We assume that the integrator operates with a sampling frequency of 25 MHz and that the target settling time is 20 ns within a 0.5% error. The power supply is V DD = 1 V.
We apply the design strategy to the transistor-level amplifier in Figure 10 made up of a differential pair (M1-M5) and two common-source stages (M6-M7 and M8-M9). The compensation is achieved through capacitors C C1 and C C2 , using a modified Reverse Nested-Miller Compensation, named RNMC-ICBFF. More specifically, capacitor C C2 is connected between the output and the input nodes of the second stage. Capacitor C C1 is connected between the output of the third stage and the input of the second one. In this latter connection the mandatory signal inversion is accomplished through the Inverting Current Buffer (ICB) made up of the current mirror M3-M4. Transistor M9, which provides the bias current to the third stage, acts also as a feed-forward (FF) stage, G mf .
The slew-rate enhancer, M10, is added in parallel to M9 to improve the SR performance at the output node during negative steps. Since M10 is a high-threshold transistor, it is normally off in bias condition. When node v 2 goes high and M8 switches off, M10 switches on and sinks the extra current required by the load. Using the equivalent block schematic in Figure 11, we evaluate the open-loop transfer function of the amplifier. Neglecting the contributions of transconductors' output resistances and parasitic capacitors, it takes the form in (19) where Figure 11. Block schematic of a three-stage OTA compensated with the Reversed Nested-Miller Compensation with Inverse Current Buffer and Feed-Forward stage (RNMC-ICBFF). Referring to the block schematic in Figure 1a, we can identify (1) the block responsible for the dominant pole and the GBW of the amplifier (light-yellow area); (2) the internal block with two real poles (light-green area); (3) the internal feedback across the internal block (light-red area). The overall feedback that will connect the output v out to the input v in is not drawn.
For the input transistors of the differential pair we choose Γ = 16 V −1 and, just for simplifying the design, the same value is adopted for the g m -over-I D of all the remaining transistors of the amplifier. Then, using (28), we obtain the minimum required GBW of 55 MHz. Observe that, in case of nanometer technologies, due to the low transistor intrinsic gain (g m r d ∼ 10), Equation (30a) overestimates the actual GBW that, in this specific case, is better approximated by being R o3 the output resistance of the third stage. To make up for this error, which can be as high as 20%, we dimension the GBW by increasing the value obtained from (28) by 20%. Hence, we consider GBW = 66 MHz in our design equations. The condition of making the same g m -over-I D ratio implies that transistors that share the same current have the same transconductance or, in other words, that G b = G m1 and G m3 = G mf . Therefore, defining we write the following normalized coefficients that can be substituted in (20) to obtain whereK e = 8/3 andK i = 9/4. Setting different values for n and m, we use MATLAB to solve (37) for T and χ and to evaluate the remaining amplifier parameters from The results of the dimensioning procedure are reported in Table 2 for different values on n and m. The table reports also the estimated current dissipation of the OTA as I DD = (2G m1 + G m2 + G m3 )/Γ, the Figure-of-Merit (FOM) that computes the speeddissipation-load trade-off as FOM = GBW · C L /(V DD · I DD ) and, neglecting the flicker noise for the sake of simplicity, the square root of the input noise spectral density, estimated as S n = 2 · 4KT(2/3)(1/G m1 )(1 + G m1 /G b ). As it can be observed, if the noise is satisfactorily to our application, the best choice in terms of current dissipation and FOM is the design corresponding to the row with n = 1 and m = 4.  We design the circuit in the Cadence environment and the corresponding transistors' aspect ratios are reported in Table 3. The open-loop gain of the circuit in Figure 9 is simulated and reported in Figure 12 in terms of Bode diagram. The reported GBW is 62 MHz with a phase margin of 61 deg.
All the following transient simulations deal with the time response of the SC integrator during the evaluation phase, φ 2 . In particular, all the steps are referred to the output signal and are centered around the analog ground, V AGND = V DD /2 = 0.5 V. This means that to simulate an output step of ∆V = +100 mV, we first precharge the output node at v OUT (n − 1) = V AGND − ∆V/2 = 0.45 V and then we apply a constant input signal v IN = (C f /C s )∆V. In this manner, from (29), the output jumps at v OUT (n) = v OUT (n − 1) + ∆V = 0.55 V.
The output step responses of the closed-loop amplifier to different step amplitudes are shown in Figure 13. Figure 13a,b depict the transient behavior of a ±100-mV output step for the rising edge and the falling one, respectively. The simulated settling-times are 12.2 ns (NST = 0.92) and 15.0 ns (NST = 1.13), respectively, for an accuracy level of 0.5%. Figure 13c,d show the transient behavior of a ±800-mV output step. In this case, the signal excursion is close to the rail-to-rail situation but still ensuring that no transistor exit from the saturation region. As expected, the slew-rate increases the 0.5% settling time up to 13.2 ns (NST = 0.99) and 17.8 ns (NST = 1.34), for the rising edge and the falling one, respectively.  Figure 14 shows the plot of the 0.5% settling time versus the step amplitude at the output node. The curve of the single-pole case, evaluated from (22), is also reported. As expected, for the rising edge, the settling time remains well below the single-pole limit up to 0.9 V. Above this value, some transistors enter the triode region, and the settling time goes out specifications. The falling output step suffers from slew-rate limitation at the output node. This is mitigated by the SR enhancer that allows the settling time to follow the single-pole limit up to 0.9 V, also in this case.    A 400-run Monte-Carlo simulation is performed to estimate how the circuit behaves under both global and local process variations. The results are condensed in the histograms in Figure 15. Figure 15a,b refer to the ±100-mV output step cases. Figure 15c,d refer to the ±800-mV output step cases. Except for a small number of samples in the 800-mV falling step case (Figure 15d), all the runs fall inside the settling-time specifications of 20 ns, a very good result considering that the circuit was not designed to be robust against process variations. However, it is easy to extend the design strategy to the worst-case corner of a PVT scenario or to integrate it with the approach described in [29].

Conclusions
In this paper, we provided an analytical design criterion for the optimization of the small-signal settling time in a three-stage amplifier, based on making equal the two exponential decays of the step response. Included the slew-rate effects to the design criterion we carried out a design strategy that was used to design a three-stage OTA from settling-time specifications. Extensive time-domain simulations confirmed the validity of the proposed design strategy. where As long as the GBW remains below the zeros of G(s) we can assume that the amplifier time response is mainly determined by the poles of its closed-loop transfer function. This consideration allows us to define the equivalent or global separation factors using the coefficients of its closed-loop gain, as we did in (A3), so that Therefore, we can optimize the step response of the generic three-pole amplifier by design the amplifier so thatK e = 8/3 andK i = 9/4. Once again, since the coefficients are normalized with respect to the GBW, the optimization will affect the dimensionless settling time, only.