1.0 V-0.18 µ m CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

: This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated G m –C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different ﬁrst-order single-ended LPFs designed in a 0.18 µ m CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The ﬁrst one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm 2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ C L = 50 pF) preserving dynamic ﬁgures greater than 78 dB. The second one exhibits a power consumption of 1.75 µ W at 500 nA with an active area of 0.0137 mm 2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ C L = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported ﬁlters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconﬁgurable front-end sensor interfaces.


Introduction
The achievement of low form factor system-on-chip (SoC) sensing devices with extended battery life or even battery-less systems capable of measuring a great variety of parameters makes the design of every single block within a general-purpose front-end sensor interface a challenge. A front-end sensor interface (Figure 1a) typically includes a transducer to convert the parameter to be measured into an electrical signal; next, a preconditioning stage consisting of a low-noise preamplifier (LNP) amplifies the signal and the low-pass filtering stage (LPF) takes out the out-of-band interferences and noise; finally the digitalization stage (ADC) allows further signal processing by a µC to extract the desired signal information [1][2][3][4]. In these acquisition systems, the analog low pass filter (LPF) is required to have a suitable low-cutoff frequency range, which in the case of biosignal front-end interfaces is mainly in the order of tens or hundreds of Hz (Table 1).
Another key application requiring SoC LPFs is an impedance-sensing device. Electrochemical Impedance Spectroscopy (EIS) characterizes a sample by exciting it with a small AC signal, minimizing the probability of damaging the sample, and recovering its impedance over a frequency range. The Frequency Response Analyzer (FRA-EIS) technique is based on dual (0, 90 • ) synchronous demodulation, that is, it uses a technique known as phase-sensitive detection (PSD) to extract at an excitation frequency f 0 the real and imaginary response. As shown in Figure 1b, the signal is typically amplified by an instrumentation amplifier (IA), then a mixer working at the same frequency f 0 (0, 90 • ) demodulates the signal, and a low pass filter (LPF) extracts the DC components X-Y, proportional to the real and imaginary response, while noisy signals at other frequencies are filtered [5][6][7][8][9][10][11]. In this case, the LPF is going to be used as a DC magnitude extractor at the last stage of the FRA-EIS read-out system to recover the signal, and it is required to have an adjustable value in the order of sub-Hz to Hz (Table 1) to adjust the accuracyspeed trade-off. Low cutoff frequencies will show better accuracy at the expense of larger acquisition times, while higher cutoff frequencies would speed up the acquisition process reducing the accuracy. This is because the LIAs can be considered as band-pass filters with a quality factor Q = (f0/fc), where f0 is the reference frequency and fc the low-pass filters cutoff frequency. Hence, the smaller the LPF cutoff frequency, the better the noise rejection and the better the recovery accuracy, but compromising related acquisition times.
The implementation of such low-frequency range LPFs in a fully integrated manner is not trivial and becomes especially challenging for portable systems, which require a low voltage design and a reduced area. In fact, Low Pass Filters with sub-Hz cutoff frequencies are generally implemented with external RC elements [12][13][14].
Electronics 2021, 10, x FOR PEER REVIEW 2 of 1 filtered [5][6][7][8][9][10][11]. In this case, the LPF is going to be used as a DC magnitude extractor at th last stage of the FRA-EIS read-out system to recover the signal, and it is required to hav an adjustable value in the order of sub-Hz to Hz (Table 1) to adjust the accuracy-spee trade-off. Low cutoff frequencies will show better accuracy at the expense of larger acqu sition times, while higher cutoff frequencies would speed up the acquisition process re ducing the accuracy. This is because the LIAs can be considered as band-pass filters wit a quality factor Q = (f0/fc), where f0 is the reference frequency and fc the low-pass filter cutoff frequency. Hence, the smaller the LPF cutoff frequency, the better the noise rejec tion and the better the recovery accuracy, but compromising related acquisition times.
The implementation of such low-frequency range LPFs in a fully integrated manne is not trivial and becomes especially challenging for portable systems, which require a low voltage design and a reduced area. In fact, Low Pass Filters with sub-Hz cutoff frequencie are generally implemented with external RC elements [12][13][14].  The most common approach to achieve such low cut-off frequencies in a fully inte grated way relies on Gm-C structures because of their topological simplicity. The load ca pacitor is typically a fixed value, which is set around 50 pF as the maximum practical on chip capacitance preserving an efficient silicon area. To reach sub-Hz cutoff frequencie with these capacitances, Gm ~nS are needed, which can be accomplished through bias cu rents ~pA, benefiting power efficiency. However, the problems for reliably generatin such low bias currents on-chip commonly leads to work with higher biasing current va ues (~10-100 nA), making it necessary to incorporate transconductance reduction tech  The most common approach to achieve such low cut-off frequencies in a fully integrated way relies on G m -C structures because of their topological simplicity. The load capacitor is typically a fixed value, which is set around 50 pF as the maximum practical on-chip capacitance preserving an efficient silicon area. To reach sub-Hz cutoff frequencies with these capacitances, G m~n S are needed, which can be accomplished through bias currents~pA, benefiting power efficiency. However, the problems for reliably generating such low bias currents on-chip commonly leads to work with higher biasing current values (~10-100 nA), making it necessary to incorporate transconductance reduction techniques for reliably reaching sub-Hz cut-off frequencies. Among them, in a power-constrained scenario, G m reduction can be effectively achieved through series-parallel current attenuation to benefit power efficiency [18], but these solutions jeopardize the area to achieve a good matching of transistors. On the other hand, G m -C topologies exhibit moderate linearity and noise performance so that the power is usually increased to achieve a certain dynamic range (DR), a compromise existing between power, area, and dynamic range (linearity and noise) in LPFs implemented following a G m -C approach with cutoff frequencies within the ranges of operation shown in Table 1.
Focusing on front-end interfaces, a review of the literature evidence that some of the LPF proposals present power consumptions of several µW not being compatible with portable devices (10 µW [19,20] has a total of 30.4 µW and [21] 233 µW). While those that present power consumption below the µW, either are expensive in terms of area consumption, which is a drawback for portable systems, (0.24 mm 2 [1] and 0.168 mm 2 [2]) or they achieve low power through bias currents too small to be generated on-chip with enough reliability (500 pA [22], from 300 pA to 900 pA [2] or 1 nA [23]). Among those that satisfy the power and area constraints, a high dynamic range (>60 dB) is required to ensure the recovery of the signals, but the reported papers show DR below these value ( [24] 54.6 dB, 50 dB [25], 34 dB [26], and 49.9 dB [27]). Moreover, most of the previously reported papers have constant cutoff frequencies (f c ) commonly doing the recovery of a single biomarker. Such is the case of some of the previously mentioned works: [1,25,27] present f c s of 250 Hz, 50 Hz and 250 Hz for electrocardiogram detection (ECG); [20] implantable devices for nervecuff signal recording work at 0.22 Hz and [26] has an f c of 5.4 kHz for signal processing in neural recording implants. Meanwhile, a review of recent integrated proposals for impedance devices shows that most of the LPFs employed with sub-Hz cutoff frequencies are designed as external passive RC filters [12,28]. As for fully integrated solutions, [29] presents the low pass filter embedded, but it is a second-order RC filter with a fixed 300 Hz cutoff frequency, dominating the 3.6 mm 2 active area consumption of the proposal.
Thus, it is clear that the achievement of a general-purpose high-performance low pass filter (LPF), covering the full frequency range from sub-Hz to hundreds of Hz with a high dynamic range (DR) to enhance the signal resolution while realizing a highly efficient CMOS topology in terms of power and area, still remains a challenge in analog circuit design, demanding new techniques and strategies to meet simultaneously all these required performances into a SoC. The design of such a LP filter is the motivation of this work, with the targeted design specifications: tunable cutoff frequency covering the main signal ranges of Table 1, power consumption below the~µW; area below~0.1 mm 2 ; bias currents greater than~10-100 nA to be reliably generated on-chip and a dynamic range above 60 dB.
Our proposal is based on a fixed g m input stage, with a continuously adjustable current steering (CS) technique in the output branch, which allows for G m -reduction and tunability. This technique has been previously presented in [30] applied to a 1.8 V mirrored Operational Transconductance Amplifier (OTA). This work presents and validates the experimental results of a modified 1.0 V-0.18 µm integrated LPF, also based on a mirrored OTA whose preliminary simulation results were presented in [31]; and a 1.0 V-0.18 µm specifically designed LPF using a folded-cascode core OTA to achieve an ultra-efficient power and area architecture. Both approaches exhibit wide tunable cutoff frequencies (~80 mHz-~1.2 kHz Mirrored,~100 mHz-152 Hz Folded), low power (1.75 µW@I bias = 500 nA-Mirrored and 180 nW, @I bias = 100 nA-Folded), and reduced size (0.0137 mm 2 -Mirrored and 0.0135 mm 2 -Folded), while keeping a high dynamic range (>73 dB-Mirrored and >78 dB-Folded), enhancing the state-of-the-art power-area-DR tradeoff. In this way, it will be suitable for a wide variety of sensing interfaces, so that it can be modularly used in an array system saving power, area and complexity.
The paper is organized as follows: Section 2 describes the proposed G m -C topologies with the G m -reduction strategy followed and in Section 3 the experimental results are summarized. Finally, conclusions are drawn in Section 4.

Low Pass Filter Proposed Topology
The proposed topologies for the two first-order single-ended G m -C integrators based on the CS approach are presented in this section. A fixed integrating capacitor set to 50 pF is used for both of them, implemented by a MOS capacitor to save area, and differ in the core OTA architecture. These core OTAs are firstly presented, followed by the G m -reduction modifications introduced in each topology, and finally three integrated versions -one based on the Mirrored OTA and two based on the Folded Cascode OTA-of the LPF are introduced.

Core OTAs
The considered core cells are shown in Figure 2. Figure 2a is the mirrored cascode OTA previously reported on [31], while Figure 2b shows a folded cascode OTA. The latter was chosen to preserve high performance with a 1.0 V voltage supply and because, while the mirrored OTA needs to be cascoded to apply the current steering (CS) technique, with the folded OTA the folding itself is enough to embed the CS technique.
The mirrored OTA is a classic structure with transconductance G m = kg m1 , g m1 being the transconductance of the differential input pair transistor M1 and k the gain factor of the current mirror. A NMOS-input pair was used with a small g m1 in the order of~µS and unity gain (k = 1) current mirrors to keep the gain, G m , reduced. This scheme provides the same gain G m = g m1 as a classic differential pair, but uncouples the input and output common-mode range at the cost of doubling the power consumption [30].

Low Pass Filter Proposed Topology
The proposed topologies for the two first-order single-ended Gm-C integrators based on the CS approach are presented in this section. A fixed integrating capacitor set to 50 pF is used for both of them, implemented by a MOS capacitor to save area, and differ in the core OTA architecture. These core OTAs are firstly presented, followed by the Gm-reduction modifications introduced in each topology, and finally three integrated versions -one based on the Mirrored OTA and two based on the Folded Cascode OTA-of the LPF are introduced.

Core OTAs
The considered core cells are shown in Figure 2. Figure 2a is the mirrored cascode OTA previously reported on [31], while Figure 2b shows a folded cascode OTA. The latter was chosen to preserve high performance with a 1.0 V voltage supply and because, while the mirrored OTA needs to be cascoded to apply the current steering (CS) technique, with the folded OTA the folding itself is enough to embed the CS technique.
The mirrored OTA is a classic structure with transconductance Gm = kgm1, gm1 being the transconductance of the differential input pair transistor M1 and k the gain factor of the current mirror. A NMOS-input pair was used with a small gm1 in the order of ~µS and unity gain (k = 1) current mirrors to keep the gain, Gm, reduced. This scheme provides the same gain Gm = gm1 as a classic differential pair, but uncouples the input and output commonmode range at the cost of doubling the power consumption [30]. The folded cascode OTA is a single-stage high-gain structure, which requires a lower supply voltage than a typical cascode amplifier. Again, the M1 NMOS-input differential pair is biased at a constant current IBias, introduced to the circuit through a simple MB 1:1 current mirror. This keeps gm1 constant (~µS by design) with transistors M1 in saturation region. The folded branches carry a current α < 1 times less than that of the main pair transistors, i.e., αIBias/2, to reduce the power consumption while enhancing the OTA gain and minimizing noise. In this way, through each PMOS M2 biasing transistors the total current is (1 + α)IBias/2. For this scheme, again the overall transconductance gain is Gm = gm1.

Gm Tuning Technique
To achieve a variable transconductance gain, both OTAs keep the input pair transconductance, gm1, constant by keeping the bias current, IBias, constant (Figure 2), and a current steering transfer section conveys the scaled current to the output. This is done, as shown in Figure 3, by splitting each M3 cascode current mirror transistor into two matched transistors M3I -M3 II with their cascode gate voltage VCP replaced by complementary control voltages Vctr = VCP + Vgc and ( ) =VCP − Vgc [32]. Following the current steering applied to the mirrored OTA (Figure 3a), transistors M2 present the same Vds and Vgs, as we set unity gain for the current mirrors, having Iin = Iout = kIM1 = II + III with k = 1. The output current is split into two complementary currents The folded cascode OTA is a single-stage high-gain structure, which requires a lower supply voltage than a typical cascode amplifier. Again, the M1 NMOS-input differential pair is biased at a constant current I Bias , introduced to the circuit through a simple MB 1:1 current mirror. This keeps g m1 constant (~µS by design) with transistors M1 in saturation region. The folded branches carry a current α < 1 times less than that of the main pair transistors, i.e., αI Bias /2, to reduce the power consumption while enhancing the OTA gain and minimizing noise. In this way, through each PMOS M2 biasing transistors the total current is (1 + α)I Bias /2. For this scheme, again the overall transconductance gain is G m = g m1 .

Gm Tuning Technique
To achieve a variable transconductance gain, both OTAs keep the input pair transconductance, g m1 , constant by keeping the bias current, I Bias, constant (Figure 2), and a current steering transfer section conveys the scaled current to the output. This is done, as shown in Figure 3, by splitting each M3 cascode current mirror transistor into two matched transistors M3 I -M3 II with their cascode gate voltage V CP replaced by complementary control voltages V ctr = V CP + V gc and (V ctr ) = V CP − V gc [32]. Following the current steering applied to the mirrored OTA (Figure 3a), transistors M2 present the same V ds and V gs , as we set unity gain for the current mirrors, having I in = I out = kI M1 = I I + I II with k = 1. The output current is split into two complementary currents I I = (1 − β) I in = (1 − β) I M1 and I II = βI in = βI M1 , with a value β dependent on V gc , comprehended between 0 and 1, and with I II > I I when V gc > 0; I I = I II when V gc = 0 and I II < I I when V gc < 0. Therefore, the transconductor scheme consists on a fixed gain V-I conversion input stage, followed by a current steering transfer section that conveys the scaled current to the output, so that the overall G m is G mI = (1 − β) g m1 and G mII = βg m1 , being the output located in branch I.
As for the current steering applied to the folded OTA (Figure 3b), the current I in = αI M1 (α < 1) is split into complementary currents I I = (1 − β) I in = (1 − β) αI M1 and I II = βI in = βαI M1 (I in = αI M1 = I I + I II ). Each output current has adjustable and complementary gain controlled by V gc with I II = I I for V gc = 0; I II > I I for V gc > 0 and I II < I I for V gc < 0. Since there are now two output branches, I and II, there are also two outputs being, the overall G m , G mI = (1 − β)αg m1 and G mII = βαg m1 with the output located in branch I.

Integrated Low Pass Filter
The single stage G m -C integrators in combination with the current steering technique (CS) presented in the previous section, are shown in Figures 4 and 5. A unity-gain feedback structure is used to increase linearity in the passband [33,34]. Current steering is applied over M3 and both NMOS current mirrors (transistors, M4) are used to drive the current to the outputs. Since there are now two branches, there are also two outputs, I and II. Output II is kept at V dd /2 to keep the symmetry of the system and ensure linear current division. The other one, output I, is the output of the integrator. This output is connected to V inachieving unity-gain feedback.

Mirrored-OTA Based Low Pass Filter
The auxiliary output branch, Output II, of the Mirrored-based Low Pass Filter uses a simple M4 current mirror, but for the Output I branch, a gain-boosting technique is used to enhance the current mirror copy and reduce the offset. A simple NMOS-input differential pair operating with a total current consumption of 0.25 µA and a DC gain of 43 dB is used with a Miller compensation network to ensure stability, as shown in Figure 4b.
This proposal has been designed in the low-cost 0.18 µm 1 P-6 M CMOS process from UMC. The maximum on-chip integrating capacitance for this technology is around 50 pF, which is the value set for the output capacitor. Transistor sizes in (µm/µm) are M1 = 7.5/10, M2 = 10/4, M3 = 5/4, M4 = 1/4, MB = 6/4, and for the auxiliary Error Amplifier M1 = 2/4, M2 = 6/4, M3 = 6/4, M3' = 3/4. Miller compensation is achieved with a 3 kΩ resistance and a 1 pF capacitance. With a 1.0 V voltage supply, V dd , and V cm set to 0.5 V. The external reference current is set to 500 nA introduced through a 1:1 current mirror to the input differential pair and through a 2:1 current mirror to the EA, with a total power consumption of 1.75 µW. The auxiliary output branch, Output II, of the Mirrored-based Low Pass Filter uses a simple M4 current mirror, but for the Output I branch, a gain-boosting technique is used to enhance the current mirror copy and reduce the offset. A simple NMOS-input differential pair operating with a total current consumption of 0.25 µA and a DC gain of 43 dB is used with a Miller compensation network to ensure stability, as shown in Figure 4b.
This proposal has been designed in the low-cost 0.18 µm 1 P-6 M CMOS process from UMC. The maximum on-chip integrating capacitance for this technology is around 50 pF, which is the value set for the output capacitor. Transistor sizes in (µm/µm) are M1 = 7.   The external reference current is set to 100 nA introduced through a 1:1 current mirror to the input differential pair, while the bias voltage is generated from another branch, having a total power consumption of 180 nW.
In order to enhance the behavior of the folded OTA, instead of using a classic current mirror, a cascode current mirror would enhance the copy of the current, but using classic cascode current mirrors requires a supply voltage higher than 1.0 V as the number of stacked transistors is too great. That is why a high swing cascode current mirror is chosen with a deviation from its classic topology, which is to connect both gates [35] saving the bias voltage characteristic of the high swing cascode current mirror.
Based on the same G m -C structure of the low pass filter, two different NMOS current mirrors are used to drive the currents to the output stage in order to generate the complementary outputs II and I. The first integrated filter uses a classic current mirror structure as shown in Figure 5b, while the second proposal makes use of an enhanced version of the current mirror (Figure 5c) with a better copy factor of the currents thanks to the cascode current mirrors. The common voltage of the control gate voltages, V CP , is set to 0.3 V for the first proposal while for the second one is set to 0.4 V. For the two of them, the external reference current is set to 100 nA, having a total power consumption of 180 nW with a 1.0 V voltage supply.

Folded-OTA based Low Pass Filter
The transistor sizes of the Folded-based Low Pass Filter in (µm/µm) are M1 = 8/10, M2 = 10/4, M3 = 5/4, M4 = 1/4, MB = 3/4, MB' = 6/4, MN = 2/4, MP = 10/4. With a 1.0 V voltage supply, Vdd, and Vcm set to 0.5 V. The external reference current is set to 100 nA introduced through a 1:1 current mirror to the input differential pair, while the bias voltage is generated from another branch, having a total power consumption of 180 nW.  The simulated analysis of the frequency response, shown in Figure 6, shows, with a 500 nA bias current, a constant unity gain with a tunable frequency that ranges from 2.4 kHz down to 70 mHz for Filter-1, from 2.2 kHz down to 100 mHz for Filter-2 and from 2.8 kHz down to 77 mHz for Filter-3. In order to enhance the behavior of the folded OTA, instead of using a classic current mirror, a cascode current mirror would enhance the copy of the current, but using classic cascode current mirrors requires a supply voltage higher than 1.0 V as the number of stacked transistors is too great. That is why a high swing cascode current mirror is chosen with a deviation from its classic topology, which is to connect both gates [35] saving the bias voltage characteristic of the high swing cascode current mirror.
Based on the same Gm-C structure of the low pass filter, two different NMOS current mirrors are used to drive the currents to the output stage in order to generate the complementary outputs II and I. The first integrated filter uses a classic current mirror structure as shown in Figure 5b, while the second proposal makes use of an enhanced version of the current mirror ( Figure 5c) with a better copy factor of the currents thanks to the cascode current mirrors. The common voltage of the control gate voltages, VCP, is set to 0.3 V for the first proposal while for the second one is set to 0.4 V. For the two of them, the external reference current is set to 100 nA, having a total power consumption of 180 nW with a 1.0 V voltage supply.
The simulated analysis of the frequency response, shown in Figure 6, shows, with a 500 nA bias current, a constant unity gain with a tunable frequency that ranges from 2.4 kHz down to 70 mHz for Filter-1, from 2.2 kHz down to 100 mHz for Filter-2 and from 2.8 kHz down to 77 mHz for Filter-3. To validate the proposed architectures, these three topologies, the Mirrored-based LPF and two LPFs with the same core structure, one with a classic current mirror and another with an enhanced version of the current mirror, biased at a 1.0 V power supply, have been fabricated and experimentally characterized. A low cost UMC 0.18 µm 1 P-6 M CMOS pro-  To validate the proposed architectures, these three topologies, the Mirrored-based LPF and two LPFs with the same core structure, one with a classic current mirror and another with an enhanced version of the current mirror, biased at a 1.0 V power supply, have been fabricated and experimentally characterized. A low cost UMC 0.18 µm 1 P-6 M CMOS process has been used, providing transistors with 1.8 V-3.3 V nominal supplies, MIM (Metal-Insulator-Metal) capacitors (CPOX = 1.0 fF/µm 2 ), and a high resistive polysilicon (HRP) layer (R square = 1039 Ω/sq.) Figure 7 shows the microphotograph of the implemented filters with the total active area expended. As can be seen, most of the area is consumed by the NMOS capacitor, while no difference between the two implemented folded filters in terms of area consumption is appreciated. Insulator-Metal) capacitors (CPOX = 1.0 fF/µm 2 ), and a high resistive polysilicon (HRP) layer (Rsquare = 1039 Ω/sq.) Figure 7 shows the microphotograph of the implemented filters with the total active area expended. As can be seen, most of the area is consumed by the NMOS capacitor, while no difference between the two implemented folded filters in terms of area consumption is appreciated.

Experimental Characterization
The characterization of the filters main static and dynamic parameters has been done with a Printed Circuit Board (PCB) and the measurement setup shown in Figure 8 ( Figure  8a shows the block diagram and Figure 8b a caption of the experimental setup). The active area for Filter-1 (Mirrored) is approximately 77 × 59 µm 2 ; 78 × 55 µm 2 for Filter-2 (Folded with common CM) and 78 × 56 µm 2 for Filter-3 (Folded with enhanced CM), without the integrated capacitor that has been implemented as a MOS capacitor with an area consumption of 0.0092 mm 2 . Thus, total area consumption of 0.0137 mm 2 , 0.0135 mm 2 , and 0.0136 mm 2 was for Filter-1, Filter-2, and Filter-3, respectively, with the main area expense being due to the capacitor. The measurement setup has been automatized to characterize the main static and dynamic parameters. It uses a NI-USB 6008 Data Acquisition Card (DAQ) to select between one of the two integrated filters. Two dual channel Source Measurement Units (SMU) controlled through a GPIB-USB are used as sources to generate the biasing of the

Experimental Characterization
The characterization of the filters main static and dynamic parameters has been done with a Printed Circuit Board (PCB) and the measurement setup shown in Figure 8 (Figure 8a shows the block diagram and Figure 8b a caption of the experimental setup). The active area for Filter-1 (Mirrored) is approximately 77 × 59 µm 2 ; 78 × 55 µm 2 for Filter-2 (Folded with common CM) and 78 × 56 µm 2 for Filter-3 (Folded with enhanced CM), without the integrated capacitor that has been implemented as a MOS capacitor with an area consumption of 0.0092 mm 2 . Thus, total area consumption of 0.0137 mm 2 , 0.0135 mm 2 , and 0.0136 mm 2 was for Filter-1, Filter-2, and Filter-3, respectively, with the main area expense being due to the capacitor.
The measurement setup has been automatized to characterize the main static and dynamic parameters. It uses a NI-USB 6008 Data Acquisition Card (DAQ) to select between one of the two integrated filters. Two dual channel Source Measurement Units (SMU) controlled through a GPIB-USB are used as sources to generate the biasing of the filter, and at the same time to read: the voltage supply, V dd , and the current reference, I As for the readout, the DC output voltage is acquired with a 34401A Agilent 6½ digital multimeter (DMM), while for the dynamic behavior a DPO4104 Tektronix oscilloscope is used to read the transient input and output signals. Figure 8a shows the instrumentation used for the static and the dynamic characterization. Figure 9 presents how the Vgc tuning modifies the Gm value of both outputs when Vgc > 0. The Gm difference at Vgc = 0 between the experimental and the simulated behavior appears because the experimental Gm is an indirect value obtained from the measurement of the output currents. The corresponding cutoff frequency at Vgc = 0 corresponds to the maximum fc achieved, and this maximum cutoff frequency can be extended by using negative values of Vgc, Vgc < 0 or using a smaller value of CLoad. As for the readout, the DC output voltage is acquired with a 34401A Agilent 6 1 2 digital multimeter (DMM), while for the dynamic behavior a DPO4104 Tektronix oscilloscope is used to read the transient input and output signals. Figure 8a shows the instrumentation used for the static and the dynamic characterization. Figure 9 presents how the V gc tuning modifies the G m value of both outputs when V gc > 0. The G m difference at V gc = 0 between the experimental and the simulated behavior appears because the experimental G m is an indirect value obtained from the measurement of the output currents. The corresponding cutoff frequency at V gc = 0 corresponds to the maximum fc achieved, and this maximum cutoff frequency can be extended by using negative values of V gc , V gc < 0 or using a smaller value of C Load .      All the cutoff frequency tuning has been done for Vgc ≥ 0, but it is also possible to extend the fc range for values Vgc < 0 increasing the current going through the output branch and increasing the Gm, or using a smaller value of CLoad. In this case, as the target It is possible to reduce the bias current of Filter-2 and Filter-3 to further reduce the power consumption. This reduction keeps the minimum f c almost constant while the maximum f c is reduced so if only low cutoff frequencies are needed, it is possible to save power. The maximum f c is reduced down to 680 Hz, 152 Hz and 8 Hz for Filter-2 ( Figure 10b) and to 551 Hz, 140.6 Hz and 21.7 Hz for Filter-3 (Figure 10c) for bias currents of 250 nA, 100 nA, and 50 nA, respectively.

Cutoff Frequency Tunable Range
All the cutoff frequency tuning has been done for V gc ≥ 0, but it is also possible to extend the f c range for values V gc < 0 increasing the current going through the output branch and increasing the G m , or using a smaller value of C Load . In this case, as the target frequency range was from 100 mHz to 100 Hz-to cover the frequency ranges of impedance spectroscopy and several biomarkers-an extension of the f c range, was not required. The corresponding power consumption, for both filters, is 960 nW, 480 nW, 180 nW, and 70 nW for bias currents of 500 nA, 250 nA, 100 nA, and 50 nA, respectively.
Post-layout simulation analysis for PT-variation were performed verifying that the sub-Hz to kHz frequencies were achieved thanks to the CS tuning technique, while V dd is assumed to be provided by a voltage regulator and thus kept constant. Experimentally, Figure 11a,b show the variation of the control voltage, V gc , over temperature needed to keep the filters cutoff frequencies constant at two frequencies: 5 Hz and 0.5 Hz respectively. As can be seen, the V gc values needed are still within the operating range-even though Filter-1 shows higher V gc values-to keep the output offset below ±1% and the DC gain error below 0.5 dB, for a temperature range from −40 • C to 100 • C. All the cutoff frequency tuning has been done for Vgc ≥ 0, but it is also possible to extend the fc range for values Vgc < 0 increasing the current going through the output branch and increasing the Gm, or using a smaller value of CLoad. In this case, as the target frequency range was from 100 mHz to 100 Hz-to cover the frequency ranges of impedance spectroscopy and several biomarkers-an extension of the fc range, was not required. The corresponding power consumption, for both filters, is 960 nW, 480 nW, 180 nW, and 70 nW for bias currents of 500 nA, 250 nA, 100 nA, and 50 nA, respectively.
Post-layout simulation analysis for PT-variation were performed verifying that the sub-Hz to kHz frequencies were achieved thanks to the CS tuning technique, while Vdd is assumed to be provided by a voltage regulator and thus kept constant. Experimentally, Figure 11a,b show the variation of the control voltage, Vgc, over temperature needed to keep the filters cutoff frequencies constant at two frequencies: 5 Hz and 0.5 Hz respectively. As can be seen, the Vgc values needed are still within the operating range-even though Filter-1 shows higher Vgc values-to keep the output offset below ±1% and the DC gain error below 0.5 dB, for a temperature range from −40 ˚C to 100 ˚C.

Input Common Mode Range (ICMR)
The input vs output DC voltage characteristic for the filters at the target frequencies previously set 0.5 Hz and 5 Hz is shown in Figure 12. As we increase the bias current, the input-output characteristic is improved.

Input Common Mode Range (ICMR)
The input vs output DC voltage characteristic for the filters at the target frequencies previously set 0.5 Hz and 5 Hz is shown in Figure 12. As we increase the bias current, the input-output characteristic is improved.
Filter-1 (Figure 12a)  current is increased to 500 nA, the linear input range is 310 mV-940 mV (fc = 0.5 Hz) and 350 mV-950 mV (fc = 5 Hz). Finally, for Filter-3 (Figure 12c), the linear input range is 153 mV-851 mV (fc = 0.5 Hz) and 141 mV-870 mV (fc = 5 Hz) for a bias current of 100 nA. While if the bias current is increased to 500 nA, the linear input range is 190 mV-940 mV (fc = 0.5 Hz) and 210 mV-950 mV (fc = 5 Hz) for fc = 5 Hz.  Figure 13 shows the total harmonic distortion (THD) (%) values vs the input voltage (mVpp) for a signal frequency set at fc/5: Figure 13a shows the THD for Filter-1 at 500 nA; Figure 13b,c show the THD for Filter-2 and Filter-3, respectively, and bias currents of 100 nA (straight lines) and 500 nA (dotted lines). Filter-1 has a THD below 1% for input signals up to 280 mVpp and 167 mVpp for fc 5 Hz and 0.5 Hz, respectively. Filter-2 has a THD below 1% for input signals up to 236 mVpp and 300 mVpp for fc 5 Hz and 0.5 Hz, respectively, and a bias current of 100 nA, while for a bias current of 500 nA it goes down to 222 mVpp (fc 5 Hz) and 251 mVpp (fc 0.5 Hz). Filter-3 has a THD below 1% for input signals up to 205 mVpp and 248 mVpp for fc 5 Hz and 0.5 Hz, respectively, and a bias current of 100 nA, while for a bias current of 500 nA it goes down to 190 mVpp (fc 5 Hz) and 222 mVpp (fc 0.5 Hz). 3.3. Linearity (@THD ≤ 1%) Figure 13 shows the total harmonic distortion (THD) (%) values vs the input voltage (mV pp ) for a signal frequency set at f c /5: Figure 13a shows the THD for Filter-1 at 500 nA; Figure 13b,c show the THD for Filter-2 and Filter-3, respectively, and bias currents of 100 nA (straight lines) and 500 nA (dotted lines). Filter-1 has a THD below 1% for input signals up to 280 mV pp and 167 mV pp for f c 5 Hz and 0.5 Hz, respectively. Filter-2 has a THD below 1% for input signals up to 236 mV pp and 300 mV pp for f c 5 Hz and 0.5 Hz, respectively, and a bias current of 100 nA, while for a bias current of 500 nA it goes down to 222 mV pp (f c 5 Hz) and 251 mV pp (f c 0.5 Hz). Filter-3 has a THD below 1% for input signals up to 205 mV pp and 248 mV pp for f c 5 Hz and 0.5 Hz, respectively, and a bias current of 100 nA, while for a bias current of 500 nA it goes down to 190 mV pp (f c 5 Hz) and 222 mV pp (f c 0.5 Hz).

Figure of Merit (FoM)
To compare different proposed structures with similar characteristics, different FoMs can be found in the literature [1,2,22,27]. The main parameters that are employed to define LPFs are power, dynamic range (DR), order of the filter (n), bandwidth (BW), and area consumption. We are going to use the two introduced in [1,27], as they not only take into account all the previous parameters but also normalize the power (NP) and the area (NA) consumption to the technology used, so it is believed it holds stronger comparative constraints. These FoMs are given by:

Figure of Merit (FoM)
To compare different proposed structures with similar characteristics, different FoMs can be found in the literature [1,2,22,27]. The main parameters that are employed to define LPFs are power, dynamic range (DR), order of the filter (n), bandwidth (BW), and area consumption. We are going to use the two introduced in [1,27], as they not only take into account all the previous parameters but also normalize the power (NP) and the area (NA) consumption to the technology used, so it is believed it holds stronger comparative constraints. These FoMs are given by: where NP = Power*[0.5/(V dd − V th )]*(1/V dd ) and NA = area(mm 2 )/Tech(µm 2 ) 2 , with V th = 0.4 V for 0.18 µm CMOS technology. A comparison between the two proposed structures for active filters with previously reported works of similar voltage supply is presented in Table 2. The reported filters present a tuning frequency range that spans over four orders of magnitude with very low power and area consumption while an important enhancement of the dynamic range is achieved. Besides, they are capable of maintaining the target cutoff frequencies over a temperature range from −40 • C to 100 • C. Therefore, compared with previously reported works, the proposals presented in this paper present a wider frequency range with a better performance trade-off in terms of area/pole consumption.