Parametric Fault Diagnosis of Very High-Frequency Circuits Containing Distributed Parameter Transmission Lines

: Parametric fault diagnosis of analog very high-frequency circuits consisting of a distributed parameter transmission line (DPTL) terminated at both ends by lumped one-ports is considered in this paper. The one-ports may include linear passive and active components. The DPTL is a uniform two-conductor line immersed in a homogenous medium, speciﬁed by the per-unit-length (p-u-l) parameters. The proposed method encompasses all aspects of parametric fault diagnosis: detection of the faulty area, location of the fault inside this area, and estimation of its value. It is assumed that only one fault can occur in the circuit. The diagnostic method is based on a measurement test arranged in the AC state. Different approaches are proposed depending on whether the faulty is DPTL or one of the one-ports. An iterative method is modiﬁed to solve various systems of nonlinear equations that arise in the course of the diagnostic process. The diagnostic method can be extended to a broader class of circuits containing several transmission lines. Three numerical examples reveal that the proposed diagnostic method is fast and gives quite accurate ﬁndings.


Introduction
Accurate and fast fault diagnosis of analog circuits, including fault detection, location, and estimation of its value, is an important task in electrical engineering. A huge effort has been made by engineers and researches, over the last few decades, to develop various methods, algorithms, and techniques for testing and diagnosing analog electronic circuits. As a result, many accurate findings have been obtained and reported. Numerous fault diagnosis methods were described in [1][2][3][4]. Nevertheless, some issues in this field remain open, and there is a growing need for their solving.
The various types of faults that may occur in electronic circuits can be divided into local and global defects, as well as parametric (soft) and hard (catastrophic) faults. Local defects concern random regional disturbances within a circuit, whereas global defects concern disturbances that effect entire regions. A fault is said to be parametric if the circuit parameter deviates from the tolerance range, but does not produce any topological changes. Hard faults are shorts and opens. The real short is simulated by a low resistor, whereas the real open is simulated by a high resistor. In Integrated Circuits (ICs), they are classified as spot defects. Important questions of the fault diagnosis are testability analysis and test point selection [5][6][7][8][9]. The parametric fault diagnosis problem has attracted a great deal of attention both in linear circuits [10][11][12][13] and nonlinear circuits [14][15][16][17]. Catastrophic fault diagnosis of bipolar and Complementary Metal Oxide Semiconductor (CMOS) circuits was considered in [18]. Some research studies concentrate on self-testing methods [19]. Numerous works describe artificial intelligence method applications to fault diagnosis [20][21][22].
Traditionally, the research works dealing with fault diagnosis of analog electronic circuits are limited to lumped devices. However, the distribution systems that process high-speed signals play an important role in electronic engineering. Some very highfrequency circuits include distributed parameter transmission lines (DPTLs) [23] terminated by lumped passive or active devices. A method for diagnosing short and open faults in the circuits' transmission lines was developed in [24]. However, the problem of parametric fault diagnosis of this class of circuits is a gap that should be filled.
In this paper, we consider linear analog circuits of very high frequency consisting of cascade-connected Blocks A, B, and C, as shown in Figure 1. Block A includes a uniform two-conductor DPTL immersed in a homogenous medium. It has the length d and is specified by the per-unit-length (p-u-l) parameters [23]. Blocks B and C are lumped oneports, which may contain linear resistors, inductors, capacitors, controlled sources, and independent AC sources. Our goal is to develop a method for parametric fault diagnosis of this class of circuits. The scope of the diagnosis and the main assumptions are as follows. Assume that only one block, A, B, or C, can be faulty. A parametric fault of the DPTL in Block A, considered in this paper, can be caused by, e.g., the change of geometric dimensions (e.g., the distance between the conductors and their radii), a change of a relative dielectric constant, or a change of electrical resistivity. Thus, the defect occurs along the entire line and has a global nature. It influences the p-u-l parameters of the line. The deviations of these parameters from the nominal values evaluate the fault, and all of them should be determined in the course of the diagnostic process. In Block B or C, only one element may be faulty. Diagnosis of these blocks includes the location of the faulty element and the estimation of its value. This paper is organized as follows. The basic methodology of the proposed approach is described in Section 2. Section 3 presents an iterative method utilized by the diagnostic method. Three examples and a discussion of the obtained results are demonstrated in Section 4. Section 5 concludes the paper.

Parametric Fault Diagnosis Method
To diagnose a circuit belonging to the class defined in Section 1, a measurement test is arranged in the AC state. The phasors V(0) and V(d) of the input and output voltages of the DPTL are measured at one frequency while running the test.

Detection of the Faulty Block
The preliminary step of fault diagnosis is to detect the faulty block or to state that the circuit is fault-free. For this purpose, each of the blocks with nominal parameters is considered separately. In the cases of Blocks B and C, the currents I B and I C are determined by the analysis of the blocks driven by the voltage sources V(0) and V(d), respectively. The obtained phasors of these currents are denoted byĨ B andĨ C . Since V(0) and V(d) have been measured in the real circuit, which can be faulty,Ĩ B orĨ C is the actual current in the circuit if the corresponding Block B or C is fault-free. Next, we consider Block A including the DPTL driven at the left end by V(0) and at the right end by V(d). The line is described by the system of equations: where γ = (r + jωl) (g + jωc), with Re γ ≥ 0, Im γ > 0, is the propagation constant, with Re Z C ≥ 0, is the characteristic impedance, and the p-u-l parameters, r, l, g, c have nominal values. We solve (1) for I(0) and I(d) and denote the solutions bỹ I(0) andĨ(d). They are the actual currents in the circuit if the DPTL is fault-free.
The fault detection and identification of the faulty block is based on Table 1, where I(0), I(d), I B , and I C denote the actual currents in the circuit. The table is created on the assumption, made in Section 1, that only one block, A, B, or C, can be faulty.

Diagnosis of the Faulty Block A
If Block A has been detected as faulty (Ĩ B = −Ĩ(0),Ĩ C =Ĩ(d)), we find its actual p-u-l parameters using the two-step procedure.

Step 1
Let us substitute I(0) = −Ĩ B , I(d) =Ĩ C and the measurement voltages V(0), V(d) in (1) and express γ and Z C in the rectangular form: γ = α + jβ, Z C = R C + jX C . As a result, we obtain a system of two nonlinear complex equations in four real unknown variables: α, β, R C , X C . This system has the form g(x) = 0, where x = [α β R C X C ] T , g(x) = [g 1 (x) g 2 (x)] T , and T denotes transposition. It is solved using the iterative method described in Section 3, where two iteration Formulas (8) and (9) are presented. In the discussed case, each of them consists of four individual real linear equations in four unknown real variables. If (8) generates the sequence that is not convergent, the modified iteration Formula (9) is applied.

Step 2
Having α, β, R C , and X C , the p-u-l parameters of the DPTL are determined as follows. On the basis of equations γ = α + jβ and γ = (r + jωl)(g + jωc), we write: Hence, we arrive at two real equations with four real variables r, l, g, and c: Similarly, using Z C = R C + jX C and Z C = r+jωl g+jωc gives the equality: leading to two other real equations in four real variables r, l, g, and c: In the systems of Equations (3) and (5), the unknown variables are the p-u-l parameters, r, l, g, and c. Since they have orders that differ significantly one from the other, we scale them using the factors s 1 = 1, s 2 = 10 −4 , s 3 = 10 −7 , and s 4 = 10 −11 . Combining (3) and (5) and substituting r = s 1 x 1 , g = s 2 x 2 , l = s 3 x 3 , and c = s 4 x 4 yield: Let us denote (6) . . x 4 ] T and solve it using the iterative method described in Section 3. Since g(x) is a real function, D(x) is a real 4 × 4 matrix and B x (k) = D x (k) . We apply the iteration formula (8), which in this case represents a system of four real linear equations in four unknown real variables. If the generated sequence does not converge, the modified iteration formula (9) is used.

Diagnosis of the Faulty Block B
If the preliminary step of the diagnosis states that Block B is faulty (Ĩ B = −Ĩ(0), I C =Ĩ(d)), then, according to the assumption made in Section 1, one of the elements of this block is faulty. We wish to locate this element and estimate its value. For this purpose, we consider Block B driven by the current source I = −Ĩ(0), as shown in Figure 2.
Since the input voltage V is equal to the measured voltage V(0), both I and V are given. Let us describe the circuit depicted in Figure 2 using the node method, leading to a system of N complex equations. Because V is one of the node voltages, the number of unknown variables is N − 1. We present them in rectangular form obtaining 2N − 2 real variables. Let us increase the number of variables to 2N − 1 by adding one of the circuit parameters considered as potentially faulty. As a result, we obtain a system of N complex equations in 2N − 1 real variables, which can be presented in the compact form g(x) = 0.
To solve them, we apply the method described in Section 3 where n = N, m = 2N − 1 and B x (k) is a 2N × (2N − 1) matrix. The iteration Formula (8) consists of 2N − 1 real equations in 2N − 1 real unknown variables. They include 2N − 2 real and imaginary parts of the node voltage phasors and one unknown parameter, whereas the other parameters have nominal values. If the method based on the iteration Formula (8) does not converge, the modified Formula (9) is used. We repeat this approach for each of the parameters in Block B considered as potentially faulty. Every time, the solution includes one unknown parameter and 2N − 2 redundant real variables. When the chosen parameter is faulty, we obtain the correct result. Otherwise, the method can give non-realistic solutions or not be convergent. Sometimes, the method may find a virtual solution. Note 1. If Block B contains elements not acceptable by the node method, the modified node method is applied.
Note 2. Diagnosis of Block C is carried out analogously.

Standard Method
Let us consider a system of n nonlinear complex equations in m unknown real variables presented in a compact form: To solve this equation, the iterative method developed in [24] can be used. This iteration formula: · · · · · · · · · · · · · · · · · · · · · ∂g n ∂x 1 Matrix B x (k) has order 2n × m; matrix D x (k) has order n × m; and b x (k) is an m × 1 vector. As a consequence, B T x (k) B x (k) is a real square matrix of order m × m. If the iteration process specified by (8) converges, it is terminated when max where ε x and ε f are convergence tolerances, and x (k+1) is considered as an approximate solution. If the method does not meet the convergence tolerances in a preset maximum number of iterations M it , it fails.

Modified Method
The difficulty of solving (7) arises if the standard method does not converge. In such a case, we modify it as described in the sequel. (k) and positive semidefinite because for any real Thus, its determinant is greater than or equal to zero. When det B T x (k) B x (k) = 0, the iterative method fails. Even if the determinant is close to zero, the method may not converge. To get rid of this drawback, we propose a new iteration formula as follows: where ξ and µ are positive constants selected based on numerical experiments. Since ξ e −µ k 1 is a diagonal matrix with identical positive elements ξ e −µ k on the main diagonal, the matrix B T x (k) B x (k) + ξ e −µk 1 is positive definite for all k = 1, 2, . . ., because for any real m × 1 vector y = 0: Then, its determinant is greater than zero, and Equation (9) can be uniquely solved at any iteration. As k increases, the diagonal elements of the matrix ξ e −µ k 1 decrease and tend to zero for large values of k. As a consequence, Equation (9) approaches Equation (8).

Illustrative Examples
The diagnostic method proposed in Sections 2 and 3 was implemented in the MATLAB environment, and the calculations were performed on a PC with an Intel Core i7-6700 processor. To show the efficiency of the method, three numerical examples are presented. Whenever the iterative method described in Section 3 is employed, the nominal values of the fault-free variables are chosen to form the initial guess. In the circuit of Figure 3, we diagnosed 5 faults of Block A, 17 faults of Block B, and 3 faults of Block C. In all these cases, the procedure for detecting the faulty block, described in Section 2.1, gave the correct outcomes.  The findings of the diagnoses of five faults of Block A are placed in Table 2. Every time, all the p-u-l parameters of the line are calculated. The relative error: of the 20 parameter values presented in this table is as follows. In 15 cases (75%), ε r < 1%; in three cases (15%), 1% < ε r < 3%; in two cases, (10%), 10% < ε r < 18%. To obtain the results summarized in Table 2, the iterative method, based on the iteration Formula (8), was used. The number of iterations for finding α, β, R C , and X C (Step 1) ranges from six to 22 and for finding the p-u-l parameters (Step 2) is four in all the cases. Tables 3-6 present 17 cases of the faults of Block B caused by 5 faults of the resistor RB1 (Table 3), 4 faults of the resistor RB2 (Table 4), 4 faults of the resistor RB3 (Table 5), and 4 faults of the capacitor CB1 ( Table 6).
The outcomes summarized in Table 3 are quite accurate; ε r does not exceed 0.7%. To diagnose Faults 1 and 2, the proposed iteration Formula (9) was used because the sequences generated by the iteration Formula (8) were not convergent. In the case of Fault 4, the method finds correctly the faulty resistor RB1 = 89.7956 Ω, inserted in the table, and a virtual fault RB3 = 421.7773 Ω. The number of iterations needed to determine each parameter value presented in the table varies from five to 13, and the CPU time does not exceed 0.33 s. The findings inserted in Table 4 are very accurate; ε r is smaller than 0.18%. The number of iterations ranges from five to eight, and the CPU time does not exceed 0.32 s. The relative error ε r of the resistor values posted in Table 5 is less than 0.7%; the number of iterations varies from five to six; and the CPU time does not exceed 0.36 s. In the cases of Faults 2 and 3 placed in this table, the method gives the correct faulty resistors and virtual ones. The virtual fault is RB1 = 93.8013 Ω in Case 2 and RB1 = 60.6634 Ω in Case 3. However, if the accuracy of the measurement in the diagnostic test course is increased (0.01 mV for the amplitude and 0.001 • for the phase), the method provides only the correct findings. Unfortunately, it is difficult to ensure such high accuracy in real conditions. The relative error ε r of the outcomes placed in Table 6 is less than 2.8%; the number of iterations ranges from 4-6; and the CPU time does not exceed 0.063 s.  Table 7 contains the results of the diagnosis of the faulty Block C. They were obtained performing 4-5 iterations and are burdened with very small relative error, ε r < 0.2%. The CPU time does not exceed 0.095 s.

Example 2
Let us consider the circuit, including the 150 MHz elliptical low-pass filter and the DPTL terminated by a resistor, shown in Figure  We performed 39 diagnoses including 4 faults of Block A, 30 faults of Block B, and 5 faults of Block C. In all cases, the procedure for detecting the faulty block, described in Section 2.1, gave the correct results.
The outcomes of the diagnoses of four faults of Block A are summarized in Table 8. In 11 cases (68.7%), the relative error ε r of the results provided by the method was less than 1%; in the remaining five cases (31.3%) it is greater than 1%, but smaller than 2.2%. The number of iterations for finding α, β, R C , and X C (Step 1) ranges from five to six and for finding the p-u-l parameters (Step 2) from four to five. In Block B, all the elements can be diagnosed except CB1 and CB2, because the sensitivities of the voltage of this block with respect to these elements are very small. Consequently, for realistic measurement accuracy, variations of these elements have a very small influence on the voltage. All the other elements of this block, RB1, CB3, CB4, CB5, LB1, and LB2, were diagnosed. Tables 9-14 present 30 cases of the faults including five faults of the resistor RB1 and five faults of each of the capacitors CB3, CB4, and CB5 and the inductors LB1 and LB2.
The outcomes placed in Table 9 are very accurate, and ε r < 0.01%. The number of iterations ranges from four to six, and the CPU time of each of the diagnoses does not exceed 0.1 s. To diagnose Fault 1, the proposed iteration Formula (9) was used because the sequence generated by the iteration Formula (8) was not convergent. The findings presented in Tables 10 and 11 are very accurate (ε r < 0.08%); the number of iterations varies from four to five, and CPU time does not exceed 0.21 s. The maximum relative error of the results included in Table 12 is ε r < 0.33%, and the number of iterations in all the cases is two. The CPU time is 0.16 s. The outcomes summarized in Tables 13 and 14 are very accurate; ε r < 0.04%. The number of iterations ranges from four to 14. The CPU time is 0.16 s. The relative error ε r of the resistor values inserted in Table 15 is less than 0.02%. The number of iterations varies from five to nine. The CPU time is 0.19 s. To diagnose Fault 1, the proposed iteration formula (9) was used because the sequence generated by the iteration formula (8) was not convergent.  The circuit of Figure 6 has a more complex structure than that shown in Figure 1. It consists of three blocks, A1, A2, and A3, containing DPTLs and four blocks, B, C, D, and K, including lumped elements. Similarly, as in Section 1, we assume that only one block can be faulty and only one element of the lumped block can be defective. In the blocks containing DPTLs, all the p-u-l parameters may deviate from nominal values due to a fault, and all of them must be diagnosed. The diagnostic test of the circuit requires the input and output voltages of each DPTL. The fault detection rule presented in Section 2.1 for three-block circuits can be directly extended to the circuit of Figure 6. In particular, the three-port Block K is faulty ifĨ K =Ĩ (2) (0) , andĨ  In the circuit of Figure 6, we diagnosed three faults of each of Blocks A1, A2, A3, B, C, and D and nine faults of Block K. In all these cases, the procedure for detecting a faulty block gave correct outcomes.
Tables 17 and 18 present the results of the diagnoses of two faults in each of Blocks B, C, and D and six faults in Block K. To diagnose Block K, which is a three-port circuit, an obvious modification of the procedure described in Section 2.3 is needed. The results are very accurate; the number of iterations ranges from 5-15; and the CPU time does not exceed 0.4 s. In three cases, corresponding to RB1 = 30 Ω, RK1 = 10 Ω, and RK3 = 2 Ω, the iteration formula (9) was used because the iteration sequences generated by formula (8) were not convergent.

Conclusions
Parametric fault diagnosis of analog circuits of very high frequency consisting of a distributed parameter transmission line, as well as lumped linear passive and active elements has not been discussed in the literature till now. This paper deals with the problem and proposes a method that covers all aspects of the fault diagnosis. First, the faulty area is determined, and then, the faulty component inside this area is located and its value estimated. There are three areas in the circuit, called blocks, including the DPTL (Block A) and two lumped circuits terminating the line (Blocks B and C). It is assumed that only one block may be faulty and only one component of the faulty Block B or C can be defective. The blocks may include IC devices if they can be represented by realistic linear models. The example is the operational amplifier circuit designed so that the operational amplifiers operate in the linear regions. In the DPTL, all the p-u-l parameters can deviate from their nominal values, leading to the fault of the line. This concept can be directly extended to the circuits, including more than one DPTL and more than three blocks, as illustrated in Example 3.
The proposed diagnostic method employs voltage measurements from two terminals of the DPTL, and no current measurements are required. It takes full advantage of the measured amplitude and phase at one frequency only. Numerical examples reveal that the method successfully determines the faulty block and the faulty element inside this block. The obtained values of the faulty elements are quite accurate. The iterative method utilized by the diagnostic method is effective, fast, and does not require great computing power. The proposed iteration Formula (9) is useful when the standard Formula (8) fails. In the numerical examples where such a situation occurred, it helps to find the solution. The method is limited to single fault diagnosis, which occurs most frequently in analog circuits. The temperature changes of the parameters are neglected because the temperature coefficients of resistance and capacitance of the elements used in the circuits of very high frequency have low values.
A drawback of the proposed diagnostic method is that, sometimes, it gives the actual fault accompanied by a virtual one. In 2.2% of the diagnosed cases, the method failed.