Analysis of a Wide Voltage Hybrid Soft Switching Converter

Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin 640, Taiwan; m10812048@yuntech.edu.tw * Correspondence: linbr@yuntech.edu.tw


Introduction
For past years, clean and sustainable energy has received increased attention to reduce greenhouse gas emissions and fossil energy demand. Photovoltaic (PV) solar cell, fuel cell stacks, and DC wind power are attractive sustainable energy sources as they are costeffective [1][2][3][4]. The main drawback of these sustainable energy sources is that the output DC or AC voltage is not constant. To solve this problem, the soft switching high-frequency DC-DC converters have been developed by using switching frequency modulation [5,6], pulsewidth modulation (PWM) [7][8][9][10], active clamp PWM [11,12], and asymmetric PWM [13,14] schemes. The main drawbacks of active clamp PWM and asymmetric PWM schemes are the unbalance current and voltage stresses on the rectifier diodes. In resonant converters, the operating switching frequency depends on the load power and input voltage so that the load voltage is controlled by frequency modulation. However, the wide output-voltage variation of sustainable energy sources will result in wide switching frequency deviation in resonant converters. In PWM scheme, the duty ratio (or duty cycle) on active devices or input leg voltage of PWM converter depends on input voltage. Thus, the duty cycle of PWM converter can be regulated to countract input voltage variation. Generally, the maximum (minimum) effective duty ratio d eff,max (d eff,min ) is related to minimum (maximum) input voltage V in,min (V in,max ). Due to duty loss problem at the freewheeling state on conventional phase-shift PWM converter, the effective duty ratio d eff is usually designed to be greater than 0.15 and less than 0.45. Hence, input voltage variation will be limited at V in,max /V in,min = d eff,max /d eff,min < 3 on conventional phase-shift PWM operation. As the voltage deviation from PV panels and DC wind generator outputs may be greater than 3, the cascaded or parallel-connected circuit structures [15][16][17] have been developed to overcome this problem. However, the low efficiency is the main problem of cascaded PWM converters. In serial-and parallel-connected circuit topology with wide voltage operation in [15,16], the component counts, high circulating current, and the complicated control algorithm are the main disadvantages. However, the maximum voltage deviation in [15][16][17] is still less than 4 (V in,max /V in,min < 4). The DC converters with more than 5 (V in,ma /V in,min > 5) wide voltage capability are normally demanded for renewable energy.
A hybrid converter with a three-leg phase-shift PWM circuit and a LLC circuit are presented and realized to have benefits of wide load range of zero voltage switching (ZVS), less circulating current loss, and wide input voltage capability (120-600 V). On the basis of input voltage, two sub-circuits are selected to operate in order to overcome wide inputvoltage deviation. One AC switch is adopted to select one of two sub-circuits under low or high input-voltage condition. Therefore, a 5:1 (V in,max = 5 V in,min ) wide input voltage hybrid converter is achieved. The phase-shift PWM approach is used to control output voltage. Power devices at the leading leg can be easily turned on at ZVS because the output inductor energy is used to release energy stored on output capacitor of active devices. The hard switching disadvantage of lagging-leg active devices in conventional full bridge converter is overcome by connecting a LLC resonant circuit to the lagging-leg active devices. Therefore, the lagging-leg active devices are turned on at ZVS. In circuit implementation, a Schmitt comparator with a ±30 V hysteresis range is adopted to select the appropriate sub-circuit under high or low voltage input operation. The control scheme can be easily implemented by using logic gates, comparator, and phase-shift PWM integrated circuit. The benefits of the studied hybrid zero-voltage switching (ZVS) converter are confirmed by an 800 W experimental prototype.

Structure of the Proposed Converter
The converter diagram of conventional full bridge PWM converter is given in Figure 1a. The main benefit of full bridge PWM converter is ZVS operation on S 1 and S 2 (leading-leg switches). However, the full bridge PWM converter has several drawbacks. such as hard switching operation on S 3 and S 4 (lagging-leg switches) and high primary current loss at the freewheeling state v ab = 0 when S 1 and S 3 are ON or S 2 and S 4 are ON. Therefore, serious switching losses can be generated at the lagging leg and high conduction losses will be generated on the primary side under low duty cycle condition. To overcome hard switching loss, a LLC resonant circuit (L r T 2 , C r , D 3 , D 4 , C LLC and D 5 ) remark in red (Figure 1b) is adopted and connected to the lagging-leg switches. As LLC resonant circuit is operated at constant frequency (f sw = f r resonant frequency of L r and C r ), active devices S 3 and S 4 can achieve ZVS operation. The other drawback of conventional PWM converter in Figure 1a is the serious circulating current loss at the freewheeling state v ab = 0. To solve this problem, diode D 5 is used to connect two voltage terminals V o,LLC and V R on the secondary side. Therefore, the secondary rectified voltage V R is positive in Figure 1b instead of V R = 0 in Figure 1a during the freewheeling interval. During the forward power flow from V in to V o , the primary-side leg voltage |v ab | ≈ V in and the secondary rectified voltage V R ≈ V in n s /n p1 > V o,LLC . Thus, diode D 5 is reverse biased. Diode D 5 is forward biased during the freewheeling interval (v ab = 0). Because D 5 is conducting, the energy on C LLC is transferred to V o at the freewheeling state. In the freewheeling interval, the rectified voltage V R = V o,LLC > 0, the primary inductor voltage V LR = −(n p1 /n s1 )V o,LLC, and the primary current i LR are decreased. For some renewable energy power conversions for solar power or wind power applications, the DC converters with wide voltage operation capability are needed in order to counteract wide input voltage variation. Conventional full bridge PWM converter can operate well with narrow voltage variation, such as V in,max /V in,min < 3. For more wide voltage deviation, the conventional full bridge PWM circuit cannot achieve this demand. To achieve wide voltage deviation request, three leg PWM converter is adopted and shown in Figure 1c. Comparing the circuit diagrams in Figure 1b,c, it can be noted, one more switch leg with components S 1 , S 2, and Q remark in blue is adopted in the presented wide voltage deviation, the conventional full bridge PWM circuit cannot achieve this demand. To achieve wide voltage deviation request, three leg PWM converter is adopted and shown in Figure 1c. Comparing the circuit diagrams in Figure 1b,c, it can be noted, one more switch leg with components S1, S2, and Q remark in blue is adopted in the presented circuit. The transformer T1 has four winding turns np1, np1, ns1, and ns1. Switch Q is used to control turns ratio of T1 under the different input voltage regions. When 120 V ≤ Vin < 270 V (low voltage region, Vin,L), the proposed converter with high voltage gain is requested to keep load voltage constant. Therefore, active devices Q, S1, and S2 are OFF, as shown in Figure 2a. Only S3-S6 are activated to regulate Vo. Circuit S3-S6, T1, LR, D1, D2, and Lo are activated as the full bridge phase-shift PWM converter. The leading-leg active devices S3 and S4 can easily turn on at ZVS operation. The turns-ratio of T1 is np1/ns1 under low voltage input range. Circuit structure with components S5, S6, T2, Lr, Cr, D3, D4, and CLLC is operated as the LLC series resonant converter. Due to the resonant behavior, the lagging leg active devices S5 and S6 are turned on at ZVS. When 270 V ≤ Vin < 600 V (high voltage region, Vin,H), Q is ON and S3 and S4 are OFF, as shown in Figure 2b. S1, S2, S5, and S6 are activated to control load voltage Vo. Circuit structure with components S1, S2, S5, S6, T1, LR, D1, D2, and Lo are activated as the full bridge phase-shift PWM circuit. The When 120 V ≤ V in < 270 V (low voltage region, V in,L ), the proposed converter with high voltage gain is requested to keep load voltage constant. Therefore, active devices Q, S 1, and S 2 are OFF, as shown in Figure 2a. Only S 3 -S 6 are activated to regulate V o . Circuit S 3 -S 6 , T 1 , L R , D 1 , D 2, and L o are activated as the full bridge phase-shift PWM converter. The leading-leg active devices S 3 and S 4 can easily turn on at ZVS operation. The turns-ratio of T 1 is n p1 /n s1 under low voltage input range. Circuit structure with components S 5 , S 6 , T 2 , L r , C r , D 3 , D 4, and C LLC is operated as the LLC series resonant converter. Due to the resonant behavior, the lagging leg active devices S 5 and S 6 are turned on at ZVS. When 270 V ≤ V in < 600 V (high voltage region, V in,H ), Q is ON and S 3 and S 4 are OFF, as shown in Figure 2b. S 1 , S 2 , S 5, and S 6 are activated to control load voltage V o . Circuit structure with components S 1 , S 2 , S 5 , S 6 , T 1 , L R , D 1 , D 2, and L o are activated as the full bridge phase-shift PWM circuit. The leading-leg active devices S 1 and S 2 turn on at ZVS. The turns-ratio of T 1 in Figure 2b is 2n p1 /n s1 under high voltage input range. Due to LLC circuit connected to the lagging leg, S 5 and S 6 are turned on at ZVS. From the previous discussion, it is clear that the presented hybrid converter has soft switching operation, wide input-voltage operation (V in,max /V in,min = 5), and less primary current at the freewheeling state.

Principle of Operation
If Vin is in the low voltage region (Vin,L = 120-270 V), active devices Q, S1, and S2 are all turned off. Power switches S3-S6 and passive components T1, LR, D1, D2, and Lo are operated with PWM approach to control load voltage Vo. LLC resonant circuit with components S5, S6, T2, Lr, Cr, D3, D4, and CLLC is operated with fixed switching frequency to achieve ZVS operation of S5 and S6. It is assumed the inductances Lm1 = Lm2 >> LR and capacitances CS1 = ... = CS6 = Coss. The PWM waveforms under the low input-voltage region are given in Figure 3a. One can observe that there are six states (Figure 3b-g) in each half switching cycle. The PWM waveforms are symmetrical in every half switching period. To simplify the system analysis, only the operating states in the first half switching period are stated in this section.
State 1 [t0 ≤ t < t1]: In state 1, S3 and S6 are in the on-state and leg voltage vbc = Vin. LLC converter is controlled at the resonant frequency. As S6 is in the on-state, iLr decreases and iLr < iLm,T2. The secondary diodes D1 and D4 are forward biased. The drain voltages vCS4 =

Principle of Operation
If V in is in the low voltage region (V in,L = 120-270 V), active devices Q, S 1, and S 2 are all turned off. Power switches S 3 -S 6 and passive components T 1 , L R , D 1 , D 2, and L o are operated with PWM approach to control load voltage V o . LLC resonant circuit with components S 5 , S 6 , T 2 , L r , C r , D 3 , D 4, and C LLC is operated with fixed switching frequency to achieve ZVS operation of S 5 and S 6 . It is assumed the inductances L m1 = L m2 >> L R and capacitances C S1 = . . . = C S6 = C oss . The PWM waveforms under the low input-voltage region are given in Figure 3a. One can observe that there are six states (Figure 3b-g) in each half switching cycle. The PWM waveforms are symmetrical in every half switching period. To simplify the system analysis, only the operating states in the first half switching period are stated in this section.
State 1 [t 0 ≤ t < t 1 ]: In state 1, S 3 and S 6 are in the on-state and leg voltage v bc = V in . LLC converter is controlled at the resonant frequency. As S 6 is in the on-state, i Lr decreases and i Lr < i Lm,T2 . The secondary diodes D 1 and D 4 are forward biased. The drain voltages Electronics 2021, 10, 473 The currents i Lo and i LR are expressed in Equations (1) and (2): Electronics 2021, 10, x FOR PEER REVIEW 6 of 18 state 6, the diode current iD2 is equal to iLo so that D5 becomes reverse biased and the primary current iLR ≈ − ns1iLo/np1. The time duration of state 6 is obtained and expressed in Equation (7): Since D5 is forward biased, the duty loss in state 6 is calculated in Equation (8): In this state, vLo = Vo,LLC − Vo < 0 so that iLo decreases. At time t6, the converter goes to the next half switching period.   When Vin is in the high voltage region (Vin,L = 270 V-600 V), Q is turned on and S3 and S4 are turned off. Switches S1, S2, S5, and S6 and passive components T1, LR, D1, D2, and Lo are controlled by phase shift PWM scheme. Components S5, S6, T2, Lr, Cr, D3, D4, and CLLC are operated as the LLC resonant circuit to have ZVS operation of S5 and S6. The turns ratio of full bridge converter under the high input-voltage region is 2np1/ns1 in Figure 2b. Figure  4a shows PWM waveforms for high voltage input region. Figure 4b-g provides the equivalent state circuits for first half switching period.
In this state, switches S1 and S6 are ON and the leg voltage vac = Vin. LLC converter (S6, Lr, T2, Cr, D4, and CLLC) is operated at the resonant frequency. On the secondary side, D1 and D4 are conducting. The drain voltages vCS2 = vCS5 = Vin and the diode voltage stresses vD2 ≈ Vinns1/np1 and vD3 ≈ 2Vo,LLC. The inductor currents iLo and iLR are increased and iLr is decreased in this state.
State 2 [t1 ≤ t < t2]: At t1, switch S1 is turned off. Owing to iLR(t1) > 0, iLR discharges CS2. If the inductor energy , then CS4 can be completely discharged to zero voltage. State 3 [t2 ≤ t < t3]: At t2, vCS2 = 0. Since iLR(t2) > 0, DS2 conducts and S2 is turned on at ZVS. In this state, the leg voltage vac = 0 so that D5 is forward biased. Therefore, the rectified voltage VR = Vo,LLC, vLR = −2 × np1Vo,LLC/ns1 < 0 and vLo = Vo,LLC -Vo < 0. The inductor currents iLr, iLo, and iLR are all decreased in state 3. If the primary currents iLR or iD1 can be declined State 2 [t 1 ≤ t < t 2 ]: At t 1 , S 3 turns off. As i LR (t 1 ) > 0, C S4 is discharged by i LR after time t 1 . If the inductor energy [L R + n p1 /n s1 ) is decreased and will be equal to 0 at t 2 . The discharged time of C S4 is expressed as: LLC converter is still controlled at the resonant mode to distribute power from V in to : At t 2 , v CS4 is decreased and equal to zero voltage. Since i LR (t 2 ) > 0, D S4 is conducting and S 4 can turn on to have soft switching operation. Due to v bc = 0, the diode D 5 becomes forward biased and the rectified voltage V R is clamped at V o,LLC . Therefore, the inductor voltages v LR = −n p1 V o,LLC /n s1 < 0 and v Lo = V o,LLC − V o < 0. i LR and i Lo are decreased in this state.
However, the conventional full bridge converter has v LR ≈ 0 and i LR ≈ constant in this state (freewheeling state). Therefore, the conventional full bridge PWM converter has more circulating current loss in this state. In Equation (5), one can observe the primary current i LR is decreased at freewheeling state in the proposed converter. If the time interval at freewheeling state is long enough, the diode current i D1 or the primary current i LR can be declined to zero.
The time ∆t iLp=0 is related to L R , V o,LLC, and I o . Thus, more freewheeling time duration is required at full load to eliminate the circulating current.
State 4 [t 3 ≤ t < t 4 ]: At t 3 , i D1 = 0 and i LR ≈ 0. The diode current i D5 = i Lo . Thus, the circulating current of i LR is almost removed at freewheeling state (v bc = 0). The inductor State 5 [t 4 ≤ t < t 5 ]: S 6 is turned off at t 4 . Since i Lr (t 4 ) − i LR (t 4 ) is negative, C S5 will be discharged. In LLC converter, D 3 becomes forward biased as i Lr > i Lm,T2 after time t 4 . C S5 will be discharged to zero voltage at t 5 .
State 6 [t 5 ≤ t < t 6 ]: State 6 starts at time t 5 when v CS5 is declined to zero. Due to i LR (t 5 ) − i Lr (t 5 ) > 0, D S5 becomes forward biased. Then, S 5 can be turned on after time t 5 to realize soft switching operation. In this state, v bc = −V in and D 2 becomes forward biased. Owing to i D2 (t 5 ) < i Lo (t 5 ), D 5 is conducting and V R = V o,LLC . The inductor voltage v LR ≈ n p1 V o,LLC /n s1 − V in < 0 and the primary current i LR decreases in this state. At the end of state 6, the diode current i D2 is equal to i Lo so that D 5 becomes reverse biased and the primary current i LR ≈ − n s1 i Lo /n p1 . The time duration of state 6 is obtained and expressed in Equation (7): Since D 5 is forward biased, the duty loss in state 6 is calculated in Equation (8): In this state, v Lo = V o,LLC − V o < 0 so that i Lo decreases. At time t 6 , the converter goes to the next half switching period.
When V in is in the high voltage region (V in,L = 270 V-600 V), Q is turned on and S 3 and S 4 are turned off. Switches S 1 , S 2 , S 5, and S 6 and passive components T 1 , L R , D 1 , D 2, and L o are controlled by phase shift PWM scheme. Components S 5 , S 6 , T 2 , L r , C r , D 3 , D 4, and C LLC are operated as the LLC resonant circuit to have ZVS operation of S 5 and S 6 . The turns ratio of full bridge converter under the high input-voltage region is 2n p1 /n s1 in Figure 2b. Figure 4a shows PWM waveforms for high voltage input region. Figure 4b-g provides the equivalent state circuits for first half switching period.
State 1 [t 0 ≤ t < t 1 ]: In this state, switches S 1 and S 6 are ON and the leg voltage v ac = V in . LLC converter (S 6 , L r , T 2 , C r , D 4, and C LLC ) is operated at the resonant frequency. On the secondary side, D 1 and D 4 are conducting. The drain voltages v CS2 = v CS5 = V in and the diode voltage stresses v D2 ≈ V in n s1 /n p1 and v D3 ≈ 2V o,LLC . The inductor currents i Lo and i LR are increased and i Lr is decreased in this state.
State 2 [t 1 ≤ t < t 2 ]: At t 1 , switch S 1 is turned off. Owing to i LR (t 1 ) > 0, i LR discharges C S2 . If the inductor energy [L R + (2 n p1 /n s1 ) 2 L o ]i 2 LR (t 1 ) > 2C oss V 2 in , then C S4 can be completely discharged to zero voltage. State 3 [t 2 ≤ t < t 3 ]: At t 2 , v CS2 = 0. Since i LR (t 2 ) > 0, D S2 conducts and S 2 is turned on at ZVS. In this state, the leg voltage v ac = 0 so that D 5 is forward biased. Therefore, the rectified voltage V R = V o,LLC , v LR = −2 × n p1 V o,LLC /n s1 < 0 and v Lo = V o,LLC -V o < 0. The inductor currents i Lr , i Lo, and i LR are all decreased in state 3. If the primary currents i LR or i D1 can be declined to zero, then the necessary time interval of the freewheeling state at the high input-voltage region is derived as: If i D1 = 0 at t 3 , then the circuit operation goes to state 4. If i D1 is not equal to zero at the end of the freewheeling state, then the circuit goes to state 5. State 4 [t 3 ≤ t < t 4 ]: At t 3 , i D1 = 0. One can observe i D5 = i Lo and the primary current i LR is approximately equal to zero when v ac = 0 (freewheeling state). Since D 5 is conducting, power is delivered to V o through LLC resonant converter in state 4.
State 5 [t 4 ≤ t < t 5 ]: At t 4 , S 6 turns off. Owing to i LR (t 4 ) − i Lr (t 4 ) > 0, C S5 will be discharged. In LLC circuit, D 3 is conducting. At t 5 , v CS5 is decreased to zero voltage. State 6 [t 5 ≤ t < t 6 ]: At t 5 , v CS5 = 0. Owing to i LR (t 5 ) − i Lr (t 5 ) > 0, D S5 is conducting. Thus, S 5 is turned on at ZVS. In state 6, v ac = −V in and D 2 is forward biased. Due to i D2 (t 5 ) < i Lo (t 5 ), D 5 is still conducting and V R = V o,LLC . The primary inductor voltage v LR ≈ 2n p1 V o,LLC /n s1 − V in < 0 and i LR decreases. At the end of state 6, the diode current i D2 = i Lo so that D 5 is conducting. The duty loss at state 6 under the high input-voltage region is obtained as: At time t 6 , the converter goes to the next half switching period.
to zero, then the necessary time interval of the freewheeling state at the high input-voltage region is derived as: If iD1 = 0 at t3, then the circuit operation goes to state 4. If iD1 is not equal to zero at the end of the freewheeling state, then the circuit goes to state 5.
State 4 [t3 ≤ t < t4]: At t3, iD1 = 0. One can observe iD5 = iLo and the primary current iLR is approximately equal to zero when vac = 0 (freewheeling state). Since D5 is conducting, power is delivered to Vo through LLC resonant converter in state 4.

Circuit Characteristics
A three-leg full bridge circuit and a LLC resonant circuit are included in the studied converter. Both PWM circuit and LLC circuit will achieve power transfer from Vin to Vo. LLC circuit is controlled at constant frequency. Thus, the secondary-side voltage Vo,LLC is calculated in (11): At the freewheeling state, the primary-side leg voltage vac or vbc is zero and diode D5 is forward biased. Thus, the rectifier terminal voltage VR = Vo,LLC. The primary inductor voltage vLR= −np1Vo,LLC/ns1 (low input-voltage region) or vLR= −2 × np1Vo,LLC/ns1 (high input-

Circuit Characteristics
A three-leg full bridge circuit and a LLC resonant circuit are included in the studied converter. Both PWM circuit and LLC circuit will achieve power transfer from V in to V o . LLC circuit is controlled at constant frequency. Thus, the secondary-side voltage V o,LLC is calculated in (11): At the freewheeling state, the primary-side leg voltage v ac or v bc is zero and diode D 5 is forward biased. Thus, the rectifier terminal voltage V R = V o,LLC . The primary inductor voltage v LR = −n p1 V o,LLC /n s1 (low input-voltage region) or v LR = −2 × n p1 V o,LLC /n s1 (high input-voltage region) and the primary current i LR will decrease to zero at the freewheeling state. Due to LLC circuit is controlled under the inductive impedance, S 5 and S 6 can turn on at zero voltage. Due to voltage-second balance on L o , V o is derived in (2).
d eff is the effective duty cycle and k = 1 (or 2) under the high (or low) input-voltage region. From Equation (12), the proposed converter has a voltage gain as Equation (13).
If the proposed converter does not use LLC resonant circuit at lagging-leg (S 5 and S 5 ), then the voltage gain of three-leg converter without LLC converter is derived as: The voltage gains of the presented circuit and conventional PWM converter are compared and provided as: From Equation (15), the presented circuit has a much larger voltage gain. The power ratings of LLC circuit and full bridge circuit in the presented converter are given as: In steady state, the ripple currents ∆i Lo of conventional PWM converter and the presented converter are expressed as From Equations (18) and (19), the ripple current comparison is given as.
∆i Lo,proposed ∆i Lo,con That means the presented converter has less ripple current ∆i Lo . The voltage ratings of S 1 −S 6 and Q are equal to V in,max . The voltage rating of D 1 and D 2 is approximately equal to V in,max /(n p1 /n s1 ). Similarly, the voltage rating of D 3 and D 4 is approximately equal to V in,max /(n p2 /n s2 ). The voltage stress of D 5 is V in,max /(n p1 /n s1 ) − V in,max /(n p2 /n s2 ). The DC diode currents of

Experimental Results
The laboratory prototype with a rated power P o = 800 W is built and tested. The circuit components of the laboratory prototype are provided in Table 1. Figure 5 gives the control block of the studied converter. The general purpose PWM integrated circuit UCC3895 is selected to generate the necessary PWM waveforms to drive the leading and lagging leg switches. A comparator with ±30 V voltage tolerance is adopted in control block to decide low voltage input or high voltage input range. The reference voltage of Schmitt voltage comparator is designed at 270 V. Thus, the actual low and high voltage input ranges are V in,L =120-300 V and V in,H = 240-600 V. Figure 6 gives the experimental test bench. The digital oscilloscope Tektronix TDS3014B, the dc electronic load Chroma 63112A, and the dc power source Chroma 62016P-600-8 are used in the laboratory test to measure the experimental results. Figure 7 provides the experimental results at the low voltage region (V in,L = 120-300 V) and full load. Figure 7a,b gives the experimental PWM signals of S 3~S6 for 120 and 300 V, respectively. The leg voltage v bc , primary currents i LR and i Lr , and resonant voltage v Cr under 120 V input case are provided in Figure 7c. Similarly, the measured waveforms of v bc , i LR , i Lr , and v Cr under 300 V input case are shown in Figure 7d. Comparing Figure 7c,d, the leg voltage v bc at V in = 300 V has less duty ratio. Since the secondary-side voltage V o,LLC is connected to the rectified terminal V R , the inductor voltage v LR at the circulating state is negative and i LR will decrease to zero in this state. Figure 7e,f demonstrates the measured waveforms of i D1 , i D2 , i D5, and i Lo for V in = 120 and 300 V cases. One can observe that the PWM converter has less duty cycle and more ripple current ∆i Lo on L o under V in = 120 V input case in Figure 7d,f. Figure 8a provides the PWM signals of S 3 (the leading-leg switch) at V in = 120 V input and P o = 20% rated load. In the same manner, the measured PWM waveforms of S 3 at V in = 120 V input and P o = 100% rated load are provided in Figure 8b. Figure 8c,d illustrates the test waveforms of S 3 under V in = 300 V input and 20% and 100% rated loads, respectively. The PWM waveforms of S 5 for different input voltages (V in = 120 and 300 V) and different loads (20% and 100% loads) are provided in Figure 8e-h. From Figure 8, it is clear that active switches S 3 and S 5 can both turn on at ZVS for 120 and 300 V input cases. Likewise, the test waveforms at high voltage input (V in = 240-600 V) and the rated power are given in Figure 9. Since S 3 and S 4 are off under high voltage input condition, only PWM waveforms of S 1 , S 2 , S 5, and S 6 are shown in Figure 9a,b for 240 and 600 V, respectively. The measured leg voltage v ac , primary currents i LR and i Lr and resonant voltage v Cr for 240 and 600 V inputs are given in Figure 9c,d, respectively. It can be noted in Figure 9d, i LR will decrease to zero during the circulating interval. The experimental waveforms of i Lo , i D5 , i D2, and i D1 for V in = 240 and 600 V are illustrated in Figure 9e,f. The hysteresis voltage comparator is used in the control block and the reference voltage is designed at 270 V with ±30 V voltage tolerance. Figure 10a,b shows the PWM signals of S 1 under 240 V input and different load conditions (20% and 100% rated loads). Figure 10c,d provides the test waveforms of S 1 under 600 V input and different loads (20% and 100% loads). The PWM signals of S 5 at different input voltages (V in = 240 and 600 V) and different load conditions (20% and 100% loads) are provided in Figure 10e-h. It can be noted that S 1 and S 5 all turn on under zero voltage. Figure 11 gives the test PWM waveforms of Q, S 1, and S 3 during the input voltage variation between V in = 120 and 600 V. When V in increases from 120 to 600 V, Q turns on and S 3 turns off at V in = 300 V. At the same time, S 1 is activated at V in > 300 V. On the other hand, Q and S 1 turn off and S 3 is activated at V in = 240 V when V in decreases from 600 to 120 V. The measured efficiencies of the proposed converter at the rated power are 89.7%, 91.2%, 90.9%, and 93.4% under V in = 120, 240, 300. and 600 V, respectively. Using thermal imaging camera FLIR E85, the measured junction and case temperatures of power MOSFET S 5 at the rated power are 98 • C and 85 • C. The junction and case temperatures of rectifier diode D 1 are 102 • C and 90 • C. The measured core and winding temperatures of filter inductor L o with MPP core CM343125 are 87 • C and 82 • C, respectively, at the rated power.             (e) (f) Figure 9. Measured PWM signals at full load and high input-voltage range (a) S1, S2, S5, S6 at Vin = 240 V, (b) S1, S2, S5, S6 at Vin = 600 V, (c) vac, iLR, vCr, iLr at Vin = 240 V, (d) vac, iLR, vCr, iLr at Vin = 600 V, (e) iD1, iD2, iD5, iLo at Vin = 240 V, (f) iD1, iD2, iD5, iLo at Vin = 600 V.  Figure 10. Measured PWM waveforms of S1 and S5 at the high input-voltage region (a) S1 at Vin = 240 V and Po (b) S1 at Vin = 240 V and Po = 100% load, (c) S1 at Vin = 600 V and Po = 20% load, (d) S1 at Vin = 600 V and Po = 10 S5 at Vin = 240 V and Po = 20% load, (f) S5 at Vin = 240 V and Po = 100% load, (g) S5 at Vin = 600 V and Po = 20% lo Vin = 600 V and Po = 100% load. V in v Q,g v S1,g v S3,g 300V 240V 2s 20V20V 20V 200V . Figure 11. Measured waveforms of Vin, Q, S1 and S3 between 120 and 600 V input c

Conclusions
A hybrid PWM converter is presented and investigated to achieve w eration (Vin = 120-600 V), ZVS operation for all active devices and low p loss at the freewheeling state. To solve high circulating current drawback full bridge converter, a DC voltage comes from a LLC circuit is used at the tified terminal. Thus, the primary inductor voltage is negative and the circ will reduce to zero during freewheeling state. The other drawback of conv converter is serious switching loss on lagging leg devices. The added LL the same lagging-leg devices as PWM circuit to help the lagging-leg activ turned on at zero voltage. Three-leg PWM circuit structure is used to achiev input operation. The circuit performance is provided through the experim

Conclusions
A hybrid PWM converter is presented and investigated to achieve wide voltage operation (V in = 120-600 V), ZVS operation for all active devices and low primary current loss at the freewheeling state. To solve high circulating current drawback in conventional full bridge converter, a DC voltage comes from a LLC circuit is used at the secondary rectified terminal. Thus, the primary inductor voltage is negative and the circulating current will reduce to zero during freewheeling state. The other drawback of conventional PWM converter is serious switching loss on lagging leg devices. The added LLC circuit shares the same lagging-leg devices as PWM circuit to help the lagging-leg active devices to be turned on at zero voltage. Three-leg PWM circuit structure is used to achieve wide voltage input operation. The circuit performance is provided through the experimental results.